COMPUTER ENGINEERING DEPARTMENT

ACTIVITY 2: VHDL Block Diagram - Flip-flop Familiarization and Sequential Circuit Design

2.1 Program Outcomes (POs) Addressed by the Activity

a. ability to design and conduct fieldworks, as well as to analyse and interpret data
b. ability to function on multidisciplinary teams
c. ability to identify, formulate, and solve engineering problems
d. ability to use techniques, skills, and modern engineering tools necessary for engineering practice

2.2 Activity’s Intended Learning Outcomes (AILOs)

At the end of this activity, the student shall be able to:
a. simulate flip-flops operation using VHDL block diagram
b. design circuit block diagram of different sequential circuits such as counters
c. implement sequential circuit design using different types of flip flop
d. verify experimental results versus theoretical results

2.3 Objectives of the Activity

The objective of this activity is to:
a. program flip-flop characteristics and design of clocked sequential circuits using the Quartus II software.
b. generate a vector waveform from the given sample sequential logic circuit

2.4 Principle of the Activity

Flip-flop - is a circuit that has two stable states and can be used to store state information.

Sequential Logic Circuit - is a type of logic circuit whose output depends not only on the present value of
its input signals but on the sequence of past inputs, the input history.

Binary Counter - A counter is a digital sequential logic device that will go through a
certain predefined states (for example counting up or down) based on the application of the
input pulses.

VHDL - Very High Speed Integrated Circuit Description Language.

Quartus II - is software that provides a complete, multiplatform design environment that easily adapts to
your specific design needs.

2.5 Materials/Equipment

1 PC unit
1 Keyboard and Mouse

2.6 Procedure/s

A. Apply the necessary inputs of the given circuits/problem statement and record your result.

2.7 Activity Report

2.7.1 Data and Results

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 1. Circuit:
use clock overwrite: sw2=4us, sw3=2us, key0=1us, sw0=2us, sw1=8us.
Use grid size = 1us and end time = 16us
SW2

SW0 J
SET
Q LEDR0
KEY0
SW1 K CLR Q LEDR1

SW3
FIGURE 4-2. JKFF
Block Diagram:

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 Waveform:

Truth Table

0 0 Pulse 0 0 0 0
0 1 Pulse 1 1 0 1
1 0 Pulse 2 0 0 0
1 1 Pulse 3 1 0 0
0 0 Pulse 4 0 0 0
0 1 Pulse 5 1 1 1
1 0 Pulse 6 0 1 0
1 1 Pulse 7 1 1 0
0 0 Pulse 8 0 1 0
0 1 Pulse 9 1 0 1
1 0 Pulse 10 0 0 0
1 1 Pulse 11 1 0 0
0 0 Pulse 12 0 0 0
0 1 Pulse 13 1 1 1
1 0 Pulse 14 0 1 0
1 1 Pulse 15 1 1 0

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 2. Circuit:
use clock overwrite: set=1us, clear=1us, clk=2us
use forcing high to J & K.
Use grid size = 1us and end time = 32us
SET

1 J
SET
Q Q0

CLK

K CLR Q

CLEAR

J
SET
Q Q1

K CLR Q

J
SET
Q Q2

K CLR Q

J
SET
Q Q3

K CLR Q

FIGURE 4-4. BINARY COUNTER

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 Block Diagram:

Waveform:

Truth Table

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 1 1 Pulse 0 1 1 1 1 1 1
1 1 Pulse 1 1 1 0 1 1 1
1 1 Pulse 2 1 1 1 0 1 1
1 1 Pulse 3 1 1 0 0 1 1
1 1 Pulse 4 1 1 1 1 0 1
1 1 Pulse 5 1 1 0 1 0 1
1 1 Pulse 6 1 1 1 0 0 1
1 1 Pulse 7 1 1 0 0 0 1
1 1 Pulse 8 1 1 1 1 1 0
1 1 Pulse 9 1 1 0 1 1 0
1 1 Pulse 10 1 1 1 0 1 0
1 1 Pulse 11 1 1 0 0 1 0
1 1 Pulse 12 1 1 1 1 0 0
1 1 Pulse 13 1 1 0 1 0 0
1 1 Pulse 14 1 1 1 0 0 0
1 1 Pulse 15 1 1 0 0 0 0

3. Problem Statement:
Design a 3 bit Down-Counter Sequential Circuit using T Flip-flops.
use clock overwrite: clk=1us, set=1 and clear = 1
Use grid size = 1us and end time = 8us
Truth Table, Kmap and state equation

0 0 0 1 1 1 1 1 1
0 0 1 0 0 0 0 0 1
0 1 0 0 0 1 0 1 1
0 1 1 0 1 0 0 0 1
1 0 0 0 1 1 1 1 1
1 0 1 1 0 0 0 0 1
1 1 0 1 0 1 0 1 1
1 1 1 1 1 0 0 0 1

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 KARNAUGH MAP KARNAUGH MAP KARNAUGH MAP
TA = (BC)’ TB = C’ TC = 1

Block Diagram:

Waveform:

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 Truth Table

1 1 Pulse 0 1 1 1 1
1 1 Pulse 1 1 1 1 0
1 1 Pulse 2 1 1 0 1
1 1 Pulse 3 1 1 0 0
1 1 Pulse 4 1 0 1 1
1 1 Pulse 5 1 0 1 0
1 1 Pulse 6 1 0 0 1
1 1 Pulse 7 1 0 0 0

2.7.2 Observations

2.7.3 Conclusion/s

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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 2.7.4

Section: TE31 Date Performed: February 8, 2022

Course Code: CPE0027L Date Submitted: February 8, 2022

Course Title: Introduction to HDL

Instructor: Engr. Maribel Misola Activity No.: Formative 2

Student Name: Roxas, Alexis Angel B. Signature:

2.7.5 Rubrics/Rating

Criteria Grade

Activity Conduct (1-5)

Correctness of Command(s)/Program(s) (1-5) x 2

Completeness of Tasks (1-5)

Data Analysis and Results Interpretation (1-5)

Total Score

Mean Score = (Total Score / 5)

Percentage Score = (Total Score/25) * 100

Other Comments:

ACTIVITY 2: VHDL BLOCK DIAGRAM - FLIP FLOP AND SEQUENTIAL LOGIC CIRCUITS
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