© 2002 L.

MacEachern

Wiring Parasitics

Contact Resistance
Measurement and Rules
© 2002 L. MacEachern

Contact Resistance
•Connections between
metal layers and non-
metal layers are called
contacts.
•Connections between
metal layers are called
vias.
•For non-critical design, a
simple lumped
resistance based on
process measurements
is substituted.
• Parasitic Resistance Extraction (PRE) programs typically
model contact resistance as a small network.
© 2002 L. MacEachern

Resistance Magnitude
•Contact resistance
is a function of Component Resistance Typical Use
layout geometry, metal very low power and signal lines
the layers
contacted, and the metal2 very low power lines
particular
manufacturing polysilicon low signal lines and
process. transistor gates
n-type medium signal lines and sources
•Contact resistance diffusion and drains of transistors
is generally p-type medium signal lines and sources
considered “very diffusion and drains of transistors
low”, although it contact very low signal connection
may range from (routing)
10’s of mΩ to 10’s via very low signal connection
between metal layers
of Ω. (routing)
© 2002 L. MacEachern

CMOS Joining Rules

•Typical two-metal-layer process.

n-type p-type
poly metal metal2 Symbol Meaning
diffusion diffusion
n-type
diffusion ü û T C û ü allowed

p-type
û ü T C û û not allowed
diffusion
Transistor
T
poly
T T ü C û formed
contact
C required
metal
C C C ü V via required
V
metal2
û û û V ü
© 2002 L. MacEachern

Effects of Contact Resistance

•Contact resistance is • Propagation delay time can be

an unwanted feature dominated by contact resistance
which must be for 0.1µm CMOS with ρc>2.10-7
accounted for in both Ωcm2
high speed analog
and digital designs.
•As feature size
decreases, the
significance of
contact resistance
contributions to
circuit behaviour
increases.
© 2002 L. MacEachern

Measuring Contact Resistance

•Process Evaluation
Devices (PEDs) are
typically placed on
each wafer.
•Process dependent
parameters are
monitored using these
sacrificial dice. It is
important to maximize
the usage of these
dice.

PED
© 2002 L. MacEachern

“Meander” Contact Chain

•Typical layout for

measuring contact
resistance.
•The metal
resistance and the
secondary layer
(e.g. n-diff)
resistance is also contact
included in the
measurement.
•There is an inherent
n-diff, p-diff, poly
spatial orientation
bias. metal
© 2002 L. MacEachern

The Hilbert Curve

The Hilbert-Peano Curve

is conveniently described
by an L-System using an
initial state of either “L” or
“R” and the paired
transformation rules,

L +RF-LFL-FR+
R -LF+RFR+FL-

(When plotting the curve,

the characters “L” and “R”
are ignored.)
© 2002 L. MacEachern

Hilbert Contact Chains

•The Hilbert-Peano
Curve algorithm
implemented in the
layout package
generates the contact
chain.
•Hilbert-Peano curve
properties reduce
spatial orientation
bias in the
measurements.
© 2002 L. MacEachern

Layout Rules for Contacts

© 2002 L. MacEachern

Basic Definitions
WIDTH :

SPACE :

CLEARANCE :

EXTENSION :

OVERLAP :
© 2002 L. MacEachern

Reserved Mask Names …

NW --- Definition of N-Well
PW --- Definition of P-Well
OD --- Definition of thin oxide for device and interconnection
OD2 --- Definition of thick oxide for 5V device
PO --- Definition of Poly-1 Si for gate and capacitor bottom plate
PO2 --- Definition of Poly-2 Si for resistor and capacitor top plate
3VN --- Definition of NLDD implantation for 3V device
5VN --- Definition of NLDD implantation for 5V device
PP --- Definition of P+ implantation
NP --- Definition of N+ implantation
© 2002 L. MacEachern

… Reserved Mask Names

3VESD --- Definition of ESD implantation for 3V I/O
5VESD --- Definition of ESD implantation for 5V I/O
CO --- Definition of contact window from M1 to OD, PO or PO2
M1 --- Definition of 1st metal for interconnection
VIA1 --- Definition of via1 hole between M2 and M1
M2 --- Definition of 2nd metal for interconnection
VIA2 --- Definition of via2 hole between M3 and M2
M3 --- Definition of 3rd metal for interconnection
VIA3 --- Definition of via1 hole between M4 and M3
M4 --- Definition of 4th metal for interconnection
CB --- Definition of bonding pad
© 2002 L. MacEachern

Contact Rule (156)

Contact Rules
Rule No. Description Layout Rule

Layer : CO --- Contact Window

CO.W.1 Minimum and maximum width of a CO region A 0.4 um

CO.S.1 Minimum space between two CO regions B 0.4 um

CO.C.1 Minimum clearance from a CO on OD region C 0.3 um

to a PO gate

CO.C.2 Minimum clearance from a CO on PO region D 0.4 um

to an OD region

CO.E.1 Minimum extension of an OD region beyond E 0.15 um

a CO region

CO.E.2 Minimum extension of a PO region beyond a F 0.2 um

CO region

CO.E.3 Minimum extension of a PP region beyond a G 0.25 um

CO region

CO.E.4 Minimum extension of an NP region beyond a H 0.25 um

CO region,

CO.R.1 Poly contact on OD area is forbidden

CO.R.2 Butted Contact is not allowed. I

* Please use fully contacted layout for device source and drain.
© 2002 L. MacEachern

Contact Rules: Reference Layout

PO
OD
E G

PP
CO CO
B

N+
PP
A
NP
H
E E
D N+ PO

F
© 2002 L. MacEachern

I/O Pad Structure

Typical I/O Pad RF Pad
bonding M2 bonding
M2 wire wire

M1 via M1

substrate substrate

M1 & M2 shorted, capacitively M1 & M2 capacitively coupled. M1

coupled to substrate through oxide. shorted to ground. M1 shields M2
Substrate acts as a resistor to from substrate. Capacitance can be
ground, fouling matching and adding tuned out by off-chip inductor.
“resistor” noise.