®

RT9605B

Triple-Channel Synchronous-Rectified Buck MOSFET Driver

General Description
The RT9605B is a high frequency, triple-channel
synchronous-rectified buck MOSFET driver specifically
designed to drive six power N-MOSFETs. The part is
promoted to pair with Richtek's multiphase buck PWM
controller family for high-density power supply
implementation. The output drivers of RT9605B can
efficiently switch power MOSFETs at frequency 300kHz
typically. Operating in higher frequency should consider
the thermal dissipation carefully. Each driver of RT9605B
is capable to drive a 3nF load in 30/40ns rising/falling
time with little propagation delay from input transition to
the gate of the power MOSFET. The device implements
bootstrapping on the upper gate with only an external
capacitor and a diode required. This reduces circuit
complexity and allows the use of higher performance, cost
effective N-MOSFETs. All drivers incorporate adaptive
shoot-through protection to prevent upper and lower
MOSFETs from conducting simultaneously and shorting
the input supply. The RT9605B also detects the fault
condition during initial start-up prior to the multi-phase
PWM controller takes control. As a result, the input supply
will latch into the shutdown state. The RT9605B comes
to a small footprint package with VQFN-24L 4x4 package.
Features
 Drive Six N-MOSFETs for 3-Phase Buck PWM Control
 Adaptive Shoot-Through Protection
 Support High Switching Frequency
 Fast Output Rising/Falling Time
 Propagation Delay 40ns
 Tri-State Input for Bridge Shutdown
 Upper MOSFET Direct Short Protection
 Small 24-Lead VQFN Package
 RoHS Compliant and 100% Lead (Pb)-Free
Applications
 CPU Core Voltage Supplies on Motherboard
 High Frequency Low Profile DC/DC Converters
 High Current Low Voltage DC/DC Converters
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
Pin Configurations
(TOP VIEW)
PHASE1

PHASE2
LGATE1

LGATE2
PVCC1
PVCC2

Ordering Information
RT9605B
24 23 22 21 20 19
Package Type UGATE1 1 18 GND
QV : VQFN-24L 4x4 (V-Type)
BOOT1 2 17 UGATE2
(Exposed Pad-Option 1)
NC 3 16 BOOT2
Lead Plating System GND
PWM1 4 15 PVCC3
P : Pb Free
PWM2 5 14 LGATE3
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with GND 6 13 GND
Halogen Free and Pb free) 7 8 9 10 11 12

Note :
BOOT3
PWM3

UGATE3
VDD

PHASE3
GND

Richtek products are :

 RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020. VQFN-24L 4x4
 Suitable for use in SnPb or Pb-free soldering processes.

Copyright © 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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RT9605B
Typical Application Circuit
PHASE2

L1
0.5µH

R19 2.2 C16

12V 3.3µF
VIN
Q3
1µH
Q1 Q2

C8 C9 D1
1000µF 1µF C15
C1 Optional 5VSB
33pF C2 C10 to C13 C14 1µF R20 C24 to C35
R2 R18 12V 0 1000µF x 12
C4 1500µF x 4 1µF 0
4.7µF
17 19 21 20 3

UGATE2

PHASE2

PVCC2

LGATE2

NC
R1 Q7 PHASE3
C3 R3 3k C23
15k 10nF 3.3nF C36 to C39
R25 10µF x 4
5 3 16 13 16 14 0
BOOT2 LGATE3 Q8
COMP

FB

VDD

PWM1

R4 110k RT9605B C21

VID5 RDROOP 7 15 1µF
6 PWM3 PVCC3 R27
R5 56k PI 15 2.2 L2
VID0 PWM3 5 11 12V 0.5µH
2 DACQ RT8800 PWM2 GND PHASE3 VCORE
R6 27k 14 R26
R11 PWM2 4
UGATE3 10
VID1 0
13k 1.8k GND PWM1 Q9
R7 10
VID2 1 DACFB ISP3 R16 2 9 D3
BOOT1 BOOT3
ICOMMON

R8 6.8k 9 11 Optional PHASE3 C22

PHASE1
UGATE1

LGATE1
VID3 PGOOD ISP2 1µF

PVCC1
R12 C5 1µF R VIN

VDD
ISP1

R9 3.3k
DVD

10k
VID4
RT

R10 5.1k 3.3V R17

R13 27k 4 7 8 12 Optional PHASE2 1 24 22 23 8 R23 10
5VSB
12V R C17 R21
R15 C6 0 12V C18 R22 PHASE1
R14 1µF 1µF
16k 0
3k C19 1µF
1µF
R17 PHASE1 L3
Optional D2 0.5µH
430 R
Q4 Q5
Optional RICOMMON1 C7
RICOMMON2 R24
1µF VIN 2.2 Q6
C20
3.3nF
VCORE

Functional Pin Description

UGATE1 (Pin 1), UGATE2 (Pin 17), UGATE3 (Pin 10) VDD (Pin 8)
Upper Gate Drive Output. Should be connected to the Supply Input. Connect to +5V stand-by power. Place a
upper MOSFET gate. bypass capacitor between this pin and GND.

BOOT1 (Pin 2), BOOT2 (Pin 16), BOOT3 (Pin 9) PHASE1 (Pin 24), PHASE2 (Pin 19), PHASE3 (Pin 11)
Floating bootstrap supply pin for the upper gate drive. Upper driver return. Should be connected to the common
Connect the bootstrap capacitor between this pin and the node of upper and lower MOSFETs. The PHASE voltage
PHASE pin. The bootstrap capacitor provides the charge is monitored for adaptive shoot-through protection.
to turn on the upper MOSFET.
LGATE1 (Pin 23), LGATE2 (Pin 20), LGATE3 (Pin 14)
NC (Pin 3) Lower Gate Drive Output. Should be connected to the lower
No connected. MOSFET gate.

PWM1 (Pin 4), PWM2 (Pin 5), PWM3 (Pin 7) PVCC1 (Pin 22), PVCC2 (Pin 21), PVCC3 (Pin 15)
PWM input control signal. Connect this pin to the PWM Supply Input. Connect to +12V supply. Place a bypass
output of the controller. If the PWM signal enters and capacitor between this pin and PGND.
remains within the shutdown window, are both UGATE
and LGATE are drived low, disabling the output MOSFETs. Exposed Pad
Exposed pad should be soldered to PCB board and
GND (Pin 6, 12, 13, 18 ) connected to GND.
Chip power ground.
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 RT9605B
Function Block Diagram

VDD BOOT1

UGATE1

Short-Through Protection PHASE1

PWM1
PVCC1

LGATE1

GND

VDD BOOT2

UGATE2

Control Short-Through Protection PHASE2

PWM2 Logic PVCC2

LGATE2

GND
BOOT3
VDD
UGATE3

Short-Through Protection PHASE3

PWM3 PVCC3

LGATE3

GND

Timing Diagram

PWM

TPDUGATE TFUGATE
TRUGATE

90% 90%
UGATE 10% 10%
90% 90%
LGATE
10% 10%

TFLGATE
TPDLGATE TRLGATE

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RT9605B
Absolute Maximum Ratings (Note 1)
 Driver Supply Voltage, PVCC ---------------------------------------------------------------------- −0.3V to 15V
 Core Supply Voltage, VDD ------------------------------------------------------------------------- −0.3V to 7V
 BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V
 PHASE to GND
DC -------------------------------------------------------------------------------------------------------- −5V to 15V
< 20ns --------------------------------------------------------------------------------------------------- −10V to 30V
 LGATE
DC -------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VPVCC + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- −2V to (VPVCC + 0.3V)
 UGATE
DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
 PWM Input Voltage ---------------------------------------------------------------------------------- (GND − 0.3V) to 7V
 Package Thermal Resistance (Note 2)
VQFN-24L 4x4, θJA ---------------------------------------------------------------------------------- 67°C/W
 Junction Temperature -------------------------------------------------------------------------------- 150°C
 Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C
 Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------- 150V

Recommended Operating Conditions (Note 4)

 Driver Supply Voltage, PVCC ---------------------------------------------------------------------- 12V ±10%
 Core Supply Voltage, VDD ------------------------------------------------------------------------- 5V ±10%
 Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(Recommended Operating Conditions, TA = 25°C unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

VDD Supply Current
Operation Current IVDD Frequency = 250kHz -- -- 10 mA
Power On Reset
PVCC POR Threshold VPVCC Rising 7.2 8 8.8 V
PVCC Hysteresis -- 1.1 -- V
VDD Threshold VDD Rising 3.7 4 4.3 V
PWM Input
VPWM_IN = 0V 500 600 700
Input Current I PWM A
VPWM_IN = 5V 200 350 500
Floating Voltage VPWMFL 1.4 1.8 2.2 V
To be continued
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 RT9605B
Parameter Symbol Test Conditions Min Typ Max Unit
VPWMRTH PWM_IN Rising 2.7 3.1 3.5 V
PWM Threshold
VPWMFTH PWM_IN Falling 0.8 1 1.3 V
Output
UGATE Rise Time t RUGATE PVCC = 12V, 3nF load -- 80 -- ns
UGATE Fall Time t FUGATE PVCC = 12V, 3nF load -- 40 -- ns
LGATE Rise Time t RLGATE PVCC = 12V, 3nF load -- 40 -- ns
LGATE Fall Time t FLGATE PVCC = 12V, 3nF load -- 25 -- ns
UGATE Turn-Off Propagation Delay t PDUGATE PVCC = 12V, 3nF load -- 30 -- ns
LGATE Turn-Off Propagation Delay t PDLGATE PVCC = 12V, 3nF load -- 25 -- ns
Shutdown Window 0.8 -- 3.5 V
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

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RT9605B
Typical Operating Characteristics
VIN = 12V, unless otherwise specified.
Dead Time Dead Time
Phase 1, Falling Phase 1, Falling
UGATE (5V/Div) VOUT = 1.4V, IOUT = 0A VOUT = 1.4V, IOUT = 30A
UGATE (5V/Div)

PHASE (5V/Div) PHASE (5V/Div)

LGATE (5V/Div) LGATE (5V/Div)

Time (50ns/Div) Time (50ns/Div)

Dead Time Dead Time

Phase 1, Rising Phase 1, Rising
VOUT = 1.4V, IOUT = 0A UGATE (5V/Div) VOUT = 1.4V, IOUT = 30A
UGATE (5V/Div)

PHASE (5V/Div)
PHASE (5V/Div)

LGATE (5V/Div) LGATE (5V/Div)

Time (50ns/Div) Time (50ns/Div)

Dead Time Dead Time

Phase 2, Falling Phase 2, Falling
UGATE (5V/Div) VOUT = 1.4V, IOUT = 0A VOUT = 1.4V, IOUT = 30A
UGATE (5V/Div)

PHASE (5V/Div)
PHASE (5V/Div)

LGATE (5V/Div) LGATE (5V/Div)

Time (50ns/Div) Time (50ns/Div)

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 RT9605B

Dead Time Dead Time

Phase 2, Rising Phase 2, Rising
VOUT = 1.4V, IOUT = 0A UGATE (5V/Div) VOUT = 1.4V, IOUT = 30A
UGATE (5V/Div)

PHASE (5V/Div)
PHASE (5V/Div)

LGATE (5V/Div) LGATE (5V/Div)

Time (50ns/Div) Time (50ns/Div)

Dead Time Dead Time

Phase 3, Falling Phase 3, Falling
UGATE (5V/Div) VOUT = 1.4V, IOUT = 0A VOUT = 1.4V, IOUT = 30A
UGATE (5V/Div)

PHASE (5V/Div) PHASE (5V/Div)

LGATE (5V/Div) LGATE (5V/Div)

Time (50ns/Div) Time (50ns/Div)

Dead Time Dead Time

Phase 3, Rising Phase 3, Rising
VOUT = 1.4V, IOUT = 0A UGATE (5V/Div) VOUT = 1.4V, IOUT = 30A
UGATE (5V/Div)

PHASE (5V/Div) PHASE (5V/Div)

LGATE (5V/Div) LGATE (5V/Div)

Time (50ns/Div) Time (50ns/Div)

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RT9605B

Power On Power On
VOUT = 1.4V, IOUT = 0A VOUT = 1.4V, IOUT = 90A
VOUT (2V/Div) VOUT (2V/Div)

VIN (10V/Div) VIN (10V/Div)

UGATE (20V/Div) UGATE (20V/Div)

LGATE (10V/Div) LGATE (10V/Div)

Time (2.5ms/Div) Time (2.5ms/Div)

Power Off Power Off

VOUT = 1.4V, IOUT = 0A VOUT = 1.4V, IOUT = 90A

VOUT (2V/Div) VOUT (2V/Div)

VIN (10V/Div)
VIN (10V/Div)

UGATE (20V/Div) UGATE (20V/Div)

LGATE (10V/Div) LGATE (10V/Div)

Time (25ms/Div) Time (25ms/Div)

Efficiency vs. Output Curreent

90%
90 VIN = 12V, f = 300kHz
VOUT = 1.45V
88%
88

86%
86
Efficiency (%)

84%
84

82%
82

80
80%

78
78%

76
76%
0 10 20 30 40 50 60 70 80 90 100
Output Curreent (A)

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 RT9605B
Application Information
D1
The RT9605B is designed to drive three sets of both high
d1 s1 L
side and low side N-MOSFET through externally input VIN VOUT
PWM control signal. It has power-on protection function
Cgd1 Cgs1
which held UGATE and LGATE low before PVCC rising
across the threshold voltage. After the initialization, the Igd1 Igs1
Cgd2 d2
PWM signal takes the control. The rising PWM signal Ig1
Ig2 Igd2
first forces the LGATE turns low then UGATE is allowed g1
g2 D2
to go high just after a non-overlapping time to avoid shoot- Igs2
through. The falling of PWM signal first forces UGATE to
Cgs2 s2
go low. When UGATE and PHASE reach a predetermined
GND
low level, LGATE is allowed to turn high. The non-
overlapping function is also presented between UGATE Vg1
and LGATE signal transient. VPHASE +12V

The PWM signal is acted as "High" if above the rising

threshold and acted as "Low" if below the falling threshold.
Any signal level remaining within the shutdown window is
considered as "tri-state", the output drivers are disabled
and both MOSFET gates are pulled and held low. If the
PWM signal floating, the pin will be kept at 2.1V by the
internal divider and provide the PWM controller with a
recognizable level.
The RT9605B typically operates at frequency of 200kHz
to 300kHz. It shall be noted that to place a 1N4148 or
schottky diode between the PVCC and BOOT pin as
shown in the typical application circuit.
Driving Power MOSFETs
The DC input impedance of the power MOSFET is
extremely high. When Vgs at 12V, the gate draws the
current only few nano-amperes. Thus once the gate has
been driven up to "ON" level, the current could be
negligible.
However, the capacitance at the gate to source terminal
should be considered. It requires relatively large current
to source and sink the gate rapidly. It also needs to switch
drain current on and off with high speed. The required gate
drive currents are calculated as follows.
t
Vg2
12V
t
Figure 1. Equivalent Circuit and Associated Waveforms
In Figure 1, the current Ig1 and Ig2 are required to move the
gate up to 12V. The operation consists of charging Cgd
and Cgs. Cgs1 and Cgs2 are the capacitances from gate to
source of the high side and the low side power MOSFETs,
respectively. In general data sheets, the Cgs is referred as
"Ciss" which is the input capacitance. Cgd1 and Cgd2 are
the capacitances from gate to drain of the high side and
the low side power MOSFETs, respectively and referred
to the data sheets as "C rss " the reverse transfer
capacitance. For example, tr1 and tr2 are the rising time of
the high side and the low side power MOSFETs
respectively, the required current Igs1 and Igs2 are showed
,
below :
dVg1 C gs1  12
Igs1  C gs1  (1)
dt t r1
dVg2 C gs2  12
Igs2  C gs2  (2)
dt t r2

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RT9605B
Before driving the gate of the high side MOSFET up to
12V (or 5V), the low side MOSFET has to be off; and the
high side MOSFET is turned off before the low side is
turned on. From Figure 1, the body diode "D2" had been
turned on before high side MOSFETs turned on.
Igd1  C gd1 dV  C gd1 12V
dt t r1
Before the low side MOSFET is turned on, the Cgd2 have
been charged to VIN. Thus, as Cgd2 reverses its polarity
Select the Bootstrap Capacitor
Figure 2 shows part of the bootstrap circuit of RT9605B.
The VCB (the voltage difference between BOOT and PHASE
pins provides a voltage to the gate of the high side power
MOSFET. This supply needs to be ensured that the
MOSFET can be driven. For this, the capacitance CB has
(3)
to be selected properly. It is determined by following
constraints.
VIN
1N4148

and g2 is charged up to 12V, the required current is

BOOT

V  12 +
Igd2  C gd2 dV  C gd2 IN UGATE CB
(4) VCB
dt t r2 PHASE -

It is helpful to calculate these currents in a typical case.

LGATE
Assume a synchronous rectified buck converter, input
GND
voltage VIN = 12V, Vg1 = Vg2 = 12V. The high side
MOSFET is PHB83N03LT whose C iss = 1660pF,
Figure 2. Part of Bootstrap Circuit of RT9605B
Crss = 380pF, and tr = 14ns. The low side MOSFET is
PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and
In practice, a low value capacitor CB will lead the over-
tr = 30ns, from the equation (1) and (2) we can obtain
charging that could damage the IC. Therefore to minimize
Igs1  1660  10  12  1.428 (A)
-12
(5) the risk of overcharging and reducing the ripple on VCB,
14  10 -9 the bootstrap capacitor should not be smaller than 0.1μF,

Igs2  2200  10  12  0.88 (A)

-12 and the larger the better. In general design, using 1μF can
(6)
30  10 -9 provide better performance. At least one low-ESR capacitor
should be used to provide good local de-coupling. Here,
from equation. (3) and (4) to adopt either a ceramic or tantalum capacitor is suitable.

Igd1  380  10  12  0.326 (A)

-12 Power Dissipation
(7)
14  10 -9 For not exceeding the maximum allowable power
500  10 -12
 (12  12) dissipation to drive the IC beyond the maximum
Igd2   0.4 (A) (8)
30  10 -9 recommended operating junction temperature of 125°C,
it is necessary to calculate power dissipation appro-
priately. This dissipation is a function of switching
the total current required from the gate driving source is
frequency and total gate charge of the selected MOSFET.
Ig1  Igs1  Igd1  (1.428  0.326)  1.745 (A) (9) Figure 3 shows the power dissipation test circuit. CL and
Ig2  Igs2  Igd2  (0.88  0.4)  1.28 (A) (10) C U are the UGATE and LGATE load capacitors,
respectively. The bootstrap capacitor value is 1μF.

By a similar calculation, we can also get the sink current

required from the turned off MOSFET.

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 RT9605B
1µF
10 1N4148 CBOOTx Over Voltage Protection Function at Power On
12V
12V
An unique feature of the RT9605B is the addition of over
BOOTX voltage protection in the event of upper MOSFET direct
VDD UGATEX 2N7002
CU
shorted before power on. The RT9605B detects the fault
1µF
RT9605B 3nF condition during initial start-up, the internal power on OVP
PHASEX sense circuitry will rapidly drive the low side MOSFET on
2N7002
before the multi-phase PWM controller takes control.
PWM PWMX LGATEX 20
CL
GND Figure 5 shows the measured waveforms with the high
3nF
side MOSFET directly shorted to 12V.
Figure 3. Test Circuit (One Phase is Shown)

Figure 4 shows the power dissipation of the RT9605B as

+12V
a function of frequency and load capacitance. The value of
the CU and CL are the same and the frequency is varied
from 100kHz to 1MHz. PHASEX

The operating junction temperature can be calculated from

the power dissipation curves (Figure 4). Assume LGATEX
VDD = 12V, operating frequency is 200kHz and the
VCORE
CU=CL=1nF which emulate the input capacitances of the
high side and low side power MOSFETs. From Figure 4, Figure 5. Waveforms at High Side MOSFET Shorted
the power dissipation is 100mW. For RT9605B, the
Please note that the +12V trigger point to RT9605B is at
package thermal resistance θJA is 67°C/W, the operating
3V, and the clamped level on PHASE pin is at about 2.4V.
junction temperature is calculated as :
Obviously since the PHASE pin voltage increases during
TJ = (67°C/W x 100mW) + 25°C = 31.7°C (11)
initial start-up, the VCORE increases correspondingly, but
where the ambient temperature is 25°C. it would quickly drop-off following the voltage in LGATE
The method to improve the thermal transfer is to increase and +12V.
the PC board copper area around the RT9605B firstly. Layout Consideration
Then, adding a ground pad under IC to transfer the heat to
Figure 6 shows the schematic circuit of a two-phase
the peripheral of the board.
synchronous buck converter to implement the either phase
Power Dissipation vs. Frequency of RT9605B. The converter operates at VIN 12V.
1000
CU=CL=3nF R1
900 10
12V
C4
Power Dissipation (mW)

800 1µF
L1
700 1.2µH D1
VIN
600 12V
+

C2
500 C1 1µF
1000µF
400 CU=CL=2nF BOOTX PVCCX
CB
300 1µF
Q1 PWMX PWM
200 CU=CL=1nF UGATEX
L2
RT9605B

100 VCORE PHASEX

2µH PHB83N03LT
+

0 C3
0 200 400 600 800 1000 1500µF Q2 PHB95N03LT GND
LGATEX
Frequency (kHz)

Figure 4. Power Dissipation vs. Frequency Figure 6. Sync. Buck Converter Circuit

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RT9605B
When layout the PC board, it should be very careful. The
power-circuit section is the most critical one. If not
configured properly, it will generate a large amount of EMI.
The junction of Q1, Q2, L2 should be very close.
Next, the trace from UGATE, and LGATE to the gates of
MOSFET should also be short to decrease the noise of
the driver output signals. The bypass capacitor C4 should
be connected to GND directly. Furthermore, the bootstrap
capacitors (CB) should always be placed as close to the
pins of the IC as possible. The trace from PHASE to the
common node of the two MOSFETs should be kept wide
since it usually carries large current.

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 RT9605B
Outline Dimension

1 1

2 2

DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min. Max. Min. Max.
A 0.800 1.000 0.031 0.039
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 3.950 4.050 0.156 0.159
Option 1 2.400 2.500 0.094 0.098
D2
Option 2 2.650 2.750 0.104 0.108
E 3.950 4.050 0.156 0.159
Option 1 2.400 2.500 0.094 0.098
E2
Option 2 2.650 2.750 0.104 0.108
e 0.500 0.020
L 0.350 0.450 0.014 0.018

V-Type 24L QFN 4x4 Package

Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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