SattBus
Interface Circuit
The SattBus Interface Circuit is
designed to connect a serial
communication bus (operating at 62.5
to 562.5 Kb/s) to a single-chip
microprocessor.
The circuit is a combined FM0
(biphase space) decoder/encoder with a
differential transmitter and receiver.
The typical application would
connect a pulse transformer with a ratio
of 1:1 and an inductance of 30 mH.
The separate TX and RX enable
signals make it possible to perform
loop-back tests.
SattBus has the following main
features:
● a robust communication network for
linking PLCs, process controllers,
intelligent I/O devices, sensors...
● up to 120 nodes over a distance of
2000 meters can be connected. The
distance can be increased by use of
fiber and fiber modems.
● installation and configuration of
SattBus is very simple to perform.
unshielded twisted-pair cable is used.
● being the ideal solution for user’s
seeking a low cost field bus capable of
tolerating harsh environments and
used to collect small amounts of data.
Functions
6
Load line 89 Ω (51 Ω bus)
Load line 158 Ω (120 Ω
5 bus)
Differential Output Voltage (± V)

Specification point
Max. (Vcc = 5.5 V)
4 Typically
Min. (Vcc = 4.5 V)

0
0 20
Output Current (± mA)
Transmitter
The driver has differential three-state
outputs. The minimum differential
output is ±3.5 V at ±30 mA. The outputs
are enabled by /TX-ENABLE.
Watchdog
A watchdog timer limits the
transmission time to 16 ms (at 1 MHz
internal clock) each time /TX-ENABLE
is pulled low to start a transmission.
Clock Oscillator and Divider
Either 4 or 12 MHz crystals can be used
for the system clock. A division factor of
Block Diagram
40 60 80
4 or 12 can be selected to get the internal
clock frequency (usually 1 MHz) or,
alternatively, a 36 MHz oscillator
frequency is possible if an external
crystal oscillator is used.
The crystal (of parallel resonance
type) is connected between the XTAL1
and XTAL2 pins and a capacitor of
22-47 pF is then connected from
XTAL2 to ground. The crystal oscillator
input pin (XTAL1) is sensitive to
external capacitance so no external
capacitance should be connected to the
oscillator input pin. The conductor cable
on the input must be kept short and
distant from the oscillator output and the
buffered clock output.
Receiver and Data Decoder
The receiver has a differential input with
four selectable hysteresis levels
determined by the hysteresis control
pins. The input impedance is typically
40 kΩ in a possible 18 to 100 kΩ range.
The decoder data (tristate) output is
enabled when RX-ENABLE is high. A
carrier detect function is available for
bus activity indication. The signal
CDETECT is released 37 µs (at 1 MHz
internal clock frequency) after the last
carrier zero-crossing event.
Hysteresis HYST1 HYST2
levels
±150 mV 1 1
±250 mV 0 0
±350 mV 1 0
±450 mV 0 1

HYST1 DATA OUT

Receiver Data
HYST2 decoder
RXENABLE

Carrier
detector CDETECT
INPUT
1,2 Watchdog
/TXENABLE

Data
synchronizer DATA IN
Driver

Data encoder

Clock divider CLK 1

CLOCK CONTROL

+5 V CLK 12/4

GND Oscillator

XTAL1 XTAL2
Timing Diagram

16 µs
0 1 0 0 1 1 0
DATAIN
Tsu
/TXENABLE

INPUT 1

INPUT 2

CDETECT

RXENABLE
DATAOUT
0 1 0 0 1 1 0

Typical Application

BUS-IF
10 X1 12
CLK
11 X2 13
0V 1MCL

20 CCN 15
+5V DOUT
14
DIN
8 HYS1
+5V 17
+5V 0V 9 HYS2 RXE
+5V 18
TXE
t° 3 IO1
4 IO2 19
Bus CDET

+5V 0V

CPT
21 33
XTAL1 ALE
32
PSEN
20 11
XTAL2 P30/D
RXD
13
P31
35
EA TXD/CL
14
P32
10
RST/VPD INT0
15
P33
2
0 INT1
3 16
1 P34
4
2 T0
5 17
3 P35
6 P1
4 T1
7 18
5 P36
8
6 WR
9 19
7 P37
RD
43 24
0 0/A8
42 25
1 1/A9
41 26
2 2/A10
40 27
3 3/A11
39 P0/D/A P2 28
4 4/A12
38 29
5 5/A13
37 30
6 6/A14
36 31
7 7/A15

80C31 (PLCC-44)
Pin Descriptions

1 TEST. Digital output pad. Test 11 XTAL2. Oscillator amplifier output.

pin – may not be connected.
2 AVCC. Supply pad. +5 V supply
pin for receiver and transmitter.
3 INPUT1. Digital input/output
pad. Receiver input, driver out-
put (1).
4 INPUT2. Digital input/output
pad. Receiver input, driver out-
put (2).
5 AGND. Supply pad. 0 V supply
pin for receiver and transmitter.
6 GND. Supply pad. 0 V supply
pin for logic.
7 COMPOUT. Test pin – may not
be connected.
8 HYST1. Digital input pad. Hys-
teresis control pin 1.
9 HYST2. Digital input pad. Hys-
teresis control pin 2.
10 XTAL1. Oscillator amplifier
input.
12 CLK12/4. Digital output pad. Clock
oscillator buffered output.
13 CLK1. Digital output pad. Clock out-
20 put. Oscillator frequency divided by
19 4 or by 12.
18 14 DATAIN. Digital input pad. Data
17 input (to be transmitted).
16
15 15 DATAOUT. Digital output pad. Data
1 14 output (from receiver). Tristate
2 13 determined by RXENABLE.
3 12 16 VCC. supply pad. +5 V supply pin
4 11
5 for logic.
6 17 RXENABLE. Digital input pad.
7 Receiver data output enable. High =
8 enable.
9 18 /TXENABLE. Digital input pad.
10 Transmit enable. Low = enable.
19 CDETECT. Digital output pad. Carri-
er detect. High when carrier is
detected.
20 CLOCKCONTROL. Digital input
pad. Clock control. High = divide by
12, low = divide by 4.

Technical Data
Absolute Maximum Ratings
DC supply voltage (VDD) Min. –0.5 V, max. 7.0 V
Input pin voltage (Vin) Min. Vss –0.5 V
Max. VDD +0.5 V
Input pin current (Iin) Min. –100 mA, max. 100 mA
(at 25 °C)
Storage temperature
(Tstrg) Min. –55 °C, max. 85 °C
Electrostatic discharge Max. 1000 V
R = 1.5 kΩ. C = 100 pF
Lead temperature Max. 300 °C for DIL.
Max. 260 °C for SOIC.
T = 10 s
Operating Conditions
DC supply voltage (VDD) Min. 4.5 V, max. 5.5 V
Circuit ground (VSS) Min. 0.0 V, max. 0.0 V
Static supply current
(IDDS) Max. 1 mA
Operating current (IDD) Max. 5 mA. Crystal oscillator
running at 12 MHz, receiver
enabled, transmitter disabled.
Ambient temperature (Ta) Min. –25 °C, max. 70 °C
Inputs/Outputs
Digital input (DI) Non-inverting TTL
(HCTcompatible)
Input low voltage (Vil) Max. 0.8 V
Input high voltage (Vih) Min. 2.0 V
Input low current (Iil) Max. –1.0 µA
Input high current (Iih) Max. 1.0 µA
Digital output (DO) Non-inverting CMOS 4 mA
(HC compatible)
Output low voltage (Vol) Max. 0.4 V
Output high voltage (Voh) Min. 4.0 V
Output low current (Iol) 4.0 mA
Output high current (Ioh) –4.0 mA
Digital output (DO), Non-inverting CMOS 4 mA
tristate (DATAOUT only) (Tristate)
Output low voltage (Vol) Max. 0.4 V
Output high voltage (Voh) Min. 4.0 V
Output low current (Iol) 4.0 mA
Output high current (Ioh) –4.0 mA
Output tristate leakage
current (Ioz) ±10 µA
Order codes
DIP 20 pin package 490024308
SOW 20 pin package 490201908
00000. AE Andersson Grafiska AB. Printed in Sweden 1999.

ABB regional center ABB regional center Americas ABB regional center Germany ABB regional center
Europe and Africa Rochester, USA Munich, Germany Asia Pacific
Västerås, Sweden Phone:+1 716 292 6131 Phone:+49 (0) 89 84000-144 Kuala Lumpur, Malaysia
Phone:+46 (0) 21 34 20 00 Fax:+1 716 273 7014 Fax:+49 (0) 89 84000-100 Phone:+60 (0) 3 973 2685
Fax:+46 (0) 21 13 78 45 Fax:+60 (0) 3 973 9685
Specifications subject to change without notice. 493-0998-11
Printed in Sweden. © 1999 ABB Satt AB. 9910 v. 1-2