11/30/22, 4:32 PM ATPG Simulation Mismatch: Common Problems and Solutions

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ATPG Simulation Mismatch: Common Save This Page

Problems and Solutions

Updated October 31, 2019

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SUMMARY

List of Common Problems and Solutions for ATPG Simulation

Mismatches 

DETAILS

Problem Identify
Categories Implement Solution
Types Problem

Timing Data changes  

and flop
   captures new Fix timing or mask cell.  
  data 
If C6 use C6 settings as described in the DRC
(capture or
      section.

serial shift)
If T24 use T24 settings as described in the
Serial DRC section.
Clock Skew patterns have
  
many failing
    
cycles during
shift
 

Flop output is
X due to
reported
setup/hold
violations

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11/30/22, 4:32 PM ATPG Simulation Mismatch: Common Problems and Solutions

Same
 
behavior as
clock skew
Zero Delay
(caused due
to simulator
issues)

Parallel force Parameters:

too close to SIM_PARALLEL_DELAY_SHIFT_CLOCK
clock pulse
violates setup  
time SIM_PARALLEL_EARLY_FORCE_AND_MEASURE

Parallel Parallel
Shift Cycle release close
to clock pulse parameter:  SIM_DELAY_SCAN_RELEASE
  
violates hold
time

Parallel
release too
close to next parameters: SIM_EARLY_RELEASE

clock pulse           SIM_EARLY_RELEASE_TIME

violates setup
time

 
   
Clock, set, or
Glitch reset have Fix timing problem or mask cell
glitch

  Failing cell is  
supposed to
False and
be part of a Define false or multicycle path in ATPG or
Multicycle
false or read_sdc <sdc_file>
Paths
multicycle
path

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11/30/22, 4:32 PM ATPG Simulation Mismatch: Common Problems and Solutions

No clock
pulse in
waveform
and clock
  pulse in ATPG  

Clock Pulses Clock pulse in Fix OCC/NCP definition and/or pin constraints
waveform
   and no clock   
pulse in ATPG

Clock pulses
in wrong
cycle

Reference  
 
 
clock does
 
OCC/NCP not pulse
Reference
and
Clock Check reference clock is specified correctly in
Internal Reference
OCC/NCP and dofile
Pins clock pulses
 
when it  
       should not

  Wrong  
condition
OCC/NCP statement in Fix condition statements in OCC/NCP
OCC/NCP
definition

Trace back  
  ends at user
defined Fix internal pin constraint to match with
Internal Pin/
internal pin verilog simulation, or fix test_setup sequence
Black Box
or black box to initialize pins to the correct value
pin that is
constrained

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11/30/22, 4:32 PM ATPG Simulation Mismatch: Common Problems and Solutions

   

  Data/clock "set_simulation_options -c6_mask_races on",

race and cell
C6
fails C6 "add_cell_constraint -drc C6", or mask cell as
violation needed

 
 
Scan cell data
  disturbed Never set D1 to ignore. Prefered option is to
outside of fix D1. If not possible set D1 to warning and
D1 Ignored
shift or tool will mask the bad cells with XX
capture, and constraint
 
cell fails D1

DRC
 
   
Clock skew  
 
when
shifting from Add lockup cell between the two clocks or fix
T24
clk1 to clk2 timing
and cell fails
T24

 
 
  Serial
patterns fail Never set K rules to ignore.  Fix K rule
K Ignored
and K rules violations.
are ignored

     

Tool X/Binary Fails on

Settings bidirectional  
Library       pin. Pad cell
has long pull- add_input_constraint -NO_Z -BIDI_Only
            up time for
bidirectional
port

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11/30/22, 4:32 PM ATPG Simulation Mismatch: Common Problems and Solutions

Scan cell
traces back to
add_input_constraint -slow_pad
bidirectional
port

Clock goes X set_xclock_handling X

Clock pulses
set_simulation_options -
together with
set_reset_dominate_port off
set or reset

Select X for set_simulation_options -mux_select_X_sim_X

mux ON

Select X cell
with multiple
set_bus_simulation local
tri-state
drivers

Only
multiple_load
 
patterns are
RAM/ROM
failing Check for wrong memory model or
Model
initialization file
Trace back
 
ends at  
RAM/ROM

 
 
 
Failure on pin
Verify and fix PAD library model -
PAD Model driven by PAD
lcVerify/Libcomp
cell

  Trace back
ends on cell  

Bad Library that behaves

Verify and fix library model - lcVerify/Libcomp
Model different in
simulation
versus ATPG

KB Article ID#
MG607968

CONTENTS
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11/30/22, 4:32 PM ATPG Simulation Mismatch: Common Problems and Solutions
CONTENTS
 
Summary
Only
sequential   Details
patterns are
If the cell needs to be masked always use Related
TX Articles
  failing and
constraint.
there are XX
Other cell ASSOCIATED
COMPONENTS
Settings constraints
Tessent TestKompress
  Chain test
Tessent FastScan
patterns fail
due to set_chain_test -suppress_capture_cycle ON
dummy Is this article helpful?
capture cycle
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Please let us know
 
Test setup your feedback about
initialization this document
  Fix test_setup procedure, optionally use
does not
"expect" statement in test_setup to verify
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initialize the remaining
Setup values are initialized as expected.
design as
 
  expected
Setup

PLL clock Allow extra time for PLL to lock - modify

Design
does not lock test_setup procedure
  
 

   
Simulation
netlist
Design Use correct netlist
different from
ATPG netlist

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