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02 Fundamental of Logic Design
02 Fundamental of Logic Design
EE 811
Advanced Digital System Design
Fundamental of Logic
Design
Learning Objectives
• Review the basic concepts of logic circuits
• Variables and functions
• Boolean algebra
• Minterms and maxterms
• Logic gates
• Synthesis
• Create CMOS logic gates
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x = 0 x = 1
S
Battery x L Light
S
Power
supply x L
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S S
Power
supply x1 x2 L Light
x1
Power Light
g
supply
l S L
x2
x1 S
Power
supply S x3 L Light
x2
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Power
supply x S L
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x1
x2
x1
x1 + x2 x1 + x2 + + xn
x2
xn
(b) OR gates
x x
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xn
x1
x2
x1
x1 + x2 x 1 + x 2 + + x n
x2
xn
A X A B X A B X A B X Logic
0 0 0 0 0 0 0 0 0 0 0 Expression
1 1 0 1 0 0 1 1 0 1 1
1 0 0 1 0 1 1 0 1
1 1 1 1 1 1 1 1 0
Truth
Table
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x
1
x
2 f = x + x x
x 1 2 3
3
1
x
1 0
x 1
2 0
1
A
0
1
B
0
1
f
0 Time
(c) Timing diagram
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x1
x1 x1
x2 x2
x2
(a) x1 x2 = x1 + x2
x1
x1 x1
x2 x2
x2
(b) x1 + x2 = x1 x2
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x1 x2 f = x1 x2
0 0 0
0 1 1
x1
1 0 1
x2 f = x1 x2
1 1 0
x1
x2
f = x1 x2
x1 x2 f = x1 x2
0 0 1
0 1 0
x1
1 0 0
x2 f = x1 x2 = x1 . x2
1 1 1
x1
x2
f = x1 x2
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Example
f ( x1 , x 2 , x3 ) x1 x 2 x3
Basic functions
• Summary of basic logic functions
• Inversion, AND, OR
• Can be used to implement logic function of any
complexity
x x
0 1
1 0
NOT
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Logic gates
• The basic logic function (operation) can be
iimplemented
l t d electronically
l t i ll with ith
transistors, which is called a logic gate
• A logic gate has one or more inputs and
one output
• schematics
x1 x1
x x x1 x2 x1 + x2
x2 x2
Truth Table
f ( x1 , x 2 , x3 ) x1 x 2 x3
Representations of a logic function:
-- mathematic Algebra expression
x1 x2 x3 y -- Truth Table
0 0 0 1 -- Karnaugh map (next page)
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1 Observations for an n-variable function:
n
1 0 1 0 1) 2 rows in truth table
1 1 0 1 (2n)
1 1 1 2) 2 different n-variable functions totally
1
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Karnaugh Map
x1 x2 x3
x1 x2
0 0 0 m0 x3
00 01 11 10
0 0 1 m1
0 m0 m2 m6 m4
0 1 0 m2
0 1 1 m3 1 m1 m3 m7 m5
1 0 0 m4
1 0 1 m5 (b) Karnaugh map
1 1 0 m6
1 1 1 m7
x1x2
x3
00 01 11 10
0 0 0 1 1
f = x1x3 + x2x3
1 1 0 0 1
x1 x2 x1 x2
x3 x4 x3 x4
00 01 11 10 00 01 11 10
00 00 1
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 10 1 1
x5 = 0 x5 = 1
f 1 = x1 x3 + x1 x3 x4 + x1 x2 x3 x5
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Boolean Algebra
• Axioms of Boolean Algebra
• 0•0=0,
00 0 0 0•1=0,
1 0 11•0=0,
0 0 1 1•1=1
1 1
• 0+0=0, 0+1=1, 1+0=1, 1+1=1
• If x=0, then x=1; if x=1, then x=0
• Single-Variable theorems
• X•0=0, x•1=x, x+0=x, x+1=1, x+x=1, x•x=0
• Multiple-Variable Properties
• Commutative, associative, distributive,
absorption, combining, DeMorgan’s theorem
Properties
• Commutative x y yx
• Associative x ( y z) ( x y) z
• Distributive x y z x y x z
• Absorption x x y x
• Combining x y x y x
• DeMorgan’s theorem x y x y
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f ( x1 , x2 ) x1 x2 x1 x2 x1 x2 f ( x1 , x2 ) x2 x1
Sum-of-Products
• Minterm: any function can be expressed as the sum of
some minterms.
• For a function of n variables, a product term in which each of the n
variables appears once
• Variables either in uncomplemented or complemented form
• For a given row of a truth table, xi of xi =1, xi if xi =0
• Maxterm: any function can be expressed as the product of
some maxterms.
• For a function of n variables, a sum term in which each of the n
variables appears once
• Variables either in uncomplemented or complemented form
• For a given row of a truth table, xi of xi =0, xi if xi =1
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Sum-of-Products, Product-of-sums
SOP POS
f ( x1 , x2 , x3 ) m(1,4,5,6) f ( x1 , x2 , x3 ) M (0,2,3,7)
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Transistor as a switch
• Concept of switch
• Signals are assumed to have only 2 possible
values(0,
l (0 andd 1)
• The basic element is a switch which has two states
• The switch state is controlled by an input variable x
• Switch is open if x=0; closed if x=1
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T1 T2
T1
Vf
Vx Vf Vx T3 x1 x2 T1 T2 T3 T4 f
1
0 0 on on off off 1
T2 0 1 on off off on 1
Vx T4 off on on off
2 1 0 1
1 1 off off on on 0
PDN
(a) Circuit (b) Truth table and transistor states
• PUN: PMOS x1
y
• PDN:
PDN NMOS x2
Switch network
• Output Vf is GND
V DD
selectively connected
either to Vdd through
PUN or to Gnd Pull-up network
(PUN)
through PDN
PDN,
Vf
depending on inputs Vx
1
Pull-down network
(PDN)
Vx
n
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F f=1
For f 1
f x1 x2 x3
f x1 ( x2 x3 ) For f=0
Vf
Vx
1
Vx
2
Vx
3
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Exercise ?
• Create CMOS gate for function
f x1 ( x2 x3 x4 )
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MSI Devices
• Medium Scale Integration (MSI) devices are digital devices that are build
using a few tens to hundreds of logic gates
gates.
• Full Adders
0 0 0 0
0 1 0 1 0 1 0 1
BCD/DEC
Y0
Y1
A0 Y2
Y3
A1 Y4
A2 Y5
A3 Y6
Y7
Y8
Y9
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Decoders
• A decoder is a combinational digital circuit with a number of inputs ‘n’ and a
number of outputs ‘m’, where m= 2n
• Only one of the outputs is enabled at a time. The output enabled is the one
specified by the binary number formed at the inputs of the decoder.
• On the circuit below,
below the inputs of the decoder are connected on three
switches, forming the number 5 [(101)2], thus only the lamp #5 will be ON
1 1 1 0 1 2 3 4 5 6 7
0 0 0
0 1 0 1 0 1
3/8 DEC.
Y0
Y1
A0
Y2
A1 Y3
Y4
A2
Y5
Y6
Y7
2 to 4 Line Decoder:
2-to-4 Line Decoder
2/4 DEC A1 A0 Y0 Y1 Y2 Y3 Y0 = A1 A0 Y0
Y0 0 0 1 0 0 0 Y1 = A1 A0 A1
A1 Y1
Y1 0 1 0 1 0 0 Y2 = A1 A0
A0 Y2 Y2
1 0 0 0 1 0 Y3 = A1 A0
A0
Y3 1 1 0 0 0 1 Logic Y3
Expressions
Logic Symbol Truth Table Logic Circuit
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3 to 8 Line Decoder:
3-to-8 Line Decoder with Enable Input
3/8 DEC E A1 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0
Y0 0 X X X 0 0 0 0 0 0 0 0
A2 Y1
Y1 1 0 0 0 1 0 0 0 0 0 0 0
A2 Y2 Y2
1 0 0 1 0 1 0 0 0 0 0 0
A1 Y3 1 0 1 0 0 0 1 0 0 0 0 0 Y3
A1
A0 Y4 1 0 1 1 0 0 0 1 0 0 0 0
Y4
Y5 1 1 0 0 0 0 0 0 1 0 0 0
Y5
Y6 1 1 0 1 0 0 0 0 0 1 0 0 A0
E Y7 1 1 1 0 0 0 0 0 0 0 1 0 Y6
1 1 1 1 0 0 0 0 0 0 0 1
Y7
E
Logic Symbol Truth Table Logic Circuit
Multiplexers
• A multiplexer is a device that has a number of data inputs “m”, and number
of control inputs “n” and one output, such that m=2n. The output has always
the same value as the data input specified by the binary number at the
control inputs.
• The rotary switch (selector) shown in figure (a) below
below, is equivalent to a 4-
4
to-1 multiplexer.
• The sliding switch shown in figure (b) below, is equivalent to an 8-to-1
multiplexer.
I2 I0 I1 I2 I3 I4 I5 I6 I7
1
1
I1
0
Y 8/1 Mux
I0
1 4/1 Mux
0
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2-to-1 Multiplexer
2/1 MUX S I1 I0 Y
I0
I0 0 0 0 0
Y I1I0
I1 0 0 1 1 S 00 01 11 10 1/2 Dec.
S 0 1 0 0 0 0 1 1 0 S Y
Logic Symbol 0 1 1 1 1 0 0 1 1
1 0 0 0
S Y 1 0 1 0 I1
Y= S I0 + S I1
0 I0 1 1 0 1
1 I1 1 1 1 1
Logic Expression Logic Circuit
Logic Function Truth Table
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A3 B3 A2 B2 A1 B1 A0 B0
Cout
S3 S2 S1 S0
• Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder
shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}.
Magnitude Comparator
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D J Q Q D J Q Q
CLK CLK
K Q Q K Q Q
Logic Symbol CLK D QN+1 Function Logic Symbol CLK D QN+1 Function
D Q X Q D Q X Q
CLK 0 CLK 0
0 0
Q Q 1
1 1 1
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Two extra inputs are often found on flip flops, that either clear or preset
the output. These inputs are effective at any time, thus are called
asynchronous. If the Clear is at logic 0 then the output is forced to 0,
irrespective of the other normal inputs. If the Preset is at logic 0 then
the output is forced to 1, irrespective of the other normal inputs. The
preset and the clear inputs can not be 0 simultaneously. In the Preset
and Clear are both 1 then the flip flop behaves according to its normal
truth table. Positive Edge JK Flip Flop with Preset and Clear
CLK CLK
J J
K K
CLR CLR
PR PR
Q Q
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2-to-1 SET
MUX
D Q
A1
CLR Q
Clock
1 2 3 4 5 6 7 8 9 10
Clock
A0
A1
D
Q
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Homework
• Problem 2.6 to 2.10
• Problem 2.7 to 2.11
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