Verification Techniques of FPGA Designs

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Verification Techniques For

FPGA Designs
Oct. 8, 2008
By Premduth Vidyanandan, Xilinx Inc.,
Longmont, CO, duthv@xilinx.com
With
the increasing size and complexity of
FPGA devices, there is a need for more
efficient verification methods. Timing
simulation can
Staff
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Add Hydrogen to the
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By Premduth Vidyanandan, Xilinx

11 Myths About Using
Inc., Longmont, CO, duthv@xilinx.com KeysFormal Verification
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Delivering 3D IC innovations faster
With the increasing size and
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Managing Cardlevel netlist challenges for 3D IC
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complexity of FPGA devices, there is a
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Trusted industry leading content to take with you, every Ga in U n l im it ed
need for more efficient verification
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methods. Timing simulation can be the MOST READ
most revealing verification method;
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designs. Timing simulations that

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traditionally were measured in the Tracing to
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multiple days or weeks requiring high-
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One of the biggest challenges that management and…
FPGA design and verification engineers

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face today is time and resource deliver a
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speed, density and complexity, there is

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but also on computer processors and
available memory to complete a full

timing verification. Furthermore there
is an escalating challenge for the
design and verification engineer

(which many times can be the same
person) to get proper testing of today’s

FPGA designs in shorter timeframes Keys to Faster Innovation
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with an increased confidence of first- free articles
pass success.
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of leading
Timing content to take with you, every
Simulation Ga in U n l im it ed
Today’s FPGAs need both functional
and timing simulation in order to

ensure that designs work and continue
to work. FPGA designs are growing in

complexity and the traditional
verification methodologies are no

longer sufficient. In the past,
simulation was not an important stage
in the FPGA design flow. Currently,

however, it is becoming one of the
most critical. Timing simulation is

especially important when designing
with the more advanced FPGAs such as

the Virtex-5 FPGA Family from Xilinx.
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Traditional FPGA verification methods Managing system level netlist challenges for 3D IC
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1. Functional simulation
Functional simulation is a very
important part of the verification
process, but it should not be the only
part. When doing a functional

simulation it will only test for the
functional capabilities of the RTL
design. It does not include any timing
information, nor does it take into
consideration changes done to the

original design due to implementation
and optimization
2. Static Timing Analysis / Formal
Verification
Most engineers see this as the only
analysis needed to verify that the
design meets timing. There are a lot of
drawbacks to using this as the only

timing analysis methodology. Static
analysis cannot find any of the
problems that can be seen when
running a design dynamically. This
analysis will only be able to show if the

design as a whole can meet setup and
hold requirements and generally is
only as good as the timing constraints
applied. In a real system, dynamic Keys to Faster Innovation

4 remaining
factors can cause timing violations on free articles
the FPGA. One example of this would
be Block Ram collisions. With the assemblies in advanced package designs
day.
introduction of Dual Port Block Rams Ac c es s Powered By:
in FPGA devices, care should be taken
not to read and write to the same
location at the same time, as this will
result in incorrect data being read
back. Static analysis tools will never be
able to find this problem. Similarly if

there are misconstrued timespecs,
static timing analysis will not be able to

find this problem.
3. In-System Testing
Virtually every engineer relies on this
method as the ultimate test. If the

design works on the board and passes
the test suites, then it is ready to be
released. This is definitely a very good

test, but it may not catch all the
problems right away. At times the
design needs to be run for quite some

time before corner-case issues will
manifest. Issues like timing violations

may not manifest themselves in the
same way in all chips. Usually by that
time the design is in the end-

customer’s hands. This means high
costs, downtime and frustration to try

to figure out the problem. In order to
get proper in-system testing
completed, all the hardware hurdles
will need to be overcome such as
problems with SSO, cross talk and Managing system level netlist challenges for 3D IC
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other boardindustry leading
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issues. to take
If there are with you, every Ga in U n l im it ed
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external interfaces that will need to be
connected prior to commencement of
the in-system testing, this will increase
the time to market of the product.
As can be seen from above, the

traditional methods of verification are
not sufficient for a fully verified

system. There is a compelling reason to
do dynamic timing analysis.
· Timing Simulation is the only way in
which dynamic analysis can be done.

Most engineers have compelling
reasons for refusing to do timing
simulation. Some of the main concerns

are:
· It is time consuming
· It takes a lot of memory and
processor power to be able to verify
· There is no way to re-use the
testbench from functional simulation.

New testbenches have to be created
· Debugging the design turns out to be

a chore as the whole netlist is flattened
and there is no way to single out the
problem in a timely manner.
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· Timing simulation shows the worst-
case numbers. The design has enough

slack to not be concerned.
· Not all the sub-modules are coded at

the same site. There is no way to split
out the parts that are coded at each
site, since the designers of these parts

will be the ones who understand the
design better in order to verify it.

4 remaining free
These are valid concerns and that is
articles
why the next section will cover what Managing system level netlist challenges for 3D IC
engineers
Trusted can doleading
industry to overcome some
content of with
to take you, every Ga in U n l im it ed
day. Ac c es s
these hurdles. Powered By:
Obtaining Accurate Results Using
Netgen for Timing Simulation
Xilinx has come up with a

revolutionary method to get Static
Timing Analysis numbers and the

timing numbers out of Netgen for
Dynamic Analysis to match. Running

Netgen with the –pcf switch and
pointing to a valid PCF file will ensure
that the numbers out of the Trce and

Netgen will match.
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All the new Xilinx architectures take
advantage of Relative Minimums for
timing calculations. Using relative mins

means that you will be using Maximum
Clock delay and Minimum Data delay
for setup calculations and vice-versa

for hold calculations. Current
simulators do not support using a

number from the MIN field of the SDF
and another number from the MAX
field of the same SDF file. Due to this

limitation Xilinx requires two separate
simulations—one for Setup and

another for Hold checks.
Netgen writes out the SDF file such

that when a SDFMAX simulation is run,
the maximum clock delays and the
minimum data delays are used.

SDFMAX ensures that a design meets
the setup requirements for the target

device. When a SDFMIN simulation is
run, the minimum clock delays and
maximum data delays are used.

SDFMIN ensures that a design meets
the hold requirements for the target

device. Improving the Timing
Simulation Experience

The commonly used phrase “the whole
is greater than the sum of parts” can
be reversed with respect to timing Managing system level netlist challenges for 3D IC
Trusted
simulation industry leading
to almost say,content to of
“the sum take with you, every Ga in U n l im it ed
day. Ac c es s
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parts is greater than the whole.” This
phrase sums up what this section will
cover. In order to cut down on the time
spent on timing simulation, we will
have to rely on the “divide and

conquer” method. For one big
flattened netlist, any form of

verification will be a time consuming
and tedious task to complete. Hence
the solution is to break the netlist into

smaller components.
This methodology is not revolutionary

to the digital logic world; it is
evolutionary. Ever since HDL has been

around, designers have preferred
component-based simulation instead of

simulation of one big design. The
problem is that there was no way to
propagate this method to the world of
timing simulation. This is no longer the
case with the advancements in keeping

hierarchy throughout FPGA
implementation. The idea behind this
was simple. Most of the designs are
created from smaller blocks and
verification is done on each sub-

module.
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A method was introduced some time

ago called KEEP_HIERARCHY. This
solution allows the design to maintain
hierarchy even if it goes through
implementation. This took a small step
towards improving the timing

simulation solution, but the real
problem it aided in solving was the
debugging stage. Now the design is no
longer a flattened netlist. The back- Keys to Faster Innovation
4 remaining
annotated HDL file has different pieces free articles
of hierarchy that match the original Managing system level netlist challenges for 3D IC
design.industry
Trusted Now if a leading
problem is found
content to take with you, every Ga in U n l im it ed
when doing a timing simulation, it is a
lot easier to debug the problem and
narrow it down to the source of the
issue. As mentioned earlier, this was
only a stepping stone to the full

capabilities of this feature.
The next step for KEEP_HIERARCHY

was the ability to create “Multiple
Hierarchical Files.” This is a feature
that was introduced into the software
tools to be able to write separate
netlists for each piece of the hierarchy

as well as a corresponding SDF
(Standard Delay Format) file. The
introduction of this feature opened the
door for a variety of methods to use
with timing simulation. Once a

different file can be written for each
piece of the hierarchy, each Timing
module looks the same as the RTL
version. This enables the ability to
reuse the testbenches that were used

when doing the functional simulation.
This was a big step in timing
simulation.
Now engineers no longer need to write

a separate testbench just for doing the
timing simulation. If a testbench has
been written for functional
verification, almost no work needs to
be done to re-use the exact same Managing system level netlist challenges for 3D IC
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testbench industry leading
for timing content to
simulation. take with
The you, every Ga in U n l im it ed
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port names at the top level will always
be the same, and this way the
testbenches can be re-used. One of the

main advantages of this sort of design
is that it makes it easier to pinpoint the
problem. In order to understand the
true power of this feature, we will
have to look at a real world example.
Figure 1 - Top Module showing
individual Sub Modules
In Figure 1, Sub Module A is created
first by Engineering Team 1 while Sub

Modules B and C are created by
engineering Team 2 and IP Module D is
purchased from a third party. These
are all created at different times
and/or by different engineers, and

each module is verified with its own
testbench to prove it functions
accurately. Once all the individual
pieces have been successfully verified,
they are assembled for

implementation into the FPGA. This is
usually how the RTL simulation is
done. Now, with the ability to use MHF
(Multiple Hierarchical Files) in
conjunction with KEEP_HIERARCHY, it

is possible to maintain the same
strategy even with timing simulation.
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Using this feature helps solve two of Managing system level netlist challenges for 3D IC
the biggest dilemmas faced assemblies in advanced package designs
by to take with
Trusted industry leading content you, every Ga in U n l im it ed
day. Ac c es s
designers who try to do a timing Powered By:
simulation: 1) the ability to re-use the
testbenches for each module and 2) the
ability to pinpoint the specific module

that is causing the problem. There are
multiple ways in which to run a timing
simulation. Since the top level ports for
each of these modules will remain the
same when using MHF, the RTL

testbenches can be easily reused.
Having the final netlist in a modular

form does enable the user to switch
out different modules for their RTL
equivalents. By doing this, the user will
be able to speed up simulation
runtimes. RTL is almost always

significantly faster than structural
netlists and so, if there is a way to
replace the structural code with RTL
without impacting the functionality of
the design, this should be exercised.

Almost no design will work flawlessly
as soon as it has been implemented.
This is why there is a need for doing a
timing simulation.
Using the same example as above, we

can take a look at how to improve the
speed and the visibility of the complete

design. In order to get the smallest
runtimes, it is ideal to only run timing
simulation on one module at a time. In Managing system level netlist challenges for 3D IC
Trusted
this case industry leading
we would content to take with you, every
run timing Ga in U n l im it ed
simulation on Sub Module A and then
have Sub Modules B, C and D in RTL
form. Once we run timing simulation
and everything works as expected,
then each Sub Module can be switched
out and tested in the same manner.
Using this methodology would also

mean that if a problem were found in
one of the Sub Modules it would be
easy to pinpoint that Sub Module and
send it back to the author to fix. If
multiple Sub Modules exhibit

problems then the added advantage is
that two different engineering teams
could be working on the problems at
the same time.
In the traditional flow, problems found

in one part of the design had to be
fixed before the designer could look at

the other parts of the design. Using the
MHF flow prevents the need for this.
One of the other major complaints
from timing simulation users is that if
the other engineering team is out of

the country then it makes it really
difficult and time consuming to finish
the final verification. This is due to the
fact that a lot of time is lost as well as
the fact that there is a lot of Keys to Faster Innovation

dependency when using 4 remaining free
traditional articles
timing simulation methodologies. With
the MHF methodology, the dependency assemblies in advanced package designs
day.
factor is removed. Using MHF will cut Ac c es s
Powered By:
out a lot of idle time by the different
engineering teams. This will ensure
that the teams are used to their full
efficiency. Having a modular structure

with the netlists also can aid the
verification group as well. In the past
what needed to be done by one
verification engineer can now be split
between groups of verification

engineers. The same ideologies that
can be applied to the development
group can also be applied to the
verification group.
In addition to continuous
advancements in the world of
simulation, there have also been major

advancements in methods of applying
stimulus as well. Designs used to be
extremely small, so an earlier method
of stimulating a design was to toggle
each signal using force files or simple

stimulus at the simulator prompt. With
designs getting more complex, the
need for a better methodology of
applying stimulus arose. This is where
the power of VHDL and Verilog and

came into play. With the introduction
of HDL coding languages, test benches Keys to Faster Innovation
4 remaining
started to get more complex and free articles
compact.
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In this field, leading content
technologies to take with you, every
have arisen Ga in U n l im it ed
such as PSL, SystemC and
SystemVerilog. Coverage of these
languages is beyond the scope of this

article. One disadvantage of these
coding styles is that it is taxing to use
the output of a simulation as the
stimulus to another. Some simulators
support Extended Value Change Dump

Format that allows the user to do
exactly that. The main hurdle with
users not using this method for timing
simulation was that there was no way
to use the output as stimulus as the

port names will change when
everything gets flattened. With MHF
this problem goes away, as there are
now individual modules for which the
stimulus can be applied and so the

output of a module can now be used as
the stimulus of another module for
both RTL as well as timing simulation.
Choosing the Hierarchy
A major part of achieving success in

hierarchical simulation is picking the
hierarchy. There is no given formula
for picking the correct hierarchy. This
is why there is no correct hierarchy or

wrong hierarchy, although there are
some guidelines that can be used when
trying to pick a hierarchy. It is always
good design practice to ensure the Managing system level netlist challenges for 3D IC
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following industry leading
guidelines arecontent
met. to take with you, every Ga in U n l im it ed
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· The design should be fully
synchronous.
· All critical paths should be contained

within one Logic Group (a piece of the
design that can be synthesized
separately). Typically, each Logic
Group is a module in Verilog or an

entity in VHDL that is instantiated in
the top-level of the design.
· All IOB (Input/Output Block) logic

should be at the top-level. Every input
or output of the device should be
declared in the top-level as well as I/O
buffers and I/O tristates. However,

instantiated I/O logic in Logic Group is
acceptable.
· Registers should be placed on all of

the inputs and/or outputs of each Logic
Group. A good design practice is to
make all input signals or all output
signals registered at the Logic Group

boundaries. This ensures that the
critical paths inside of a Logic Group
are maintained and eliminates possible
problems with logic optimization
across Logic Group boundaries. This

rule should be followed consistently Keys to Faster Innovation
4 the
for all hierarchy groups in remaining
design. free articles
· The top-level should contain only Managing system level netlist challenges for 3D IC
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instantiated leading
modules or content
entities,to take with you, every
IOB Ga in U n l im it ed
logic, and clock logic (DCMs, BUFGs,
etc.).
· Logic Groups should be chosen so that

no group is so small that it is trivial or
less relevant to verify separately but

not so large that it becomes unwieldy
to simulate and debug should a
problem arise. There is no exact
formula for this and can change
depending on the design and

requirements for the verification.
· Logic Groups should be selected so

that the portions of design that are
most likely subject to change late in
the design flow are isolated from other
more stable portions of the design. This
allows late design changes to have a

lesser effect on verification runtimes
when properly selected.
Preserving hierarchy should not affect

the performance of the design as long
as the above-mentioned guidelines are
followed. To obtain maximum benefit
from preserving hierarchy, it should
only be applied to blocks in the design

whose ports are needed to be visible
during the gate level simulation. These Keys to Faster Innovation
4 remaining
blocks will typically be the upper-level free articles
blocks in the design that follow the
guidelines listed above. By limiting the assemblies in advanced package designs
day.
preservation of hierarchy to selected Ac c es s Powered By:
blocks, the synthesis and
implementation tools will have more

freedom to optimize the design and
improve performance. Figure 2 below
shows an example of where hierarchy

can be preserved in an example
design.
Figure 2 - Example of choosing
hierarchy for preservation
It should be noted that these are only
guidelines. There is no set rule that

dictates how hierarchy should be
chosen or maintained. It does vary
from design to design as well as from

user to user. It is up to the user to
decide where it makes the most sense

for hierarchy to be maintained for
verification and where it should be
dissolved.
Hierarchical Verification Put to
Practice
In order to quantify the possible
benefits of taking a hierarchical

approach to timing simulation, we will
examine two designs, one VHDL and

one Verilog, both targeting mid-size
Xilinx FPGAs and simulated using the
Model Technology ModelSim SE
simulator for 500 microseconds. These Managing system level netlist challenges for 3D IC
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simulationsindustry
were leading
run oncontent to take
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Xeon machine with 2 GB of RDRAM
memory running on the Linux
operating system. This is a modest

attempt to represent the magnitude
difference this methodology could

represent and is not necessarily
representative of typical simulation
runtimes or memory requirements.
The VHDL design represents a
somewhat typical DSP oriented design

targeting a Xilinx Virtex-4 SX35 FPGA.
We chose to split this design into nine

sub-level pieces and one top-level
piece by placing a KEEP_HIERARCHY
on each desired sub-section. We choose

the most volatile section of code for
this test, in that it is changing

frequently in this part of the design
flow. Performing a relatively simple
simulation and comparing the RTL

simulation time to that of the timing
simulation of the design, we find a

significant increase in runtime and
memory requirements as shown in
Table 1 below. If, however, we take the

approach of just performing a timing
simulation on the portion of the design

that changed, we can reduce the
runtime and memory requirements by Keys to Faster Innovation
24x and 21x respectively.4Even

remaining
if we free articles
choose to verify the entire design using
only the changed section for timing assemblies in advanced package designs
day.
verification, we see only an Ac c es s Powered By:
approximate doubling of runtime and
memory requirements from the full
RTL simulation. This also represents a

large reduction in these requirements
compared to a more traditional full
timing simulation.
Type of VHDL Verilog

simulation Design Design
Runtime /
Runtime
Simulation Simulatio
Memory Memory
Full RTL 18.1

6.4 minutes
Simulation minutes /
/ 28.8 MB
26 MB
Full Timing 186.2 176.9

Simulation minutes / minutes /
775 MB 742 MB
Timing
28.0
simulation 7.7 minutes
minutes /
of / 35.8 MB
112 MB
subsection
Full
simulation, 13.8 48.9

timing only minutes / minutes /
on 56 MB 134 MB
subsection
Table 1: Runtimes and memory usage
for different styles of simulation for two
FPGA designs
Looking at the Verilog design, which is
a somewhat larger and more complex

data-path style of design, we targeted
the Xilinx Virtex-4 LX80 FPGA. We split

it into 14 sub-levels and one top-level
using the KEEP_HIERARCHY constraint
to enable piece-wise timing simulation.

We see larger runtimes compared to
the VHDL run but similar

improvements for this design.
Performing a timing simulation of just
the section that changed compared to

simulating the entire design saves us
6.3x the runtime and 6.6x the

simulation memory. Simulating the
entire RTL design replacing just the
portion of design that changed with a

timing simulation netlist still shows a
3.6x runtime improvement and a 5.5x

reduction in memory requirements.
In both designs, the coverage for the

changed module is exactly the same
and design debug was easier due to the
faster runtimes and a smaller design to

analyze. The simulator also felt more
nimble likely due to the lighter
memory requirements. We noted that Managing system level netlist challenges for 3D IC
Trusted industry
it is possible leading
a lesser content
machine to take with you, every
(slower, Ga in U n l im it ed
less memory) could be used for this
simulation with this methodology,
which expands the resources available

to verify this design and allows for
parallel runs to further reduce the

overall runtime.
Conclusion
In summary, this article covers
methodologies for advanced

verification with a technology that is
currently available. This is by no
means a revolutionary methodology

but one that either most designers are
not fully aware of or fully understand.

These are techniques that have been
used in the past for different types of
simulation and verification, but may

not have been used to their full
potential. Using hierarchical

simulation can have an immense effect
on how much time and effort it takes
to completely verify a design.

Hopefully, with the aid of this article, it
is possible to accomplish faster and

more efficient timing simulation while
reducing the simulation hardware
requirements for future FPGA designs.
Premduth Vidyanandan is the technical Keys to Faster Innovation

4 Design
marketing engineer for the remaining free articles
Software Group at Xilinx. In this role,
Vidyanandan is responsible for product assemblies in advanced package designs
day.
definition, requirements and education Ac c es s
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for the simulation and verification
solutions within the Xilinx ISE Design
Tools, including the HDL simulation
libraries and ISE Simulator.

Vidyanandan joined Xilinx in 2001 and
has held various positions in customer

and product applications prior to his
current position in technical marketing.
He holds a bachelor’s degree in

electrical engineering from Purdue
University.
Company: XILINX INC.
Product URL: Click here for more

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This article is part of Electronic 2 Download
Design's coverage of the 2022 Flash
Memory Summit.
Samsung Electronics assemblies in advanced package designs
is content to take with
Trusted industry leading you, every
SPONSORED Ga in U n l im it ed
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further bridging the gap between Ac c es s
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compute and storage with its second- Use Real-Time MCUs
to Develop Efficient
generation SmartSSD. EV M t C t l
The first-generation SSD was How Siemens EDA

introduced in late 2020. Paired with helps you engineer a
smarter future faster
flash storage was a Xilinx-designed
Kintex FPGA that unloaded storage- Designing a Modular
Overlay Network for
related computation from the server’s
Industry 4.0
CPU, reducing power and latency
alike.
Samsung said it is upgrading its
second-generation SmartSSD with
AMD’s Xilinx Versal ACAP to reduce the

power consumed by the host system by
up to 70% and CPU utilization by up to

97% compared to traditional SSDs.
The AMD-Samsung hardware falls into

the category of computational storage
devices (CSDs), which offload the CPU
in the server by running repetitive

storage computations such as
compression or encryption locally.
Most of these CSDs come in the form of

an SSD, where CPUs, FPGAs, or other
types of accelerators are embedded in
the same package as the memory

controller. That way, they can directly
access data stored in NAND flash
storage. As the amount of data stashed
in a data
day. center’s storage continues to Ac c es s
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rise, the time it takes to haul data to

the CPU at the heart of a server is
dragging on performance at the

system level.
Computational storage crunches data

as close as possible to where it’s stored
instead of moving masses of it over
networks to a server,
accelerating workloads including
video transcoding or real-time

analytics.
Samsung said the new SmartSSD pays

dividends in areas such as artificial
intelligence (AI) and 5G networks.
According to the company, the new

storage hardware can reduce the time
it takes to process a request to retrieve

data from a database by more than
50%.
Upgrading the Insides
From the outside, the first-generation

SmartSSD was virtually identical to
any standard Samsung NVMe SSD.
But on the inside, the Xilinx Kintex
FPGA had direct access to 4 TB of

NAND flash storage and 4 GB of Keys to Faster Innovation
4 remaining free
SDRAM, plus a Samsung-designed articles
flash-memory controller, with

everything packed in a standard U.2 assemblies in advanced package designs
day.
form factor. Ac c es s Powered By:
With the FPGA placed in close physical
proximity to the storage, the SmartSSD
could run storage-related
computations itself, reducing the

amount of data that must move from
storage to the compute plane.
The second generation of the
SmartSSD is powered by the VM1802,

which belongs to AMD’s Xilinx Versal
Prime ACAP family. The programmable
SoC is packaged with Samsung’s NAND

flash in a compact E3 module.
Versal is a family of heterogeneous

compute platforms that unite scalar
engines (Arm CPU cores), intelligent

engines (DSPs), advanced SerDes for
high-end networking, and the same
breed of programmable logic at the

heart of its FPGAs. The building blocks
share the same SoC with hard cores for

connectivity and security. One of the
primary differences with Xilinx’s SoCs
is a network-on-chip (NoC) that ties

everything together.
The Versal Prime chip at the heart of
the SmartSSD comes packed with dual- Keys to Faster Innovation

4 remaining
core Arm Cortex-A72 CPUs and dual- free articles
core real-time Cortex-R5 CPUs. It

delivers double leading
the programmable assemblies in advanced package designs
Trusted industry content to take with you, every Ga in U n l im it ed
logic as existing Xilinx MPSoCs.
Based on 7-nm process technology, the
Versal processor features four lanes of
PCIe Gen 4 that double the data rate of

PCIe Gen 3. To assist with storage
acceleration, the chip also supports 100
GbE of networking.
The combination of Arm cores,
programmable logic, and high-speed

networking gives the SmartSSD more
smarts. Versal can offload entire

storage-related workloads instead of
having to share the load with a CPU.
The Future of Flash?
Samsung said it rolled out the first-

generation SmartSSD to video
communications platform vendors and
other firms. The second-generation

CSD uses software and intellectual
property (IP) developed by them.
“With the upgraded processing

functionality of the second-generation
SmartSSD, Samsung will be able to

easily address increasing customer
needs in the database and video
transcoding sectors, as we expand the

boundaries of a next-generation
storage market,” said Jin-Hyeok Choi,
head of memory solution products and
development
day. at Samsung. Ac c es s
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One of the obstacles to the widespread
use of computational storage is that

you have to rework software running
in the data center to take advantage of
the additional logic linked to flash

storage.
Samsung is playing the long game with

its SmartSSDs. It is partnering with the
Storage Networking Industry

Association (SNIA) and the standards
group behind the NVMe spec to create
industry-standard interfaces for its

future SmartSSDs and other types of
computational storage.
“Adhering to standards like these
should help computational storage find

a foothold in the expanding
architecture of future data centers,”
said Steven Leibson, principal analyst

at Tirias Research, in a report.
Check out more coverage of
the 2022 Flash Memory Summit.
CONTINUE READING Keys to Faster Innovation


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Verification Techniques of FPGA Designs

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NEW TECHXCHANGES ANALOG POWER EMBEDDED TEST AUTOMATION AUTOMOTIVE DATA

Verification Techniques For

By Premduth Vidyanandan, Xilinx

designs. Timing simulations that

standard desktop computers can now

powered 64-bit servers. This cuts into

FPGA design and verification engineers

speed, density and complexity, there is

available memory to complete a full

is an escalating challenge for the

design and verification engineer

person) to get proper testing of today’s

and timing simulation in order to

to work. FPGA designs are growing in

verification methodologies are no

simulation was not an important stage

in the FPGA design flow. Currently,

most critical. Timing simulation is

with the more advanced FPGAs such as

Keys to Faster Innovation

Managing system level netlist challenges for 3D IC

Keys to Faster Innovation

Functional simulation is a very

important part of the verification

process, but it should not be the only

part. When doing a functional

functional capabilities of the RTL

design. It does not include any timing

information, nor does it take into

consideration changes done to the

2. Static Timing Analysis / Formal

Most engineers see this as the only

analysis needed to verify that the

design meets timing. There are a lot of

drawbacks to using this as the only

analysis cannot find any of the

problems that can be seen when

running a design dynamically. This

analysis will only be able to show if the

hold requirements and generally is

only as good as the timing constraints

applied. In a real system, dynamic Keys to Faster Innovation

location at the same time, as this will

result in incorrect data being read

back. Static analysis tools will never be

able to find this problem. Similarly if

static timing analysis will not be able to

Virtually every engineer relies on this

method as the ultimate test. If the

released. This is definitely a very good

design needs to be run for quite some

manifest. Issues like timing violations

time the design is in the end-

costs, downtime and frustration to try

As can be seen from above, the

not sufficient for a fully verified

do dynamic timing analysis.

· Timing Simulation is the only way in

which dynamic analysis can be done.

simulation. Some of the main concerns

· It takes a lot of memory and