IEEE JOUR�AL OF SOLID-STATE CIRCUITS, VOL. 31, NO.

11, NOVEMRER 1996 1723

Low-Jitter Process-Independent I)LL and

PLL Based on Self-Biased Techniques
John G. Maneatis

Abstract- Delay-Iorked loop (DLL) and phase-Iorked loop

Vee Symmetric
� Load
."'''''''''''''''''''''''''l
(PLJ") designs based upon self-biased techniques are presented.
The DLL and PLL designs achieve process technology inde­
pendence, fixed damping factor, fixed bandwidth to operating Il>-----.�_H �/
frequency ratio, broad frequency range, input phase offset cancel­
I � �
VBP l !
lation, and, most importantly, low input tracking jitter. Both the �,
..
, ..
,....
,....
,..,..
........
.. ....
..." ,.:
.."'...":
. ..,
....:"�

Vo_ Vo+
damping factor and the bandwidth to operating frequency ratio
are �Ietermined c�mpletely by a ratio of capacitances, Self-biasing
aVOids the necessity for external biasing, which can require special
bandgap bias circuits, by generating all of the internal bias
voltages and currents from each other so that the bias levels are
eomJ�letely determined by the operating conditions. Fabricated
in a 0.5-llm ]V -well CMOS gate array process, the PLL achieves
an operating frequency range of 0.0025 MHz to 550 MHz and
input tracking jitter of 384 ps at 250 MHz with 500 m V of low Fig. L Differential buffer delay stage with symmetric loads.
frequency square wave supply noise.

ally all of the process technology and environmental variability

L I.\lTRODCCTION that plagues PLL and DLL designs. Self-biasing can provide
a bandwidth that tracks the operating frequency. This tracking

D
ELAY-LOCKED loops (DLL's) and phase-locked loops
(PLL's) are often used in the I/O intelfaces of clio-ital
bandwidth can in turn provide a very broad frequency range,
"'
minimized supply and substrate noise induced jitter with a high
integrated circuits in order to hide clock distribution delays and
to improve overall system timing. Tn these applications, DLL's
input tracking bandwidth, and, in general, very robust designs.
Other benefits include a fixed damping factor for PLL's and
and PLL's must closely track the input clock. However, the
input phase offset cancellation. Both the damping factor and
rising demand for high-speed I/O has created an increasingly
the bandwidth to operating frequency ratio are determined
noisy environment in which DLL's and PLL's must function,
completely by a ratio of capacitances giving effective process
This noise, typically in the form of supply and substrate noise,
technology independence. The key idea behind self-biasing
tends to cause the output clocks of DLL's and PLL's to jitter
is that it allows circuits to choose thc operating bias levels
from their ideal timing. With a shrinking tolerance for jitter in
in which they function bcst. By referencing all bias voltages
the decreasing period of the output clock, thc design of low
and currcnts to other generated bias voltages and currents,
jitter DLL's and PLL's has becomc very challenging.
thc opcrating bias levels are essentially established by the
Achieving low jitter in PLL and DLL designs can be
operating frequency, The need for external biasing, which can
difficult due to a number of design tradeoffs. Consider a
require special bandgap bias circuits, is completely avoided.
typical PLL which is based on a voltage controlled oscillator
This paper will bcgin by reviewing a differential buffer
(VCO). The amount of input tracking jitter produced as a
stage design that provides high supply and substrate noise
rcsult of supply and substrate noise is directly related to how
rejection and allows tile pos:,ibility of self-biasing. The loop
quickly the PLL can correct the output frequency. To reduce
architecture for self-biased DLL and PLL designs will be pre­
the j Jitter, the loop bandwidth should be set as high as possible,
sented in Section III and Section IV, respectively. A number
Unfurtunately, the loop bandwidth is affected by many process
of other loop components are critical to achieving low jitter in
technology factors and is constrained to be well below the
DLL and PLL designs. Section V will describe an improved
lowest operating frequency for stability [1]. These constraints
phase-frequency comparator and differential-to-single-ended
can cause the PLL to have a narrow operating frequency range
converter. The paper will also present some experimental
and poor jitter performance. Although a typical DLL is based
results demonstrating the performance of the DLL and PLL
on a delay line and thus simpler from a control perspective, it
designs.
can have a limited delay range which leads to a set of problems
similar to that of the PLL.
II. DIFFERENTIAL BUFFER STAGE
This paper describes both a DLL and PLL design based
upon self-biased techniques [2J. Self-biasing can remove virtu- In order to achieve low jitter operation, DLL and PLL

1996: revised July 29, 1996.

designs require buffer stage designs with low supply and
Manuscript received May 3,
The au thor is with Silicon Graphics, Inc . . Mountain View, CA 94043. suhstrate noise sensitivity. The voltage-controlled delay line
Publisher Hem Id e ntifie r S 0018-9200(96)07946-2. (VeDL) ,mel the veo used in the DLL and PLL designs are

0018 9200196$05.00 © 1996 IEEE

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1724
�.,,"'..."" ......"-"-"'....'-'..'-'..-'.,-'..'...""..: "': '�"""...'.." ...",:..:",................., "..,.... ":......:..:,:,:,:..:..:,,...,-',..."" "..... .. ..)'.. ....,...."
� VCTRL
Amplifier Bias
Fig. 2. Replica-feedback current source bias
based upon the ditferential buffer delay stages with symmetric
loads and replica-feedback biasing 131.
The buffer stage, shown in Fig. I, contains a source coupled
pair with resistive load elements called symmetric loads.
Symmetric loads consist of a diode-conncctcd PMOS device in
shunt with an equally sized biased PMOS device. Thc PMOS
bias voltage VBP is nominally equal to VCTRL, the control
input to the bias generator. Because of this equality, VCTRL
will be used instead of VBP in subsequence references to the
PMOS bias voltage. VCTRL defines the lower voltage swing
limit of the buffer outputs. The buffer delay changes with
VCTRL since the effective resistance of the load elements
also changes with VCTRL. It has been shown that these
load elements lead to good control over delay and high
dynamic supply noise rejection. The simple NMOS current
sourcc is dynamically biased with VEN
drain and substrate voltage variations, achieving the effective
performance of a cascade current source, However, this currcnt
source can provide high static supply and substrate noise
rejection without the extra supply voltage required by cascode
current sources.
The bias generator, shown in Fig. 2, produces the bias
and VBP from VCTl1L. Its primary function
voltages 'VEN
is to continuously adjust the buffer bias current in order to
provide the correct lower swing limit of VCTRL for the buffer
stages. In so doing, it establishes a current that is held constant
and independent of supply voltage. It accomplishes this task
by using a differential amplifier and a half-buffer replica. The
amplifier adjusts VBN so that the voltage at the output of the
half-buffer replica is equal to VCT'RLl the lower swing limit. If
the supply voltage changes, the amplifier will adjust to kccp the
swing and thus the bias current constant. The bandwidth of the
bias generator is typically set equal to the operating frequency
of the buffer stages so that the bias generator can track all
supply and substrate voltage disturbances at frequencies that
can affect the DLL and PLL designs. With this bias generator,
the huffer stages have been shown to achieve a static supply
noise rejection of about O.25%/V while operating over a broad
delay range with low supply voltage requirements that scale
with the operating delay, The bias generator also provides
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31. NO. 11, NOVEMBER 1996
1'·'-...." , . �
l !
.. ..''''
.. ....,
...."" ....,.."-"-'''-',, "'..·..'..·....
.. ..
.....,...., "........ ......,·
·,·..." ..·.... ..,...... ......""'...............""'..
� �
Ditt. Amplifier Half-Buffer Replica VCTRL Buffer
circuit.
L-------�--_+Fo
Dls)
Fig 3. . Typical DLL block diagram (clock distribution omitted).
a buffered version of VC'l'KL at the VBP output using an
additional half-buffer replica. This output isolates VCTKL from
potential capacitive coupling in the buffer stages and plays an
important mle in the self-biased PLL design.
Buffer stages with low supply and substrate noise sensitivity
are essential for low jitter DLL and PLL operation. With the
foundation of a buffer stage design with low noise sensitivity,
to compensate for the next two sections will consider techniques for self-biasing
DLL and PLL designs. Such techniques will provide further re­
ductions in input tracking jitter by allowing the loop bandwidth
to be set as close as possible to the operating frequency.
III. SELF-BIASED DELAY-T Df:KRD Loop
A self-biased DLL is constmcted hy taking advantage of
the control relationship offered by a typical DLL. A typical
DLL is ,hown in Fig. 3. It is composed of a phase comparator,
charge pump, loop fllter, bias generator, and voltage controlled
delay line. The negative feedback in the loop adjusts tbe delay
through the VCDL by integrating the phase error that results
between the periodic reference input and the delay line output.
Once in lock, the VCDL will delay the reference input by a
fixed amount to form the output such that there is no detected
phase error between the reference and the output. The VCDL
delay, therefore, must be a multiple of the reference input clock
period. With the chip-wide clock distribution network included
as part of the VCDL delay, the DLL can be used to rebuffer
the input clock signal without adding any effective delay.
A. Closed-Loop Response
The frequency response of the DLL can be analyzed with a
continuous time approximation, where the sampling operation
MANEATIS: LOW-JITTER PROCESS-INDEPENDENT DLL AND I'LL BASED ON SELr-IlIASED TECHNIQUES [725

of the phase comparator is ignored. This approximation holds

\
for handwidths about a decade or more below the operating
frequency. This bandwidth constraint is also required for
stability due to the reduced phase margin near the higher Delay
order poles that result from the delay around the sampled
feedback loop. Because thc loop filtcr integrates the phase
error, the DLL has a first-ordcr closcd loop response. The "'-
VCTRL
rcsponse could be formulated in terms of input phase and
output phase. However, this set of variables is incompatible
with a continuous time analysis since the sampled nature Fig. 4. Typical symmetric load buffer stage delay as a function of control

of the system would need to be considered. A better set of

voltage.

variables is input delay and output delay. The output delay is

the delay between the reference input and the DLL output or,
equivalently, the delay established by the VCDL. The input
delay is the delay to which the phase comparator compares
changes proportionally to
proportional to - -
nonlinear with respect to the control voltage. In fact, the delay
1/(VcTl1L VT), with a slope KDL
l/(VcTRL VT)2 or l/ID, where ID is one
the output delay or, equivalently, the phase difference for half of the buffer bias current.
which the phase comparator and charge pump generate no As the operating frequency is reduced, KDL becomcs largcr,
error signal. The output delay, Do(.s), is related to the input which increases the loop bandwidth relative to the opcrating
delay, DI(S), by frequency. This behavior is undesirablc because the stability

Do(s) = (Dr(s) - Do(s))· FREF·

ICH KD
SCI
L. (I)
of the loop is undermincd at lower frequencies. which in tum
constrains the operating frequency range. Thus, even though
nonlinear control over delay allows a VCDL to have a large
where FREF is the referencc frcqucncy (Hz), ICH is the delay range, stability constraints still lead to a small operating
charge pump current (A), CI is the loop filter capacitance freljuency range for the DLL.
(F), and KDL is the VCDL gain (slY). The product of the The effect on stability for nonlinear control over delay
delay difference and the reference frequency is equal to the can be corrected by applying self-biased techniques. Suppose
fraction of the reference period in which the charge pump i �
activated. The average charge pump output current is eljual lo
this fraction times the peak charge pump current. The output
.
that the charge pump current
bias current 2 ID . The
IeH is set equal to the buffer
1/1D dependence of K D L can
then be cancelled out leading to loop bandwidth that tracks
delay is then eljual to the product of the average charge pump the operating frequency without constraining the operating
current, the loop filter transfer function, and the delay line frequency range.
gain. The closed loop response is then given by With this solution, the DLL design is completely self­

1 biased as all bias voltagcs and currents are referenced to

(2) other generated bias voltages and currents. The bias generator
generates all of the needed biases for the VCDL from VCTRL,
where defined as the loop bandwidth (rad/s), is givcn by and the charge pump uses the current formed by VCTRL

- . -1
WN,

to generate corrections to l/;�TRL. The key difference from

ICH . KDL FREF . . (3)
CI
WN typical DLL designs is that no special bandgap bias circuit or
the equivalent is needed to establish the charge pump current.
If the charge pump current I CH and the VCDL gain KDL
are constant, the loop bandwidth
ing frequency
and CI
WREF.
WN will track the operat­
However, the parameters
are process technology dependent and will causc
Ie H , K D L,
c. Quantitative Analysis

A more detailed analysis will show a very simplc rcsult

for the relationship bctween the loop bandwidth and the
the loop bandwidth to vary around thc dcsign target. In
opcrating frcqucncy. First, a relationship between VCDL gain
addition, constant gain VCDL's are typically implemented
by interpolating between two closely delayed signals with a
and control voltage is needed. Fig. 5 shows a symmetric load
and its typical IV characteri�;tics. The buffer bias current is
2 .
weighted sum which leads to a narrow delay range. Linear
Iv.
It can be shown that the effective resistance of a
symmetric load REFF is directly proportional to the small
rcsults arc obtained only when the delay spacing is less than
the signal edge rate. As the delay spacing increases, the
signal resistance at the ends of the swing range which is just
interpolation becomes increasingly nonlinear. The delay range
one over the transconductance Urn for one of the two equally
can be extended by using a VCDL with nonlinear delay control
sized devices when biased aL VBP or. equivalently, VCTRL.
at the expense of a tracking loop bandwidth.
Thus. the buffer delay can be defined as

B. Bandwidth Tracking

Symmetric load buffer stages can be used to implement

t = REFF . CEFF = -
flm
1
. CEFF (4)

the VCDL in order to obtain a broad delay range. Fig. 4 wherc GEFF is thc effcctivc buffer output capacitance.
shows their typical delay as a function of control voltage. Using a half-buffcr rcplica, the bias generator sets the buffer
The delay can change over a very broad range, but it is bias currcnt cqual to the current through a symmetric load

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1726 IEEE JOUR.'lAL OF SOLlD-STATE CIRCUITS, VOL. 31, NO. 11. NOVEMBER 1996

210

In Phase Reference Early

Fig. 5. Typical symmetric load IV characteristics.
Fig, 6. Phase-frequency comparator waveforms with UP and DN asserted
on every (":yc1e.
with its output voltage at VCTRL. In this case, the two equally
sized PMOS devices are both biased at VCTRL and each source
Thus, the bandwidth to operating frequency ratio is con­
half of the buffer bias current. Since these devices typically
stant and completely determined by a ratio of capacitances
have greater than minimum channel length and are biased with
that can be matched reasonably well in layout, dramatically
moderate voltages, a simple quadratic model can be used for
rcducing the process technology sensitivity of the design. In
addition, the DLL can operate over the same broad frequency
the drain current. The drain current for one of the two equally
sized devices biased at VCTRL is then given by
range achievable by a VCO based on the same buffer stagcs

ID = �. (VCTRL .. VT)2 (5)

operating open loop.

where k is the device transconductance of one of the PMOS D. Zero-Offset Charge Pump
devices. Taking the derivative with respect to VCTRL, the The self-biased DLL design requires a charge pump current
transconductance is given by that will vary several decades over the operating frequency
range. At low current levels, small charge offsets can lead to
gm =k,(VCTRL- VT)= V2.k.ID' (6) significant phase offsets, In addition, all phase comparators

The buffer delay is then given by

will typically assert their UP and DN outputs for equal
durations on every cycle once the loop is in lock. In order to
CEFF achieve zero static phase offset, the charge pump must transfcr
t (7)
no nel charge to the loop filter for these equal duration
= �--,--------c-,-
k· (VCYRL - Vy) UP and
The delay for an n stage VCDL is given by
DN pulses, which requires that the UP and DN currents be
identical and independent of the charge pump output voltage.
CB An XOR phase comparator used for quadrature locking
D . t= - (8)
2' k
= n --c------c-
(VC TRL VT)
-

' - separately asserts its UP and DN outputs t wice per cycle

where CB is defined as
for equal durations. The same is true for a phase-frequency
2· n ' CEFF or, equivalently, the total
comparator (PFC) which is used for in-phase locking. In order
buffer output capacitance for all stages. Taking the derivative
to successfully avoid a dead-band region in the PFC as seen
with respect to VCTRL, the VCDL gain is given hy
by the charge pump, the PFC must assert both UP and DN
dD CB

I I
outputs on cvcry cycle as shown in Fig. 6. A dead-band region
KDL = = -,- --,.'7 - ----

dVcYRL 2 · k' (VCTRL - VT)2

-
is the range of input phasc ditferences for which the PLL takes

CB no corrective action. Such a dead-band region will result in

(9) additional input tracking jitter equal to the magnitude of the
4· ID'
dead-band region. This requirement means that for in-phase
Thus, the gain is inversely proportional lo buffer bias current. inputs, the charge pump will see both its UP and DN inputs
With the relationship for K DL established, the bandwidlh LO
asserted for an equal and short period of time. If in-phasc PFC
operating frequency ratio can be derived, Let the charge pump inputs produce n o UP or DN pulses, then it will take some
current be set to some multiple x of the buffer bias current finite phase difference before a large enough pulse is produced
such that to turn on the charge pump, which leads to a dead-hand region.
If the reference is early with both UP and DN outputs asserted
ICH = x· (2. ID)' (10)
on every cycle, then the difference in duration between the UP
Thc bandwidth to operating frequency ratio is then given by and DN pulses will be equal to the input phase difference.

1 , 1
Self-biasing makes it possible to design a charge pump
WN
. ICH. KDL . FREF . to have zero static phase offset when bolli the UP and
WREF WREF C1
-- = -- -

1 1
DN outputs of the phase comparator are asserted for equal

=211' ·lcH·j{DL·
C1
durations on every cycle with in-phase inputs. By constructing
the charge pump from the symmetric load buffer stage, it
1 CB 1
= - . x . (2 . ID \ . -- . - can be guaranteed that the UP and DN currents for these
211' ) 4· ID C1
.
equal duration pulses completely cancel out and transfer no
1': CB net charge to the loop filter. A simplified schematic for
(l l)
the zero-offset charge pump is shown in Fig, 7, The charge

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MANEATIS: LOW-JITTER PROCESS-INDEPENDENT DLL AND PLL BASED ON SELF-BIASED TECHNIQUES 1727

Vee

Vo Fig. 9. Typical PLL block diagram (clock distribution omitted).

the DLL. A typical PLL is shown in Fig. 9. It is composed of

a phase comparator, charge pump, loop filter, bias generator,
and yeO, Thc key differences from the DLL are that it uses
a veo instead of a delay line and that it requires a resistor in
the loop filter for stability. The negative feedback in the loop
Fig. 7. Simplified schematic of the offset-cancelled charge pump.
adjusts the veo output frequency by integrating the phase
error that results between the periodic reference input and the
divided veo output. Once in lock, the veo will generate an
output with a frequency that is N times larger than that for
the reference input such that there is no detected phase error
between the reference and the divided output. With the chip­
wide clock distribution network added in the feedback path to
the divider, the PLL can be used to mUltiply and rebuffer an
input clock signal without adding delay,

A. Closed-Loop Response

As with the DLL, the frequency response of the PLL

-=- -=-
can be analyzed with a continuous time approximation for
bandwidths a decade or more below the operating frequency.
Fig. 8. Complete schematic of the offset-cancelled charge pump with sym­
This bandwidlh cunstraint is also required for stability due to
metric loads.
the reduced phase margin near the higher order poles that result
from the delay around the sampled feedback loop. Because the
pump is composed of two NMOS source coupled pairs each loop filter integrates the charge representing the phase error
with a separate current source and connected by a current and the veo integrates the output frequency to form the output
mirror made from symmetric load elements. eharge will be phase, the PLL has a second-order closed response. Thc output
transferred from or to the loop filter connected to thc output phase, Po(s), is related to the input phase, P1(s), by
input or DN input, respectively, is switched high.
Po(s) (P1(S) - ( )
when the UP
and DN inputs asserted, the left source­
?o(s)
With both the UP = "1 . ICH . R + __1 . Kv . �
coupled pair will behave like the half-buffer replica in the
N ) sC1 S
bias circuit and produce VCTRL at the current mirror node. The (12)
PMOS deviee in the right source coupled pair will have VCTRL
where ICH is the charge pump CUITent (A), R is the loop filter
at its gate and drain which is connected to the loop filter. This
resistor (n), C1 is the loop filter capacitance (F), and K v is
devic:e will then source the exact same buffer bias current that
the veo gain (Hz/V). The closed loop response is then given
is sunk by the remainder uf the suurce coupled pair. With no
net charge transferred to the loop filter, the charge pump will
have zero static phase offset.
by

Po(S) ( 1 +
S
)-1
=

. S
The complete schematic for the zero-offset charge pump PI(S) N I cH' (Ii + 1/(sC1))· Kv
is shown in Fig. 8. The current mirror is constructed from N (1 + C1 . R)
-
•

(13)
symmetric load elements. Also, the un selected source coupled 1 + s· C1· R+ S2/(ICH/C 1 · Kv/N)
pair outputs are connected to symmetric load elements to
or, equi valentI y, by

--
match the voltages at the other outputs. At this point, all of

Pr(s) - -
the elements necessary to construct a self-biased DLL have ro(s) -N· _ l+2'('(S/WN)
(14)
been considered. The following section shows that similar 1+2 ( (S/WN) + (S/WN)2
self-biasing techniques can be applied to a phase-locked loop, where (, defined as the damping factor, is given by

IV. SELF-BIASED PHASE-LOCKED Loop (= �. J� ,IcH . Kv . R2. C1 (15)

A self-biased PLL, like the self-biased DLL, is constructed
and WN, defined as the loop bandwidth (rad/s), is given by
by taking advantage of the control relationship offered by
typical PLL. However, the control relationship and the 2· (
a
-
W", = -- . (J6)
additions to make it self-biased are more complicated than for R,Cl

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1728 IEEE JOURNAL OF SOLID-STATE CIRCUTS, VOL 31, ]\iO. 11, NOVEMBER 1996

The loop bandwidth and damping factor characterize the

closed-loop response. The PLL is critically damped with a
damping factor of one and overdamped with damping factors

Freq
greater than one.
For a typical PLL, the charge pump current IcB, veo
gain [{v. and loop filter resistance R are constant [4]. These
conditions give rise to a constant damping factor and a

VCTRL
constant loop bandwidth. A constant bandwidth can constrain
the achievement of a wide operating frequency range and low
input tracking jitter. A PLL adjusts its output frequency, not Pig. 10. Typical VCO frequency as a function of control voltage when

its output phase like a DJ J". If the frequency is disturbed,

implemenled wilh symmetric load buffer stages.

the phase error that results from each cycle of the disturbance
will accumulate for many cycles until the loop can correct the
frequency error. The error will be accumulated for a number
of cycles proportional to the operating frequency divided by
the loop bandwidth. Thus, WN should be positioned as close as
possible to WR,"P to minimize the total phase error. In addition,
WN dcpcnds on ICB, [{v, R, and el, but not on WREF. All

Fi g . II. of the
of these parameters havc indcpcndent variability. However,
Transformation the loop filler [or integration of the loop
WN must be a decade below thc lowest operating frequency filter resistor.
for stability. The result is that Wry must bc conservatively
set for stability at the lowest opcrating frequency with worst
case process variations, rather than set for optimizcd jittcr
performance.

B. Bandwidth Tmrking

Ideally, both ( ami Wry /WREF should be constant so that Fig. 12. Complete self-biased PLL block diagram (clock distributIOn omit­
there is no limit on the operating frequency range and so that
led).

the jitter performance can be improved. Ic B could be set equal

to the buffer bias current 2 ·1v as done in self-biasing the DLL current. The integration of such a resistance into the loop filter
but this is not sufficient since ( would change with operating can be accomplished by applying a transformation to the loop
frequency as a result of a square root of Iv dependence. To filter as illustrated in Fig. 11.
keep ( constant with operating frequency, two parameters, The loop filter for a PLL is typically a capacitor in series
such as ICB and R, must vary. ICB can be set equal to with a resistor that is driven by the charge pump current
the buffer bias current and R can be set to vary inversely 6IcB. The control voltage is then the sum of the voltage
proportionally to thc square root of the buffer bias current. ( drops across the capacitor and resistor. The voltage drops
will then remain constant, but Wry will be proportional to the across the capacitor and resistor can be generated separately,
square root of the buffer bias current. as long as the same charge pump current is applied to each of
To obtain a tracking bandwidth, the veo operating frc­ them. The two voltage drops can then be summed to form the
quency should have the same dependency on thc buffcr bias control voltage by replicating the voltage across the capacitor
current as the loop bandwidth WN. Symmetric load buffer with a voltage source placed in series with the resistor.
,(ages can be used to implement the veo in order to obtain a It just so happens thal the bias generator can conveniently
broad frequency range. Fig. 10 shows their typical frequency implement this voltage source and resistor since it buffers
as a function of control voltage. The frequency is proportional VCTRL to form VB? with a finite output resistance, Re ferring
to VCTIlL - Vr or, equivalently, the square root of Tv, and back to the buffer bias circuit in Fig. 2, it is evident that this
the slope is constant. Thus, Kv is constant and the reference resistance is established by a diode-connected symmetric load
frequency WIlEF is proportional to the square root of the buffer or, equivalently, a diode-connected PMOS device. Thus, the
bias current. Since both WN and WREF are proportional to the resistance is equal to l/o9m or inversely proportional to the
square root of the buffer bias current, the loop bandwidth will square root of the buffer bias current. Thus, the self-biased
track the operating frequency. PLL can be completed simply by adding an additional charge
pump current [5J to the bias generator's VBP output as shown
C. Feed-Forward Zero in Fig. 12. Therefore, as with the DLL, this PLL design is
completely self-biased.
It may seem difficult to obtain a resistor for the loop filter
that varies inversely proportionally to the square root of the
buffer bias current. However, this resistor can be formed from D. Quantitative Analysis
the small-signal resistance 1/09", for a diode-connected device, As for the DLL, a more detailed analysis wilI show a
where o9m is proportional to the square root of the buffer bias very simple result for the damping factor and the relationship

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MANEATIS: LOW-JITtER PROCESS-INDEPENDENT DLL AND PLL BASED ON SELF-BIASED TECHNIQUES 1729

between the loop bandw idth and the operati ng frequency. ran ge achiev abl e by the veo operating open loop. The only
First,a re l a tionshi p between veo gain an d cont rol volt age process techn ol og y dependence is on a ratio of capacitances
is needed. The oscillation fre quenc y for an n-stage veo is that can be matched reasona bly well in layout. WN an d ( can
given by be aggressively set to minimi ze Jitter accumulation over all
operating frequencies.
F = -- =
1 k· (VCTIlL - VT) v' 2 . k . ID
= (17)
CB CB
-

2· n· t
where CB is once again defined as
is proporti on al to the square root of
2 . n . CEFF. Th us , the
E. PLL Capture Behavior

A useful artifact of the self-bi asing used in the PLL is a

n onlinear capture behavior. Typical PLL's will slew tow ar d
oscill ation frequency

the final target f requency at rough ly a constant rate. A phase ­

the butler bias current. Ta ki ng thc dcrivative with respect to
VCTRL, thc veo gain Kv is g iven by
frequen cy comparator will detect on average a ph ase error of

Ky
1 dF 1 k
(18)
a half c ycl e which will cause the charge pump to source or

dVCTRL CB sink on average half of its charge pump current to the loop
filter. The resulting cha n ge in c ont rol voltage is given by
= =

which is independent of the buffer bias current.

With th e rel atio nship for K y establ ish ed the damping factor
and bandwidth to operating frequency rati o can be derived.
, 1 V�� 1= � . � .
d nL
1
I CH (23)
Let the charge pump current be set to some multipl e :r of the
buffer bi as current such that
which leads to th e result

IC H = X· (2· ID)' (19) VCTnL(t)

=
VCTRdO) ± �C
·
2 '1
. ICH t . (24)

Also, l et the diode-connected s ymmet ric load in th e bias and

generator that establishes the loop filter resistance be y times
2· C1
la rger than the symmetric loads used in the buf fe r stages such t !VCTRL(t) - VCTRL(O)I· I (25)
ClI
= �-.

t hat
R-�- - y
(20)
For th e self-biased PLL, the eharge pump current, which is
- 2· 9m v'i3. k· ID prop ortion al to the buffer bias current, changes with the control

S ubst ituti ng in the exp res sions for JCH, K,-, and R, the
voltage and the veo ou tput frequency. This dependcncy
means that the rate of change in the control voltage or the
damping factor is then given by
veo output freq uency will increase when approaching higher

(
=
1 /1
.
2" V N
- lCH . Kv . R 2
. C1
frequencies and decrease when app roachin g lower frequencies .
The res ulting cha nge in eontml voltage is given by
2
=
1
--
2
1
J N
. x . (2 .Jn) .
CB
- .
k y
----:---::--
-c
8 · k· ID
- - G\ 1dVCTRL
dt
=
�
2
1 �
C1
. ICH
=

.
X· k
=1
C1
. (�cnu
T
- VT) 2 (26)

=�. {f;. /��. which leads to the result

(21)
1 x . k . t)-l
c onst ant times the VcTRdt) =
( ± �
4 c
. (27)
_

Thus, the damping factor is simply a l' (0) -- F + VT

ICTRL
square root of the ratio of tw o capacitances. Su b st it utin g in
VT 1

the expressions for ( , R, and FREF, the loop bandwidth to and

op erati n g frequency ratio is given by

WN 1 2·( t = :..�1 1 ·
VCTRL( ) � _ VT
-
VCTRL t) t _ VT ·I (28)

21f FREF R · C1
""REF The control volt age as a function of t im e d urin g capture
. .
.

1 N· CB Y ;:;:- rc; is pl ot ted in Fi g 13. Th e result is that the self-biased PLL

=
1" . V Ii V CJ;;
.
21f . v'2 - k . ID w ill slew toward lock at the fastest rate possible using the
,j87,;-:Ti) 2 maximum charge pump current such that the i nstantaneous
y C1 loop bandwidth does not exceed that r equi red to lock at the
current veo output frequ en cy. In contrast, a typi cal PLL will
=

X�;7\[ !fl. . (22) only be able to slew toward lock at a con st aJl t rate using a fixed
charge pump current such that the loop bandwidth does not
The loop bandwidth to operating frequ e ncy ratio is also a exceed that required to lock <lit t he lowest operating frequency
constant times the square root of the ra ti o of the same two of interest. Thus, the self-biased PLL will exhibit much faster
c apa cita nces .
Thus, the l oop bandwidth will track operating
and, therefore, set s no constraint on the operating
frequency
frequency
, ,
loc ki n g times when loc king from similar or higher operating
frequen ci es _ If, h ow ev er the self-biased PLL is started at a
very low opera tin g frequ ency possibl y in the low kilohertz
range. The PLL ca n operate over the same broad frequency range, i t will exhibit very slow locking times.

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1730 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 31. NO. 11. NOVEMBER 1996

4
--

�3
...
0::
tJ 2
>

oL-�-L�__L-�-L���L-�

Time (us)
� � � 4 � 0 1 2 3 4 5

Fig. 13. Self-biased PLL control voltage as a function oftime during capture.

UP

DN

Fig. 14. Phase-frequency comparator with equal short duration output pulses

16.
[or in-phase inputs.
Fig. Die micrograph of the dual-loop DLL and PLL.

short duration p ulses, some delay is typically added in the

reset path. Because of this added delay, a signal transition
at the R or V input w il l cause the corresponding UP or
DN outp U t to be asserted for some short delay before both
outputs are reset for the case when the other output was
a lrea dy asserted. However, adding de lay in the reset path can
reduce the maximum operating frequency of the PFC. The
maximum operating frequency is determined by the amount
of time required to reset the PFC after receiving the last set of
input transitions so that it is ready to detect the next set of input
Fig. IS. Differential-to-single-ended converter with 50% duty cycle output. transitions. The phase-frequency comparator shown in Fig. 14,
based on a conventional PFC 141, instead adds delay only in
Loop
v. ADDITIONAL COMPONENTS the output reset path by forming the outputs without including
the reset signal generated by the four input NAND gatc. Rather
In completing the self-biased DLL and PLL designs, some than ohtaining the outputs from the three input NAND gates
additional loop components are required. These include a at the far ri ght, the outputs are obtained from copies of the
phase-frequency comparator and a differential-to-single-ended gates with the reset signal input de leted. The outputs are still
reset, but thro ugh a slower p ath that includes the two NAND
converter. Although they are not essential to the self-biased
techniques they ar e impo rtant to the overall perf orman ce of
,
gates which form the SR latches. Since the in put reset path is
the self-biased DLL and PLL designs. unchanged, th e maximum op e rating frequency is unaffected.

A. Phase-Frequency Comparator B. Differential-to-Single-Ended Converter

Equal and short duration pulses at the UP and DN outputs of
the PFC are needed for in-phase inputs in order to eliminate
a dead-band in the PFC as seen by the charge pump. Such
a dead-band will lead to additional input tracking jitter, as
discussed in Section III-D. In order to guarantee equal and
PLL's are typically designed to operate at twice the chip
operating frequency so that their outputs can be d ivided by two
in order to guarantee a 50% duty cycle [4]. This practice is
particularly wasteful if the delay elements generate differential
signa ls . The maximum operating frequency will be re duced

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MAN�ATlS: LOW-JITTER PROCESS-INDEPENDENT DLL AND PLL BASED ON SELF BIASED TECHNIQUES 1731

Fig. 17. Dual-loop DLL block diagram. 500mV/div --- 3Mps ----+ 100psJdiv

Fig. I S. Measured PLL tracking jitter with 500 m V of supply noise .

by a factor of two and the input tracking jitter performance
can be adversely affected. The requirement for a 50% duty TABLE I
cycle can be satisfied without operating the PLL at twice the DUAL-Loop DLL PERFORMANCE CHARACTERISTICS MEASURED AT

chip operating frequency if a single-ended output with 50% 250 MHz WITH 500 mV OF 1 MHz SQUARE WAVE SUPPLY NOISE

duty cycle can be obtained from the differential output signal. Operating frequency range: 0.0025 MHz-400 MHz @ 3.3 V
Minimum supply requirements: 2.45 V, 8.6 IlIA
The differential-to-single-ended converter circuit shown in
Fig. 15 can produce such a 50% duty cycle output. It is
Input offset, sensitivity: 112 ps, <100 ps/lOO MHz
Tracking jitter. sensitivity: 610 ps, 1165 pslV (P-P)
composed of two opposite phase NMOS differential amplifiers Cycle-to-cycle jitter, sensitivity: 262 ps, 430 pslV (P-P)
driving two PMOS common-source amplifiers connected by an Block area: 1.18 mm2
NMOS current mirror. The two NMOS differential amplificrs Technology: O.S-pm }I(-well CMOS gale array
arc constructed from symmetric load buffer stages using the
same NMOS current source hias voltage as the driving buffer TABLE II
stages so that they receive the correct common-mode input PLL PERFORMANCE CHA�'\,CTERISTICS MEASURED AT 250 MHz

voltage level. They provide signal amplification and a dc bias WITH 500 mV OF 1 MHz S QUA RE WAVE SUPPLY NOISE

point for the PMOS common-source amplifiers. The P:v10S Uperating frequency range: 0.0025 MHz-550 MHz @ 3.3 V

common-source amplifiers provide additional signal amplifi­ .\1inimu111 supp]y requirements: 2.10 V, 4.4 rnA
Input offset, sensitivity: <25 ps, <10 ps/lOD MHz
cation and conversion to a single-ended output through the
Tracking jitter, sensitivity: 384 ps, 704 pslV (P-P)
NMOS current mirror. Because the two levels of amplification Cycle-to-cycle jitter, sensitivity: 144 ps, 290 pslV (P-P)
are differentially balanced with a wide bandwidth, the oppos­ Block area: 1.91 mm
2

ing differential input transitions have equal delay to the output.
The limitations of this circuit in converting the differential
signal transitions into rising and faIling singlc-cnded output
transitions at medium and high bias levels are identical to
those of a divider in converting single direction transitions into
rising and falling single-ended output transitions. However,
using this circuit instead of a divider to generate a 50% duty
cycle output can substantially relax the design constraints on
the VCO for high frequency designs.
VI. EXPERIMENTAL RESULTS
I30th the self-biased DLL and PLL designs were fablicated
in a O.5-�m N-well CMOS gate array process. A micrograph
of the fahricated design s with a superimposed floor plan is
shown in Fig. 16. The loop filter capacitors for both the
DLL and PLL are integrated on-chip using PMOS gate array
devices. The capacitor arrays also contain an equal number of
NMOS devices that are in rows interleaved between the PMOS
devices. These NMOS devices are used to make a supply
bypass capacitor. The DLL design actually implemented was
a dual-loop DLL design [2], [6], as shown in Fig. 17, which
contains two cascaded DLL's to allow it to perform frequency
multiplication and duty cycle adjustment.
The PLL input-to-output tracking jitter performance with
500 m V of I MHz square wave supply noise is illustrated
Technology: D.S-pm N-well CMOS gale array
in Fig. 18. This square wave supply noise has edge transition
times less than 10 ns. It is important to note that low frequency
square wave supply noise is one of the most extreme jitter tests
that can be performed on a I'LL. Sine wave supply noise at
the loop bandwidth typically leads to much less jitter. The
confincd ccntral pcaks indicate very low static phase offset
sensitivity to supply voltage.
Performance characteristics of the dual-loop DLL and PLL
are summarized in Table I and Table II, respectively. Both
designs have a frequency range spanning five orders of mag­
nitude. This large range should allow a single design to satisfy
a variety of operating frequency requirements. The cycle-to­
cycle jitter listed is the jitter i.n the period of the output. The
measured jitter, although small, was increased by the gate array
implementation of the loop filter capacitors which contain
the interleaved rows of unrelated NMOS devices that lead
to control voltage coupling to ground. The die area for the
dual-loop DLL and PLL was: substantially increased by the
inefficient implementation of the loop filter capacitors. With
custom silicon, the PLL only occupies 0.4 mm2.
The PLL design performed about 50% better than the dual­
loop DLL design. This difference in performancc may havc
resulted from larger capacitive coupling to the DLL loop filter

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1732 IEEE JOURNAl OF SOr .TrJ-STATF. rTRrT JlTS. VOL. 1 1. NO. I I , NOVEMBER 1 996

capacitors since they werc cight timcs smaller than the PLL [2] 1. Mancatis, "Low-jitter process-independent DLL and PLL based on

loop filter capacitor.

,elf-biased techniques," in ISSCC 1996 Dig. Tech. Papers, Feb. 1996,
pp. 130- 1 3 1 .
[3] J . Maneatis and M . Horowitz, Precise delay generation using coupled
VII. oscillators," IEEE J. Solid-State Circuits, vol. 28,
"

CONCLUSIONS no. 12, pp. 1273-1282,

Dec.
Self-biasing greatly simplifies DLL and PLL designs. It
1993.
[4] 1 . Young er aI., "A PLL clock generator wilh 5 10 l lO MH" of lock
e lim inates the need for precise currents, eliminates virtually range for microprocessors," IEEE J. Solid-State Circuits, vol. 27, no.
I I,
pp. 1599-1 607, Nov. 1992,
[5] D. Mijuskovic et aI., "Cell -based fully integrated CMOS frequency
all process technology dependencies, and makes a wide op­

synthesizers," IEEE J Solid- Srare Circuits, vol. 29, 3,

erating frequency range possible. The bandwidth to operating no . pp. 271-279,
frequency ratio and the PLL damping factor are fixed com­ Mar. 1 994.
[ 6 [ A. Waizman, "A delay line loop for frequency synthesis of dc-skewed
1 994 Dig. Tech. Papers,
pletely by a ratio of capacitances. The operating frequency
clock," in ISSCC Feb. 1994. pp. 298-299.
range is limited only by the buffer stage design. Self-biasing
fac i l i tates the construction of an input offset-cancelled charge
pump. Se lf-bi a s i n g also allows a PLL to have the largest
possible loop handwidth over all operating frequencies for John G . Maneatis was born in San Francisco, CA,
un November 7, 1965. He received the B . S . degree
minimal jitter accumulation. The phase-frequency comparator
in electrical engineering and computer sc i en ce from
design provides equal short duration output pulses for in-phase the University of C alifornia , Berkeley, in 1988 and
inputs without reducing its maximum uperating freq uency . The the M . S . and Ph.D. degrees in electrical engineering
from STanford University, Stanford, CA, in 1989 and
differential-to-single-ended converter can convert differential
1994.
input signals into single-ended output signals with 50% duty He worked at Hewlett-Packard Laboratories, Palo
cycle, avoiding the need for dividing by two. Fabricated in a Alto, CA. during the summer of 1 989 o n high-speed
analog-to-digital conversion and monolithic clock
0.5-/1,ill N -wcll
recovery,
PLL achieves
CMOS gate array process, the
and at Digital Equipment Corporation
an operating frequency range of 0.0025 MHz to 550 MHz and Western Research Laboratory, Palo Alto, CA, during the summer of 1990 on
input tracking j itter of 384 ps at 250 MHz with 500 mV of CAD tool development and ECL circuit design. While at Stanford University.
his research interests included high-performance circuit design for phase­
low frequency square wave supply noise.
locked loops, microprocessors, and data conversion. Since 1994 he ha, been
a c ircuit designer at Silicon Graphics, Inc., :Vlountain View, CA, working in
REFERENCES the area of microprocessor design.
Dr. Maneatis is a member of Tau Beta Pi, Eta Kappa Nu, and Phi Beta
[I] F. Gardner, "Charge-pump phase-lock loops," IEEE Trans. Cornmun. , Kappa and a Registered Professional E l ectric al Engineer in the State of
vol. COM-28, no. II, pp. 1 849-1858, Nov. 1980. California.

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