S. S.

AGRAWAL INSTITUTE OF ENGINEERING AND TECHNOLOGY, NAVSARI

ELECTRICAL ENGINEERING DEPARTMENT
DIGITAL FUNDAMENTALS [3130704]
QUESTION BANK / ASSIGNMENT

MODULE 5

June – 2017
Nov. – 2017
Dec. – 2014

Dec. – 2015
May – 2015

May – 2016

May – 2018
Jan. – 2017
Total
Sr.
Question number of
No.
time asked
questions
Define the followings.
(i) Propagation delay (ii) Fan in (iii) Noise
1 Margin (iv) Negative Logic 7 1
(v) Write D’ Morgan’s Theorems (vi) EPROM
(vii) Totem Pole output
Compare the Followings in every aspect.
2 (i) TTL and CMOS (ii) RAM and 7 1
ROM
Write short note on Programmable Logic Arrays.
3 7 1
Compare ROM, PLA and PAL
4 7 1
Explain two input CMOS NAND gate.
5 7 1
Define the following terms.
6 3 1
I. Noise Margin II. PROM III. Negative Logic
Write a note on Memory.
7 7 1
Give classification of logic families. Also list the
8 3 1
characteristics of digital IC.
Write short note on Read Only Memory (ROM).
9 7 1
Define: 1) Fan in 2) Noise Margin 3) Propagation Delay
10 3 1
Give comparison of TTL and CMOS family.
11 3 1
Compare ROM, PLA and PAL.
12 7 1
Make comparison:
13 i. ROM vs PLA 4 1
ii. PLA vs PAL
Compare TTL, ECL, & CMOS logic families.
14 4 1
List out various logic families. Also list the
15 3 1
characteristics of digital ICs.
Using 8x4 ROM, realize the expressions F1 = AB'C +
ABC' + A'BC, F2
16 7 1
= A'B'C + A'BC' + AB'C', F3 = A'B'C' + ABC. Show the
contents of all locations.
 S. S. AGRAWAL INSTITUTE OF ENGINEERING AND TECHNOLOGY, NAVSARI
ELECTRICAL ENGINEERING DEPARTMENT
DIGITAL FUNDAMENTALS [3130704]
QUESTION BANK / ASSIGNMENT

17 Write short note on Programmable Logic Arrays. 4 1

Draw & explain in brief general architecture of Xilinx

18 3 1
FPGA.
Implement following functions using ROM. F1 = ∑ m(1,
3, 4, 6)
19 F2 = ∑ m(2, 4, 5, 7) 7 1
F3 = ∑ m(0, 1, 5, 7)
F4 = ∑ m(1, 2, 3, 4)
Compare TTL, ECL, & CMOS logic families.
20 7 1