S. S.

AGRAWAL INSTITUTE OF ENGINEERING AND TECHNOLOGY, NAVSARI

ELECTRICAL ENGINEERING DEPARTMENT
DIGITAL FUNDAMENTALS [3130704]
QUESTION BANK / ASSIGNMENT

MODULE 3

June – 2017
Nov. – 2017
Dec. – 2014

Dec. – 2015
May – 2015

May – 2016

May – 2018
Jan. – 2017
Total
Sr.
Question number of
No.
time asked
questions
Design a mod-12 Synchronous up counter using D-
1 7 1
flipflop.
Draw the circuit diagrams and Truth table of all the Flip
2 7 1
flops (SR, D, T and JK).
Implement D flip flop using JK flip flop.
3 7 1
Write short note on four bit Universal Shift Register.
4 7 1
Convert D flip flop into SR flip flop
5 7 1
With the help of function table and circuit diagram
6 7 1
explain the working of clocked SR flip flop.
Design 4-bit ripple counter using negative edge
7 7 1
triggered JK flip flop.
With neat sketch design 4-bit bidirectional shift
8 7 1
register.
Distinguish between combinational and sequential logic
9 7 1
circuits. Give the applications of flip-flops.
Design a synchronous BCD counter with JK flip-flops.
10 7 1
Implement T flip flop using D flip flop.
11 3 1
Give the comparison between synchronous and
12 4 1
asynchronous counters.
Explain RS flip flop in detail.
13 4 1
Design Modulo-8 counter using T flip flop.
14 7 1
Explain edge triggering and level triggering.
15 3 1
Explain 4 bit serial in serial out shift register.
16 4 1
Design 3-bit synchronous up counter using T flip flop.
17 7 1
What is race around condition in JK flip flop.
18 3 1
 S. S. AGRAWAL INSTITUTE OF ENGINEERING AND TECHNOLOGY, NAVSARI
ELECTRICAL ENGINEERING DEPARTMENT
DIGITAL FUNDAMENTALS [3130704]
QUESTION BANK / ASSIGNMENT
How does a counter works as frequency divider?
19 4 1
Explain with suitable example.
Give the comparison between synchronous and
20 4 1
asynchronous counters.
Explain working of master-slave JK flip-flop with
21 necessary logic diagram, state equation and state 7 1
diagram.
Draw logic diagram, graphical symbol and
22 3 1
Characteristic table for clocked D flip-flop.
Design 4-bit ripple counter using negative edge
23 4 1
triggered JK flip flop.
With necessary sketch explain Bidirectional Shift
24 7 1
Register with parallel load.
Distinguish between combinational and sequential logic
25 3 1
circuits.
Draw the truth tables for JK & T FF. Using these truth
26 tables, derive & explain the excitation tables of JK & T 7 1
FF.
Draw high assertion & low assertion input SR latches.
27 3 1
Design 3-bit ripple up-counter using negative edge
28 4 1
triggered JK flip flops. Also draw the waveforms.
Design a counter to generate the repetitive sequence 0,
29 7 1
3, 5, 7, 4 using D FFs.
Draw gated SR latch using NAND gates only.
30 3 1
Draw and explain 4-bit serial-in serial-out shift register
31 4 1
using D FFs.
Explain JK flip flop with its characteristic table and
32 4 1
excitation table.
Explain Master Slave JK flip-flop with truth table and
33 3 1
circuit diagram.
Draw and explain Ring counter
34 4 1
Design a counter to generate the repetitive sequence 0,
35 7 1
1, 2,4,3,6.
Plot the out waveform referenced to the clock signal
36 assuming the initial contents of the flip-flops is q=0. 3 1
Assume all flip-flops are edge triggered.
Draw a frequency divider using JK FFs to divide input
37 3 1
clock frequency by a factor of 8.
For the figures 1, 2, & 3, plot the output waveforms
referenced to the clock signal assuming the initial
38 7 1
contents of all FFs is Q = 0. Assume all FFs are edge
triggered.
 S. S. AGRAWAL INSTITUTE OF ENGINEERING AND TECHNOLOGY, NAVSARI
ELECTRICAL ENGINEERING DEPARTMENT
DIGITAL FUNDAMENTALS [3130704]
QUESTION BANK / ASSIGNMENT
Design a 3-bit synchronous up counter using K-maps
39 and positive edge-triggered JK 7 1
FFs.
Draw & explain in brief a high assertion input SR latch.
40 3 1