Bahir Dar University

Faculty of Electrical and Computer

Engineering

Computer Architecture and Organization

[CoEg3091]
Chapter Five
Input /Output

23-Oct-16
 Input Output 2

In this chapter:
 Peripheral Devices
 I/O techniques
 DMA

23-Oct-16
 I/O Issues 3

Why not connect peripherals directly to system

bus?
 Wide variety of peripherals
 Delivering different amounts of data
 At different speeds
 In different formats
 All slower than CPU and RAM
Need I/O modules

23-Oct-16
 I/O Issues 4

I/O modules
 Interface to CPU and Memory
 Interface to one or more peripherals

Device
Interface External
sensors
Processor Bus I/O Device and
Module Interface controls

Device
Interface

23-Oct-16
 Peripheral Devices 5

Provide means of exchanging data b/n external

environment and computer
Types
 Human readable
 communication with user (monitor, printer,
keyboard, mouse)
 Machine readable
 communication with equipment (hard drive,
CDROM, sensors, and actuators)
 Communication
 communication with remote computers/devices
23-Oct-16
(modem, Network Interface Card (NIC))
 Peripheral Devices 6

Block diagram of an external device

23-Oct-16
 Peripheral Devices 7

Control logic
 Is the I/O module's interface to the device
Data channel
 Passes the data from/to the device
 On the opposite end is the I/O module, but eventually it is the
processor.
Transducer
 Acts as a converter between the digital data of the I/O module
and the signals of the outside world.
 Keyboard converts motion of key into data representing key
pressed or released
 Temperature sensor converts amount of heat into a digital value
 Disk drive converts magnetic patterns on disk to bits in the
device buffer
23-Oct-16
 I/O Modules 8

Functions
 Control & Timing
 CPU Communication
 Device Communication
 Data Buffering
 Error Detection

23-Oct-16
 I/O Modules 9

Control and Timing

 Required because of multiple devices
communicating on the same channel
 Example
 CPU checks I/O module device status
 I/O module returns status
 If ready, CPU requests data transfer
 I/O module gets data from device
 I/O module transfers data to CPU

23-Oct-16
 I/O Modules 10

CPU Communication
 Commands from processor
 Examples: READ SECTOR, WRITE SECTOR,
SEEK track number
 Data
 Passed back and forth over the data bus
 Status reporting
 Request from the processor for the I/O Module's
status
 May be as simple as BUSY and READY
 Address recognition
 The I/O module must recognize one unique
23-Oct-16
address for each device it controls
 I/O Modules 11

Device Communication
 Specific to each device (commands, status, data)
Data Buffering
 Due to the differences in speed (device is usually
orders of magnitude slower) the I/O module needs to
buffer data to keep from tying up the CPU's bus with
slow reads or writes
Error Detection
 Distribute the error handling to the module
 Malfunctions by device (paper jam)
 Data errors (parity checking at the device level)
 Internal errors to the I/O module such as buffer
23-Oct-16
overruns
 I/O Module Structure 12

23-Oct-16
 I/O Module Operation 13

How much control will the CPU be required

to handle?
How much will the CPU be allowed to
handle?
What will the interface look like?
 e.g., Unix treats everything like a file
Support multiple or single device?

23-Oct-16
 I/O Module Operation 14

Types of I/O modules

 I/O channel (I/O processor)
 Responsible for the detailed processing
burden
 Presents a high-level interface to CPU
 I/O controller (device controller)
 Quite primitive
 Requires detailed control

23-Oct-16
 I/O Techniques 15

Programmed I/O
 poll and response
Interrupt Driven I/O
 module calls for CPU when needed
Direct Memory Access (DMA)
 I/O module has direct access to specified
block of memory

23-Oct-16
 I/O Techniques 16

23-Oct-16
 Programmed I/O 17

Operation
 CPU fetches I/O instruction from memory
 CPU issues I/O command
 I/O module performs operation
 I/O module sets status bits
 CPU checks status bits periodically
 I/O module does not inform CPU directly
 I/O module does not interrupt CPU
 CPU may wait or come back later
Wastes CPU time because typically the
processor is much faster than I/O
23-Oct-16
 Programmed I/O 18

I/O commands (from CPU to I/O module)

 CPU issues address
 Identifies module (and device if more than
one per module)
 CPU issues command
 Control - telling module what to do
o e.g. spin up disk
 Test - check status
o e.g. powered?, error?
 Read/Write
o Module transfers data via buffer from/to
23-Oct-16
device
 Programmed I/O 19

I/O instructions (part of program, fetched by CPU

from memory)
 Most important – addressing I/O devices
 Under programmed I/O, data transfer is
much like memory access (CPU viewpoint)
 Each device given unique identifier
 CPU commands contain identifier (address)
 Two modes of addressing
o Memory-mapped I/O
o Isolated I/O

23-Oct-16
 Programmed I/O 20

Memory-mapped I/O
 Devices and memory share an address space
 I/O read/write looks just like memory read/write
 No special commands for I/O
 Large selection of memory access commands
available
Isolated I/O
 Same address lines, but separate address spaces
 Need extra lines to select I/O or memory
 Special commands for I/O
 Limited set
23-Oct-16
 Programmed I/O 21

Memory-mapped I/O
vs. Isolated I/O

23-Oct-16
 Interrupt Driven I/O 22

Overcomes CPU waiting

Requires setup code and interrupt service
routine
No repeated CPU checking of device
I/O module interrupts when ready
Still requires CPU operation for moving data
between I/O module and main memory

23-Oct-16
 Interrupt Driven I/O 23

Operation (I/O module viewpoint)

 I/O module receives read command from CPU
 I/O module gets data from peripheral
 Once data is in I/O module register, it interrupts
CPU
 I/O module waits for CPU to request data
 When requested by CPU, I/O module places
data on bus

23-Oct-16
 Interrupt Driven I/O 24

Operation (CPU viewpoint)

 CPU issues read command
 Does other work
 Checks for interrupt at end of each instruction
cycle
 No code is involved in this
 If interrupted:
 Saves context (registers)
 Processes interrupt
o Fetches data from I/O module & stores it in
memory

23-Oct-16
Restores context
 Interrupt Processing 25

23-Oct-16
 Design Issues 26

Resolution of multiple interrupts

 How do you identify the module issuing the
interrupt?
Priority
 How do you deal with multiple interrupts (at the
same time or interrupting in the middle of an
interrupt handler)?

23-Oct-16
 Identifying Interrupting Module 27

Multiple interrupt lines

 Different line for each module
 Limits number of devices
 Even with this method, there still may be
multiple interrupts on a single interrupt line
 Priority
 set by hardware

23-Oct-16
 Identifying Interrupting Module 28

Software poll
 Single interrupt line
 CPU asks each module to see who needs
attention
 Slow
 Priority
 set by the order in which CPU polls the
devices

23-Oct-16
 Example – Interrupt Controller 29

82C59A Interrupt
Controller
 Used with 80386
processor
 CPU has one
interrupt line
 8259A has 8
interrupt lines

23-Oct-16
 Example – Interrupt Controller 30

Sequence of events
 82C59A accepts interrupts
 82C59A determines priority
 Fully nested
o IR0 (highest) through IR7 (lowest)
 Rotating
o after interrupt is serviced, it goes to bottom of priority list
 Special mask
o allows individual interrupts to be disabled
 82C59A signals CPU (raises INTR line)
 CPU acknowledges (with INTA line)
 82C59A puts correct vector on data bus
 CPU processes interrupt
23-Oct-16
 Direct Memory Access 31

Motivation
 Both programmed I/O and interrupt driven I/O
require active CPU intervention
 Transfer rate is limited by CPU's ability to service the
device
 CPU is tied up managing I/O transfer
Direct memory access (DMA)
 Additional module (hardware) on bus
 DMA controller takes over bus from CPU for I/O
 Waiting for a time when the processor doesn't need
the bus
 Cycle stealing – seizing bus from CPU (more
23-Oct-16
common)
 Direct Memory Access 32

DMA module

23-Oct-16
 Direct Memory Access 33

Operation
 CPU tells DMA controller:
 Read/Write
 Device address
 Starting address of memory block for data
 Amount of data to be transferred
 CPU performs other work
 DMA controller performs transfer
 DMA controller sends interrupt when finished

23-Oct-16
 Direct Memory Access 34

Cycle stealing
 DMA controller takes over bus for a cycle
 Transfer of one word of data
 Not an interrupt
 CPU does not switch context
 CPU suspended just before it accesses bus
 i.e. before an operand or data fetch or a data
write
 Slows down CPU but not as much as CPU
doing transfer

23-Oct-16
 DMA Configurations 35

Single bus, detached DMA controller

 Each transfer uses bus twice
 I/O to DMA then DMA to memory
 CPU is suspended twice

23-Oct-16
 DMA Configurations 36

Single bus, DMA controller integrated into

I/O module
 Controller may support one or more devices
 Each transfer uses bus once
 DMA to memory
 CPU is suspended once

23-Oct-16
 DMA Configurations 37

Separate I/O Bus

 Reduces number of I/O interfaces in DMA
module to one  expandable configuration
 Each transfer uses bus once
 DMA to memory
 CPU is suspended once

23-Oct-16
 38

THANK YOU!!!!

23-Oct-16