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Lec 2 (VHDL Basics)
Lec 2 (VHDL Basics)
Introduction to VHDL
Naming and labelling
Comments
Libraries
Entity
Architecture
Signals
Direct assignment
Operators
Conditional assignment
Introduction to VHDL
Library ieee;
Use ieee.std_logic_1164.all;
0 0v 0 0v
1 5v 1 5v
L Weak 0
H Weak 1
U Uninitialized
- Don’t Care
X Unknown
Z High Impedance
Libraries Arithmetic
Signed Vs. Unsigned
Use ieee.std_logic_Arith.all;
Use ieee.std_logic_Unsigned.all; OR
Use ieee.std_logic_Signed.all;
Entity any_name is
Port ( ------------ ;
------------ ;
------------- ) ;
End any_name ;
Example:
Entity circuit1 is
A
Port ( ------------ ; S
------------ ;
------------ ;
------------ ) ; B Co
End circuit1 ;
Entity Inputs/Outputs
10
Port Modes
In Input Pin
out Output Pin
inout Input &Output Pin
Buffer Output Pin + Storage
Entity Inputs/Outputs
11 Port_name : Port mode Port-type_Port-size ;
Port Types
Integer Integer values 1,2,3 ….
bits Boolean 0 or 1
Std_logic Standard Logic 0, 1, L, H, -, U, Z
0 0v
1 5v
L Weak 0
Standard Logic H Weak 1
(STD_Logic) U Uninitialized
- Don’t Care
X Unknown
Z High Impedance
Entity Inputs/Outputs
12
Port_name : Port mode Port-type_Port-size ;
Port size
Single 1 wire
Vector (Buses) N wires
Vectors (Buses) are a group of wires of the same type & name,
where each wire is indexed by a number (Similar to arrays)
Std_Logic_vector ( MSB_Index downto/to LSB_Index)
Vectors Guidelines:
1- start the indices from Zero
2- Use downto if MSB_Index > LSB_Index
3- Use to if MSB_Index < LSB_Index
4- It is favorable to always use for LSB index 0 and MSB the highest
index (Vector_size -1)
VHDL reserved keywords
13 •access •else •new •return
•after •elsif •next •select
•alias •end •nor •severity
•all •entity •not •signal
•and •exit •null •subtype
•architecture •file •of •then
•array •for •on •to
•assert •function •open •tansport
•attribute •generate •or •type
•begin •generic •others •units
•abs •guarded •out •until
•block •if •package •use
•body •in •port •variable
•buffer •inout •procedure •wait
•bus •is •process •when
•case •label •range •with
•component •library •record •xor
•configuration •linkage •register
•constant •loop •rem
•disconnect •map •report
•downto •mod
Combinational Circuit
Example
a(7:0)
8-line y(7:0)
b(7:0) 2 x 1 MUX
sel y
0 a
1 b
sel
Combinational Circuit
Example
a(7:0) 8-line
2x1 y(7:0)
library IEEE; MUX
b(7:0)
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux2 is
port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
port statement defines inputs
and outputs
Entity
Mode: in or out
library IEEE;
use IEEE.std_logic_1164.all;
entity mux2 is
port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
Data type: STD_LOGIC,
STD_LOGIC_VECTOR(7 downto 0);
19
Architecture format
ARCHITECTURE architecture_name OF entity_name IS
-- data type definitions
-- internal signal declarations
-- component declarations
BEGIN
-- behavior of the model is described here using:
-- component instantiations
-- concurrent statements
-- processes
END architecture_name;
VHDL Architecture Modeling
Types
Signals are internal wires or buses inside the hardware that help us to
describe
23 it easier. They are defined between the Architecture & its begin
SIGNAL a : STD_LOGIC;
a
1 wire
Concurrent Statements
1) Signal Assignment
2) Conditional Assignment
3) Process Statement
4) Component Instantiation
Sequential Statements
1) Signal Assignment
2) Conditional Assignment
3) Variable Assignment
4) Loop Statements
5) Wait Statement
Concurrent Statements (Signal
25
Assignment)
Destination & the statement output Must be of the same size
2. Concatenation :
Entity HA is
Port ( A, B : in std_logic ;
S, Co : out std_logic ) ;
End HA ;
Architecture data_flow of HA is
Begin
S <= A xor B ;
Co <= A and B ;
End data_flow ;
35 Program
Library ieee;
Use ieee.std_logic_1164.all;
Entity circuit2 is
Port ( A, B, C : in std_logic ;
F1, F2 : out std_logic ) ;
End circuit2 ;
Architecture data_flow of circuit2 is
Signal X, Y, Z : std_logic ;
Begin
X <= A xor B ;
Y <= A and B ;
Z <= X and Y ;
F1 <= X xor Y ;
F2 <= (Z nand Y) nand c ;
End data_flow ;
36