EEE 303

Digital Electronics
3.1 Introduction to Verilog
Rajat Chakraborty
Lecturer
Dept. of EEE, BUET
 Verilog

❖Originally intended for simulation and verification of digital- What we will do in

this course and EEE 303 Laboratory
❖With addition of synthesis capability, Verilog has also become popular for use in
design entry in CAD systems- VLSI II
 Basic Rules
❖ Variable name must start with a letter
❖ Can contain any letter, number and just two symbols ( _ , $)
❖ Case sensitive
❖White Space characters do not matter
❖Indentation and blank lines – highly recommended
❖Comment- // for single line – highly recommended
/* for multiple
line*/
❖ Semicolon ; !!! 10000V warning
 Basic Structure

module name_of_the_module (input, output);

input ……….. ;
output ……….. ;
………………. ;
………………. ;
endmodule
 Structural Specification
❖Gate level primitives
❖and, or, nand, nor, xor, xnor, not
❖Format- name_of_the_gate (input, output1, output2, …)
Two i/p AND gate- and (y,x1,x2);
Four i/p OR gate- or (y,x1,x2,x3,x4);
NOT gate- not (y,x);
 Structural Specification
❖Write down the names of extra nodes except i/p and o/p in the circuit/expression
❖Just follow the nodes to go from i/p side to the o/p side- as simple as that
 Structural Specification
❖Can skip ‘not’ gate by tilde (‘~’) symbol
❖Write down the extra nodes in a methodical way
 Continuous Assignment
❖Gate-level primitives can be tedious (almost impossible!!!) when large circuits
have to be designed
❖An alternative is to use more abstract expressions and programming constructs to
describe the behavior of a logic circuit- Behavioral specification

❖assign keyword for continuous assignment

❖Whenever any signal on the right-hand side changes its state, the value of f will be
re-evaluated- continuous
 Continuous Assignment
❖ Form the expression, write the expression (from i/p to o/p)
❖ AND - &, OR- |, NOT- ~, XOR- ^
 Continuous Assignment

Common mistakes:
i. Forgetting assign ii. Use of bracket
 Procedural Statement

❖ if-else, case, for, while, function- procedural statement

❖ Always contained inside an always block
❖ May include several always blocks, each representing a part of the circuit
Procedural Statement
 Procedural Statement

❖ after the @ symbol, in parentheses, is called the sensitivity list. The statements
inside an always block are executed by the simulator only when one or more of
the signals in the sensitivity list changes value.
always @ (*) / always @*- valid (but only for teachers in lab quiz :P )
❖If a signal is assigned a value using procedural statements, then Verilog syntax
requires that it be declared as a variable - keyword reg
Procedural for AND
Procedural for XOR
Adder Circuit
 Tips
❖Choose between continuous assignment and procedural if not stated (structural
almost never used)
❖Choose meaningful and methodical variable name
❖Write module and endmodule together while coding
❖Write the i/p, o/p, reg or sensitivity list after finishing the code
❖Use comment, indentation- for your own benefit
❖Remember to put ; , reg, assign- check Quartus to know the nature of the error

Practice! Practice!! Practice!!!