Chapter 3

Chapter 3
Digital Design and Computer Architecture, 2nd Edition

David Money Harris and Sarah L. Harris
Chapter 3 <1>
Chapter 3 :: Topics
• Introduction
• Latches and Flip-Flops
• Synchronous Logic Design
• Finite State Machines
• Timing of Sequential Logic
• Parallelism
Chapter 3 <2>
Introduction
• Outputs of sequential logic depend on current
and prior input values – it has memory.
• Some definitions:
– State: all the information about a circuit necessary
to explain its future behavior
– Latches and flip-flops: state elements that store
one bit of state
– Synchronous sequential circuits: combinational
logic followed by a bank of flip-flops
Chapter 3 <3>
Sequential Circuits
• Give sequence to events
• Have memory (short-term)
• Use feedback from output to input to store
information
Chapter 3 <4>
State Elements
• The state of a circuit influences its future
behavior
• State elements store state
– Bistable circuit
– SR Latch
– D Latch
– D Flip-flop
Chapter 3 <5>
Bistable Circuit
• Fundamental building block of other state
elements
• Two outputs: Q, Q
• No inputs
I1 Q
Q Q
I2 I1
I2 Q
Chapter 3 <6>
Bistable Circuit Analysis
• Consider the two possible cases:
– Q = 0: I1
0
Q
1
then Q = 1, Q = 0 (consistent)
0 1
I2 Q
– Q = 1:
1
then Q = 0, Q = 1 (consistent) 0
I1 Q
1 0
I2 Q
• Stores 1 bit of state in the state variable, Q (or Q)

• But there are no inputs to control the state
Chapter 3 <7>
SR (Set/Reset) Latch
• SR Latch R
N1 Q
N2 Q
S
• Consider the four possible cases:
– S = 1, R = 0
– S = 0, R = 1
– S = 0, R = 0
– S = 1, R = 1
Chapter 3 <8>
SR Latch Analysis
– S = 1, R = 0: R
0
1
N1 Q
then Q = 1 and Q = 0 0
0
0
1 N2 Q
S
– S = 0, R = 1: 1
R 0
N1 Q
0
1
0 N2 Q
S
Chapter 3 <9>
SR Latch Analysis
– S = 1, R = 0: R
0
1
N1 Q
Set the output 0

1 N2
0
Q
S
– S = 0, R = 1: 1
R 0
N1 Q
Reset the output 0

1
0 N2 Q
S
Chapter 3 <10>
SR Latch Analysis
– S = 0, R = 0: Qprev = 0 Qprev = 1
then Q = Qprev R
0
N1
0
Q
R
0
N1
1
Q
0 N2 Q 0 N2 Q
S S
– S = 1, R = 1: R
1
N1
0
Q
0
then Q = 0, Q = 0
0
0
1 N2 Q
S
Chapter 3 <11>
SR Latch Analysis
– S = 0, R = 0: Qprev = 0 Qprev = 1
then Q = Qprev R
0
N1
0
Q
R
0
N1 Q
Memory!
0 N2 Q 0 N2 Q
S S
– S = 1, R = 1: R
1
N1
0
Q
0
then Q = 0, Q = 0
0
Invalid State S
1 N2
0
Q
Q ≠ NOT Q
Chapter 3 <12>
SR Latch Symbol
• SR stands for Set/Reset Latch
– Stores one bit of state (Q)
• Control what value is being stored with S, R
inputs
– Set: Make the output 1 SR Latch
Symbol
(S = 1, R = 0, Q = 1)
– Reset: Make the output 0 R Q
(S = 0, R = 1, Q = 0) S Q
• Must do something to avoid
invalid state (when S = R = 1)
Chapter 3 <13>
D Latch
• Two inputs: CLK, D
– CLK: controls when the output changes
– D (the data input): controls what the output changes to
• Function D Latch
– When CLK = 1, Symbol
D passes through to Q (transparent) CLK
– When CLK = 0,
D Q
Q holds its previous value (opaque)
Q
• Avoids invalid case when
Q ≠ NOT Q
Chapter 3 <14>
D Latch Internal Circuit
CLK R CLK
D R Q Q
S
D Q
S Q Q
D
Q
CLK D D S R Q Q
0 X
1 0
1 1
Chapter 3 <15>
D Latch Internal Circuit
CLK R CLK
D R Q Q
S
D Q
S Q Q
D
Q
CLK D D S R Q Q
0 X X 0 0 Qprev Qprev
1 0 1 0 1 0 1
1 1 0 1 0 1 0
Chapter 3 <16>
D Flip-Flop
• Inputs: CLK, D D Flip-Flop
Symbols
• Function
– Samples D on rising edge of CLK
• When CLK rises from 0 to 1, D D Q
passes through to Q Q
• Otherwise, Q holds its previous
value
– Q changes only on rising edge of CLK
• Called edge-triggered
• Activated on the clock edge
Chapter 3 <17>
D Flip-Flop Internal Circuit
• Two back-to-back latches (L1 and L2) controlled by
complementary clocks
CLK
• When CLK = 0
– L1 is transparent
– L2 is opaque CLK CLK
– D passes through to N1 N1
D D Q D Q Q
• When CLK = 1 L1 Q L2 Q Q
– L2 is transparent
– L1 is opaque
– N1 passes through to Q
• Thus, on the edge of the clock (when CLK rises from 0 1)
– D passes through to Q
Chapter 3 <18>
D Latch vs. D Flip-Flop
CLK
D Q D Q
Q Q
CLK
Q (latch)
Q (flop)
Chapter 3 <19>
D Latch vs. D Flip-Flop
CLK
D Q D Q
Q Q
CLK
Q (latch)
Q (flop)
Chapter 3 <20>
Registers
CLK
D0 D Q Q0
CLK
D1 D Q Q1 4 4
D3:0 Q3:0
D2 D Q Q2
D3 D Q Q3
Chapter 3 <21>
Enabled Flip-Flops
• Inputs: CLK, D, EN
– The enable input (EN) controls when new data (D) is stored
• Function
– EN = 1: D passes through to Q on the clock edge
– EN = 0: the flip-flop retains its previous state
Internal
Circuit
Symbol
EN CLK
0
D Q Q D Q
D 1
EN
Chapter 3 <22>
Resettable Flip-Flops
• Inputs: CLK, D, Reset
• Function:
– Reset = 1: Q is forced to 0
– Reset = 0: flip-flop behaves as ordinary D flip-flop
Symbols
D Q
r
Reset
Chapter 3 <23>
• Two types:
– Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop?
Chapter 3 <24>
• Two types:
– Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop?
Internal
Circuit
CLK
D
D Q Q
Reset
Chapter 3 <25>
Settable Flip-Flops
• Inputs: CLK, D, Set
• Function:
– Set = 1: Q is set to 1
– Set = 0: the flip-flop behaves as ordinary D flip-flop
Symbols
D Q
s
Set
Chapter 3 <26>
Sequential Logic
• Sequential circuits: all circuits that aren’t
combinational
• A problematic circuit:
X
X Y Z
Y
Z
0 1 2 3 4 5 6 7 8 time (ns)
Chapter 3 <27>
Sequential Logic
• Sequential circuits: all circuits that aren’t
combinational
• A problematic circuit:
X
X Y Z
Y
Z
0 1 2 3 4 5 6 7 8 time (ns)
• No inputs and 1-3 outputs

• Astable circuit, oscillates
• Period depends on inverter delay
• It has a cyclic path: output fed back to input
Chapter 3 <28>
Synchronous Sequential Logic Design
• Breaks cyclic paths by inserting registers
• Registers contain state of the system
• State changes at clock edge: system synchronized to the
clock
• Rules of synchronous sequential circuit composition:
– Every circuit element is either a register or a combinational circuit
– At least one circuit element is a register
– All registers receive the same clock signal
– Every cyclic path contains at least one register
• Two common synchronous sequential circuits
– Finite State Machines (FSMs)
– Pipelines
Chapter 3 <29>
Finite State Machine (FSM)
• Consists of: CLK
– State register S’ S
Next Current
• Stores current state State State
• Loads next state at clock edge

– Combinational logic
• Computes the next state
• Computes the outputs
Next State Output
Logic Logic
CL Next
State
CL Outputs
Chapter 3 <30>
Finite State Machines (FSMs)
• Next state determined by current state and inputs
• Two types of finite state machines differ in output logic:
– Moore FSM: outputs depend only on current state
– Mealy FSM: outputs depend on current state and inputs
Moore FSM
CLK
M next
next
k state k N
inputs state
state output
outputs
logic
logic
Mealy FSM
CLK
M next
next
k state k state N
inputs state
output
outputs
logic
logic
Chapter 3 <31>
FSM Design Procedure
1. Identify inputs and outputs
2. Sketch state transition diagram
3. Write state transition table
4. Select state encodings
5. For Moore machine:
1. Rewrite state transition table with state encodings
2. Write output table
6. For a Mealy machine:
1. Rewrite combined state transition and output table with state
encodings
7. Write Boolean equations for next state and output logic
8. Sketch the circuit schematic
Chapter 3 <32>
FSM Example
• Traffic light controller
– Traffic sensors: TA, TB (TRUE when there’s traffic)
– Lights: LA, LB
Bravado
Dining
Hall
LB
LA TB
LA
Academic TA TA Ave.
Labs TB LB Dorms
Blvd.
Fields
Chapter 3 <33>
FSM Black Box
• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB
CLK
TA Traffic LA
Light
TB Controller LB
Reset
Chapter 3 <34>
FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles
Reset
• Transitions: Arcs S0
LA: green
LB: red
Chapter 3 <35>
FSM State Transition Diagram
• Moore FSM: outputs labeled in each state
• States: Circles Reset
T A
• Transitions: Arcs S0 T S1 A
LA: green LA: yellow

LB: red LB: red
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB
Chapter 3 <36>
FSM State Transition Table
Current Next
State Inputs State
S TA TB S'
S0 0 X
S0 1 X
S1 X X
S2 X 0
S2 X 1
S3 X X
Chapter 3 <37>
FSM State Transition Table
Current Next
State Inputs State
S TA TB S'
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S2 X 1 S2
S3 X X S0
Chapter 3 <38>
FSM Encoded State Transition Table
Current
State Inputs Next State
State Encoding
S1 S0 TA TB S'1 S'0
0 0 0 X S0 00
0 0 1 X S1 01
0 1 X X S2 10
1 0 X 0
S3 11
1 0 X 1
1 1 X X
Chapter 3 <39>
FSM Encoded State Transition Table
Current
State Inputs Next State
State Encoding
S1 S0 TA TB S'1 S'0
0 0 0 X 0 1 S0 00
0 0 1 X 0 0 S1 01
0 1 X X 1 0 S2 10
1 0 X 0 1 1
S3 11
1 0 X 1 1 0
1 1 X X 0 0
S'1 = S1 ⊕ S0
S'0 = S1S0TA + S1S0TB
Chapter 3 <40>
FSM Output Table
Current
State Outputs Output Encoding
S1 S0 LA1 LA0 LB1 LB0 green 00
0 0 yellow 01
0 1
red 10
1 0
1 1
Chapter 3 <41>
FSM Output Table
Current
State Outputs Output Encoding
S1 S0 LA1 LA0 LB1 LB0 green 00
0 0 0 0 1 0 yellow 01
0 1 0 1 1 0
red 10
1 0 1 0 0 0
1 1 1 0 0 1
LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
Chapter 3 <42>
FSM Schematic: State Register
CLK
S'1 S1
S'0 S0
r
Reset
state register
Chapter 3 <43>
FSM Schematic: Next State Logic
CLK
S'1 S1
TA S'0 S0
r
TB Reset
S1 S0
inputs next state logic state register
Chapter 3 <44>
FSM Schematic: Output Logic
CLK LA1
S'1 S1
LA0
TA S'0 S0
LB1
r
TB Reset
S1 S0 LB0
inputs next state logic state register output logic outputs
Chapter 3 <45>
FSM Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10
CLK
Reset
TA
TB
S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)
S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)
LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)
LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)
0 5 10 15 20 25 30 35 40 45 t (sec)
TA
Reset
S0 TA S1
LB: red LB: red
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB
Chapter 3 <46>
FSM State Encoding
• Binary encoding:
– i.e., for four states, 00, 01, 10, 11
• One-hot encoding
– One state bit per state
– Only one state bit HIGH at once
– i.e., for 4 states, 0001, 0010, 0100, 1000
– Requires more flip-flops
– Often next state and output logic is simpler
Chapter 3 <47>
Review: FSMs
Moore FSM
CLK
M next
next
k state k N
inputs state
state output
outputs
logic
logic
Mealy FSM
CLK
M next
next
k state k state N
inputs state
output
outputs
logic
logic
Chapter 3 <48>
Review: FSM Design Procedure
encodings
Chapter 3 <49>
Moore vs. Mealy FSM
• Alyssa P. Hacker has a snail that crawls down a paper tape
with 1’s and 0’s on it. The snail smiles whenever the last two
digits it has crawled over are 01. Design Moore and Mealy
FSMs of the snail’s brain.
Chapter 3 <50>
State Transition Diagrams
Moore FSM
Reset
0 1
S0 S1 S2
0 0 1
1 0 0
1
Mealy FSM
Reset
0/0
S0 S1
1/0 0/0
1/1
Mealy FSM: arcs indicate input/output
Chapter 3 <51>
Moore FSM State Transition Table
Current Next
State Inputs State State Encoding
S1 S0 A S'1 S'0 S0 00
0 0 0
0 0 1 S1 01
0 1 0 S2 10
0 1 1
1 0 0
1 0 1
Chapter 3 <52>
Moore FSM State Transition Table
Current Next
State Inputs State State Encoding
S1 S0 A S'1 S'0 S0 00
0 0 0 0 1
0 0 1 0 0 S1 01
0 1 0 0 1 S2 10
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
S1’ = S0A
S0 ’ = A
Chapter 3 <53>
Moore FSM Output Table
Current
State Output
S1 S0 Y
0 0
0 1
1 0
Chapter 3 <54>
Moore FSM Output Table
Current
State Output
S1 S0 Y
0 0 0
0 1 0
1 0 1
Y = S1
Chapter 3 <55>
Mealy FSM State Transition & Output Table
Current Next
State Input State Output
S0 A S'0 Y State Encoding
0 0
0 1 S0 00
1 0 S1 01
1 1
Chapter 3 <56>
Mealy FSM State Transition & Output Table
Current Next
State Input State Output
S0 A S'0 Y State Encoding
0 0 1 0
0 1 0 0 S0 00
1 0 1 0 S1 01
1 1 0 1
Chapter 3 <57>
Moore FSM Schematic
A CLK
S'1 S1
Y
S'0 S0
r
Reset
Chapter 3 <58>
Mealy FSM Schematic
CLK
S'0 S0 Y
r
Reset
Chapter 3 <59>
Moore & Mealy Timing Diagram
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11
CLK
Reset
A 0 1 0 1 1 0 1 1 1
Moore Machine
S ?? S0 S1 S2 S1 S2 S0 S1 S2 S0
Y
Mealy Machine
S ?? S0 S1 S0 S1 S0 S1 S0
Chapter 3 <60>
Factoring State Machines
• Break complex FSMs into smaller interacting
FSMs
• Example: Modify traffic light controller to have
Parade Mode.
– Two more inputs: P, R
– When P = 1, enter Parade Mode & Bravado Blvd
light stays green
– When R = 1, leave Parade Mode
Chapter 3 <61>
Parade FSM
Unfactored FSM P
R LA
Controller
TA FSM LB
TB
Factored FSM P Mode

R FSM
TA Lights LA
TB FSM LB
Controller
FSM
Chapter 3 <62>
Unfactored FSM
Chapter 3 <63>
Factored FSM
TA
Reset
S0 TA S1
LB: red LB: red
P
Reset
S3 S2 P
S0 S1
LA: red LA: red
M: 0 M: 1
LB: yellow LB: green R
MTB
M + TB R
Lights FSM Mode FSM
Chapter 3 <64>
Review: Finite State Machines
(FSMs)
Moore FSM
CLK
M next
next
k state k N
inputs state
state output
outputs
logic
logic
Mealy FSM
CLK
M next
next
k state k state N
inputs state
output
outputs
logic
logic
Chapter 3 <65>
Review: FSM Design Procedure
encodings
Chapter 3 <66>
Timing
• Flip-flop samples D at clock edge
• D must be stable when sampled
• Similar to a photograph, D must be stable
around clock edge
• If not, metastability can occur
Chapter 3 <67>
Input Timing Constraints
• Setup time: tsetup = time before clock edge data must be
stable (i.e. not changing)
• Hold time: thold = time after clock edge data must be stable
• Aperture time: ta = time around clock edge data must be
stable (ta = tsetup + thold)
CLK
tsetup thold
ta
Chapter 3 <68>
Output Timing Constraints
• Propagation delay: tpcq = time after clock edge that the
output Q is guaranteed to be stable (i.e., to stop changing)
• Contamination delay: tccq = time after clock edge that Q
might be unstable (i.e., start changing)
CLK
tccq
tpcq
Chapter 3 <69>
Dynamic Discipline
• Synchronous sequential circuit inputs must
be stable during aperture (setup and hold)
time around clock edge
• Specifically, inputs must be stable
– at least tsetup before the clock edge
– at least until thold after the clock edge
Chapter 3 <70>
Dynamic Discipline
• The delay between registers has a
minimum and maximum delay, dependent
on the delays of the circuit elements
CLK CLK
Q1 CL D2
R1 R2
(a)
Tc
CLK
Q1
D2
(b)
Chapter 3 <71>
Setup Time Constraint
• Depends on the maximum delay from register R1
through combinational logic to R2
• The input to register R2 must be stable at least tsetup
before clock edge
CLK CLK
Q1 D2
CL
Tc ≥
R1 R2
Tc
CLK
Q1
D2
tpcq tpd tsetup
Chapter 3 <72>
before clock edge
CLK CLK
Q1 D2
CL
Tc ≥ tpcq + tpd + tsetup
R1 R2
Tc tpd ≤
CLK
Q1
D2
tpcq tpd tsetup
Chapter 3 <73>
before clock edge
CLK CLK
Q1 D2
CL
Tc ≥ tpcq + tpd + tsetup
R1 R2
Tc tpd ≤ Tc – (tpcq + tsetup)
CLK
Q1 (tpcq + tsetup):
D2 sequencing overhead
tpcq tpd tsetup
Chapter 3 <74>
Hold Time Constraint
• Depends on the minimum delay from register R1
through the combinational logic to R2
• The input to register R2 must be stable for at least
thold after the clock edge
CLK CLK
Q1 CL D2
thold <
R1 R2
CLK
Q1
D2
tccq tcd
thold
Chapter 3 <75>
CLK CLK
Q1 CL D2
thold < tccq + tcd
R1 R2
tcd >
CLK
Q1
D2
tccq tcd
thold
Chapter 3 <76>
CLK CLK
Q1 CL D2
thold < tccq + tcd
R1 R2
tcd > thold - tccq
CLK
Q1
D2
tccq tcd
thold
Chapter 3 <77>
Timing Analysis
CLK CLK Timing Characteristics
A
tccq = 30 ps
B
tpcq = 50 ps
tsetup = 60 ps
X' X
C thold = 70 ps
Y' Y
D
per gate
tpd = 35 ps
tcd = 25 ps
tpd =
tcd =
Setup time constraint: Hold time constraint:
Tc ≥ tccq + tcd > thold ?
fc =
Chapter 3 <78>
Timing Analysis
CLK CLK Timing Characteristics
A
tccq = 30 ps
B
tpcq = 50 ps
tsetup = 60 ps
X' X
C thold = 70 ps
Y' Y
D
per gate
tpd = 35 ps
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tcd > thold ?
fc = 1/Tc = 4.65 GHz (30 + 25) ps > 70 ps ? No!
Chapter 3 <79>
Timing Analysis
Add buffers to the short paths: Timing Characteristics
CLK CLK tccq = 30 ps
A
tpcq = 50 ps
B tsetup = 60 ps
C
X' X thold = 70 ps
Y' Y
D
per gate
tpd = 35 ps
tcd = 25 ps
tpd =
tcd =
Tc ≥ tccq + tcd > thold ?
fc =
Chapter 3 <80>
Timing Analysis
Add buffers to the short paths: Timing Characteristics
CLK CLK tccq = 30 ps
A
tpcq = 50 ps
B tsetup = 60 ps
C
X' X thold = 70 ps
Y' Y
D
per gate
tpd = 35 ps
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
tcd = 2 x 25 ps = 50 ps
Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tcd > thold ?
fc = 1/Tc = 4.65 GHz (30 + 50) ps > 70 ps ? Yes!
Chapter 3 <81>
Clock Skew
• The clock doesn’t arrive at all registers at same time
• Skew: difference between two clock edges
• Perform worst case analysis to guarantee dynamic
discipline is not violated for any register – many
registers in a system!
delay CLK
CLK1 CLK2
Q1 C D2
L
R1 R2
t skew
CLK1
CLK2
CLK
Chapter 3 <82>
Setup Time Constraint with Skew
• In the worst case, CLK2 is earlier than CLK1
CLK1 CLK2
Q1 C D2
L
R1 R2
Tc
CLK1
CLK2
Q1
D2
tpcq tpd tsetup tskew
Chapter 3 <83>
CLK1 CLK2
Q1 CL D2
Tc - tskew ≥ tpcq + tpd + tsetup
R1 R2
Tc
CLK1
Tc - tskew
CLK2
Q1
D2
Chapter 3 <84>
CLK1 CLK2
Q1 CL D2
R1 R2
Tc
CLK1
Tc - tskew Tc ≥
CLK2
Q1
D2
Chapter 3 <85>
CLK1 CLK2
Q1 CL D2
R1 R2
Tc
CLK1
Tc - tskew Tc ≥ tpcq + tpd + tsetup + tskew
CLK2 tpd ≤
Q1
D2
Chapter 3 <86>
CLK1 CLK2
Q1 CL D2
R1 R2
Tc
CLK1
Tc - tskew Tc ≥ tpcq + tpd + tsetup + tskew
CLK2 tpd ≤ Tc – (tpcq + tsetup + tskew)
Q1
D2
Chapter 3 <87>
Hold Time Constraint with Skew
• In the worst case, CLK2 is later than CLK1
CLK1 CLK2
Q1 CL D2
R1 R2
CLK1
CLK2
tccq + tcd >
Q1
D2
tccq tcd
tskew thold
Chapter 3 <88>
CLK1 CLK2
Q1 CL D2
R1 R2
CLK1
CLK2
tccq + tcd > thold + tskew
Q1 tcd >
D2
tccq tcd
tskew thold
Chapter 3 <89>
CLK1 CLK2
Q1 CL D2
R1 R2
CLK1
CLK2
tccq + tcd > thold + tskew
Q1 tcd > thold + tskew – tccq
D2
tccq tcd
tskew thold
Chapter 3 <90>
Violating the Dynamic Discipline
• Asynchronous (for example, user)
tsetup thold
inputs might violate the dynamic
discipline CLK
CLK
button
taperture
D
Q D
Case I
Q
Case II
Q
Case III
???
Q
Chapter 3 <91>
Metastability
• Bistable devices: two stable states, and a
metastable state between them
• Flip-flop: two stable states (1 and 0) and one
metastable state
• If flip-flop lands in metastable state, could stay there
for an undetermined amount of time
metastable
stable stable
Chapter 3 <92>
Flip-Flop Internals
• Flip-flop has feedback: if Q is somewhere between
1 and 0, cross-coupled gates drive output to either
rail (1 or 0) R
N1 Q
N2 Q
S
• Metastable signal: if it hasn’t resolved to 1 or 0

• If flip-flop input changes at random time, probability
that output Q is metastable after waiting some time, t:
P(tres > t) = (T0/Tc ) e-t/τ
tres : time to resolve to 1 or 0

T0, τ : properties of the circuit
Chapter 3 <93>
Metastability
• Intuitively:
T0/Tc: probability input changes at a bad time (during aperture)
τ: time constant for how fast flip-flop moves away from

metastability
• In short, if flip-flop samples metastable input, if you wait

long enough (t), the output will have resolved to 1 or 0
with high probability.
Chapter 3 <94>
Synchronizers
• Asynchronous inputs are inevitable (user interfaces,
systems with different clocks interacting, etc.)
• Synchronizer goal: make the probability of failure (the
output Q still being metastable) low
• Synchronizer cannot make the probability of failure 0
CLK
SYNC
D Q
Chapter 3 <95>
Synchronizer Internals
• Synchronizer: built with two back-to-back flip-flops
• Suppose D is transitioning when sampled by F1
• Internal signal D2 has (Tc - tsetup) time to resolve to 1
or 0 CLK CLK
D2
D Q
F1 F2
Tc
CLK
D2 metastable
tres tsetup tpcq

Chapter 3 <96>
Synchronizer Probability of Failure
For each sample, probability of failure is:
P(failure) = (T0/Tc ) e-(Tc - tsetup)/τ
CLK CLK
D2
D Q
F1 F2
Tc
CLK
D2 metastable
tres tsetup tpcq

Chapter 3 <97>
Synchronizer Mean Time Between Failures
• If asynchronous input changes once per second,

probability of failure per second is P(failure).
• If input changes N times per second, probability of failure
per second is:
P(failure)/second = (NT0/Tc) e-(Tc - tsetup)/τ
• Synchronizer fails, on average, 1/[P(failure)/second]

• Called mean time between failures, MTBF:
MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc - tsetup)/τ
Chapter 3 <98>
Example Synchronizer
CLK CLK
D2
D Q
F1 F2
• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

T0 = 150 ps tsetup = 100 ps
N = 10 events per second
• What is the probability of failure? MTBF?
Chapter 3 <99>
Example Synchronizer
CLK CLK
D2
D Q
F1 F2
• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

T0 = 150 ps tsetup = 100 ps
N = 10 events per second
• What is the probability of failure? MTBF?
P(failure) = (150 ps/2 ns) e-(1.9 ns)/200 ps
= 5.6 × 10-6
P(failure)/second = 10 × (5.6 × 10-6 )
= 5.6 × 10-5 / second
MTBF = 1/[P(failure)/second] ≈ 5 hours
Chapter 3 <100>
Parallelism
• Two types of parallelism:
– Spatial parallelism
• duplicate hardware performs multiple tasks at once
– Temporal parallelism
• task is broken into multiple stages
• also called pipelining
• for example, an assembly line
Chapter 3 <101>
Parallelism Definitions
• Token: Group of inputs processed to
produce group of outputs
• Latency: Time for one token to pass from
start to end
• Throughput: Number of tokens produced
per unit time
Parallelism increases throughput
Chapter 3 <102>
Parallelism Example
• Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation
– 5 minutes to roll cookies
– 15 minutes to bake
• What is the latency and throughput without parallelism?
Chapter 3 <103>
Parallelism Example
• Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation
– 5 minutes to roll cookies
– 15 minutes to bake
• What is the latency and throughput without parallelism?
Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = 1 tray/ 1/3 hour = 3 trays/hour
Chapter 3 <104>
Parallelism Example
• What is the latency and throughput if Ben
uses parallelism?
– Spatial parallelism: Ben asks Allysa P. Hacker to
help, using her own oven
– Temporal parallelism:
• two stages: rolling and baking
• He uses two trays
• While first batch is baking, he rolls the
second batch, etc.
Chapter 3 <105>
Spatial Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50
Time
Tray 1 Ben 1 Ben 1
Roll
Parallelism
Tray 2 Alyssa 1 Alyssa 1

Spatial
Bake
Tray 3 Ben 2 Ben 2
Legend
Latency = ?
Throughput = ?
Chapter 3 <106>
Spatial Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50
Time
Tray 1 Ben 1 Ben 1
Roll
Parallelism

Spatial
Bake
Tray 3 Ben 2 Ben 2
Legend

Throughput = 2 trays/ 1/3 hour = 6 trays/hour
Chapter 3 <107>
Temporal Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50
Time
Tray 1 Ben 1 Ben 1
Parallelism
Temporal
Tray 2 Ben 2 Ben 2
Tray 3 Ben 3 Ben 3
Latency = ?
Throughput = ?
Chapter 3 <108>
Temporal Parallelism
Latency:
time to
first tray
0 5 10 15 20 25 30 35 40 45 50
Time
Tray 1 Ben 1 Ben 1
Parallelism
Temporal
Tray 2 Ben 2 Ben 2
Tray 3 Ben 3 Ben 3

Throughput = 1 trays/ 1/4 hour = 4 trays/hour
Using both techniques, the throughput would be

8 trays/hour
Chapter 3 <109>

Chapter 3

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Chapter 3

Digital Design and Computer Architecture, 2nd Edition

• Stores 1 bit of state in the state variable, Q (or Q)

Set the output 0

Reset the output 0

• No inputs and 1-3 outputs

• Loads next state at clock edge

LA: green LA: yellow

inputs next state logic state register

inputs next state logic state register output logic outputs

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

Mealy FSM: arcs indicate input/output

Factored FSM P Mode

tpcq tpd tsetup tskew

tpcq tpd tsetup tskew

tpcq tpd tsetup tskew

tpcq tpd tsetup tskew

tpcq tpd tsetup tskew

• Metastable signal: if it hasn’t resolved to 1 or 0

tres : time to resolve to 1 or 0

τ: time constant for how fast flip-flop moves away from

• In short, if flip-flop samples metastable input, if you wait

tres tsetup tpcq

tres tsetup tpcq

• If asynchronous input changes once per second,

• Synchronizer fails, on average, 1/[P(failure)/second]

MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc - tsetup)/τ

• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

Parallelism increases throughput

Latency = 5 + 15 = 20 minutes = 1/3 hour

Tray 2 Alyssa 1 Alyssa 1

Tray 2 Alyssa 1 Alyssa 1

Latency = 5 + 15 = 20 minutes = 1/3 hour

Tray 2 Ben 2 Ben 2

Tray 3 Ben 3 Ben 3

Tray 2 Ben 2 Ben 2

Tray 3 Ben 3 Ben 3

Latency = 5 + 15 = 20 minutes = 1/3 hour

Using both techniques, the throughput would be

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