80386 Microprocessor

80386 Microprocessor is a 32-bit processor that holds the ability to carry out
32-bit operations in one cycle. It has a data and address bus of 32-bit each.
Thus has the ability to address 4 GB (or 232) of physical memory.
Multitasking and protection capability are the two key characteristics of the
80386 microprocessor. 80386 has internal dedicated hardware that permits
multitasking.
Q) Explain the salient features of 80386 processor.

Features of 80386
• As it is a 32-bit microprocessor. Thus has a 32-bit ALU.
• 80386 has a data bus of 32-bit.
• It holds an address bus of 32 bit.
• It supports physical memory addressability of 4 GB and virtual memory
addressability of 64 TB.
• 80386 supports a variety of operating clock frequencies, which are 16
MHz, 20 MHz, 25 MHz, and 33 MHz
• It offers 3 stage pipelines: fetch, decode and execute. As it supports
simultaneous fetching, decoding, and execution inside the system.

Operating modes of 80386

80386 supports 3 operating modes: real, protected, and virtual real mode.
In the protected mode, 80386 microprocessor operates in a similar way like
80286 but offers higher memory addressing ability.
In virtual mode, the overall memory of 80386 can be divided into various
virtual machines. And all of them acts as a separate computer with 8086
microprocessors. This mode is also called virtual 8086 mode or V86 mode.
The other one is the virtual real mode; this mode allows the system to execute
multiple programs in the protected memory. And in case a program at a
particular memory gets crashed then it will not cause any adverse effect on the
other part of the memory.
The Internal Architecture of 80386 is divided into 3 sections.
1 Central processing unit (CPU) a. Execution Unit b. Instruction Unit
a) Execution Unit: Reads the instruction from the instruction queue and
execute the instruction. Consists of three subunits: control, data and
protection test unit
I) Control Unit: It contains microcode and special hardware allows processor to
reduce time required for execution of multiply and divide instruction. It also
speeds the effective address calculation.
II) Data Unit: Responsible for data operations requested by the control unit. It
contains ALU, eight 32-bit general-purpose registers and 64-bit barrel shifter.
The barrel shifter is used for multiple bit shifts in one clock. Thus, it increases
the speed of all shift and rotate operations.
III) Protection Test Unit: checks for segmentation violations under the control
of the microcode.
b) Instruction Decode Unit: Takes instruction byte from the code prefetch
queue and translates them in to microcode. The decoded instructions are then
stored in the instruction queue.
Q)Briefly explain the memory management of 80386.
2 Memory management unit (MMU) a. Segmentation Unit b. Paging Unit
a) Segmentation Unit:
Translate logical address to linear addresses at the request of execution unit.
Compares the effective address for the length limit specified in the segment
descriptor. Adds the segment base and the effective address to generate linear
address. Before calculation of linear address, it also checks access rights. It
provides a 4-level protection mechanism for protecting and isolating the
system code and data from those of the application program
b) Paging Unit:
Translate linear addresses generated by the segmentation unit into physical
addresses. If paging unit is not enabled, the physical address is the same as the
linear address. It gives physical address to the Bus Interface Unit to perform
memory and I/O accesses. It organizes the physical memory in terms of pages
of 4kbyts size each.
3 Bus interface unit (BIU) :Is the 80836 communications with the outside
world. It provides a full 32-bit bi-directional data and 32- bit address bus.
Responsible for following operations
I) Accepts internal requests for code fetch and for data transfers from the
code fetch unit and from the execution unit. It then prioritizes the request and
generates signals to perform bus cycles.
ii) It send address, data and control signals to communicate with memory and
I/O devices
iii) It controls the interface to external bus masters and coprocessors.
iv) It also provides the address relocation facility.
Central processing unit is further divided into Execution unit (EU) and Instruction unit
(IU)

Instruction Decode Unit

We know that instructions in the memory are stored in the form of bits. So,
this unit decodes the instructions stored in the prefetch queue. Basically, the
decoder changes the machine language code into assembly language and
transfers it to the processor for further execution.
Execution Unit
The decoded instructions are stored in the decoded instruction queue. So,
these instructions are provided to the execution unit in order to execute the
instructions. The execution unit controls the execution of the decoded
instructions. This unit has a 32-bit ALU, that performs the operation over 32-
bit data in one cycle. Also, it consists of 8 general purposes as well as 8 special
purpose registers. These are used for data handling and calculation of offset
address.
Q) Explain the interrupt handling mechanism in 80386 processor
A) Interrupts and Exceptions
The 80386 has two mechanisms for interrupting program execution:
1. Exceptions are synchronous events that are the responses of the CPU to certain
conditions detected during the execution of an instruction.
2. Interrupts are asynchronous events typically triggered by external devices
needing attention.
Interrupts and exceptions are alike in that both cause the processor to temporarily
suspend its present program execution in order to execute a program of higher priority.
The major distinction between these two kinds of interrupts is their origin. An exception
is always reproducible by re-executing with the program and data that caused the
exception, whereas an interrupt is generally independent of the currently executing
program.

Q) Discuss the register organization of 80386 processor.

The 80386 contains a total of sixteen registers. register may be grouped into these basic
categories:
• General registers. These eight 32-bit general-purpose registers are used primarily
to contain operands for arithmetic and logical operations.
• Segment registers. These special-purpose registers permit systems software
designers to choose either a flat or segmented model of memory organization.
These six registers determine, at any given time, which segments of memory are
currently addressable.
• Status and instruction registers. These special-purpose registers are used to record
and alter certain aspects of the 80386 processor state.
Explain the Memory Paging Mechanism in 80386 processor

The memory paging mechanism located within the 80386 and above allows any
physical memory location to be assigned to any linear address. The linear address
is defined as the address generated by a program. Within the memory paging unit the
linear address is invisibly translated into any physical address.