2022 IEEE 14th International Conference on Computer Research and Development
A Survey for Realizing In-Memory Computing
†WenKun Xiao
International college of cqupt
Chongqing University of Posts and Telecommunications
Chongqing, China
*wx35@nau.edu
2022 14th International Conference on Computer Research and Development (ICCRD) | 978-1-7281-7721-2/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICCRD54409.2022.9730467
†These authors contributed equally
Abstract—To resolve high energy consumption and low
efficiency of traditional Von Neumann architecture-based
memory, in-memory-computing (IMC) was proposed. It realizes
computing and storing at the same place. A variety of IMC
accelerators have been invented. This article introduces the IMC
technology and describe three typical examples of them: DRISA,
C3SRAM and Voltage-controlled Magnetic Tunnel Junctions.
The first two models are introduced in detail. All of these models
reduce the energy consuming and increase the data handling
speed significantly which is obvious in AI processing. The
limitations which require further research in future are also
discussed in this article.
Keywords—In-memory computing (IMC), C3SRAM, DRISA,
Voltage-Controlled Magnetic Tunnel Junctions (VCMTJ)
I. INTRODUCTION
Nowadays, computers are generally depending on the Von
Neumann architecture, computing and storage are run in two
different places. Data is taken from the storage unit and
transferred to the processing unit. The process unit is also
where the calculation takes place. Then it will be taken back to
the memory unit to complete the storage. In-memory
computing (IMC) is a system that computing within the
memory. The IMC technique makes the algorithms embedded
on the memory particles. This technology greatly reduces the
time and energy consumption required for calculation. In
addition to reducing the latency and energy costs associated
with data movement, IMC has the latent energy to highly
improve the required of calculation time and the complexity of
some computing tasks. This is mainly caused by the massive
parallelism provided by a dense array of millions of memory
devices performing the computations. By introducing physical
coupling between storage devices, the computational time
complexity can be further reduced. By blur the boundary
between processing and memory units, this property is also
shared with highly energy efficient mammalian brains where
memory and processing are deeply intertwined [1]. However,
these sacrifices that the generality provided by conventional
methods are functionally distinct from each other. At present,
the implementation of the IMC is based on volatile, and the
existing technologies include more mature SRAM or DRAM
construction, some new storage devices and new materials
construction which are based on non-volatile, such as Voltage
Controlled Magnetic Tunnel Junctions.
978-1-7281-7721-2/22/$31.00 ©2022 IEEE
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†YangSong Shi
Glasgow college
University of Electronic Science and Technology of China
Chengdu, China
*2019190503030@std.uestc.edu.cn
In this article, we introduce two PIM models about
achieving IMC, and we also explain working analogue and
stochastic computing schemes and comply principle. Finally,
we compare the advantages and disadvantages of the two
models and make a conclusion of our review.
II. TYPES OF IMC ACCELERATOR
In recent years, several categories of PIM are coming out,
such as SRAM-based, DRAM-based and Voltage-Controlled
Magnetic Tunnel Junctions (Voltage-Controlled MTJ). This
paper introduces two of them in details.
A. C3SRAM
The C3SRAM is an SRAM module whose circuit is
embedded in bit units and peripherals to hardware acceleration
on a neural network with binarization weight and activation [2].
It can assert all its rows at the same time and use analog
voltage at the read bitline node [2]. In addition, the C3SRAM
is installed with a analog-to-digital (ADC) in each column to
enable the PIM to have parallel vector-matrix multiplication in
every cycle [2]. It has been tested that the C3SRAM saves
3975 times energy compared to traditional digital baseline
operations [2].
B. DRAM
The DRAM has hierarchical bank-level design, which helps
reduce bitline length [3]. Typically, it uses voltages in
capacitors to represent binary data [3,4]. A variety of advanced
PIMs are based on DRAM, such as Newton-DRAM
Accelerator [5], DrAcc [6] and DRAM-based Reconfigurable
In-Situ Accelerator (DRISA) [7]. This paper will focus on
DRISA accelerator. It can perform several functions based on
different combinations of simple Boolean logic gates [7]. The
DRISA could help realize 8.8x speed up and 1.2x better energy
efficiency than ASICS, and 7.7x speed up and 15x better
energy efficiency than GPUs [7].
C. Voltage-Controlled Magnetic Tunnel Junctions
The voltage-controlled MTJ uses voltage and current to
represent input signals, based on voltage-controlled magnetic
anisotropy (VCMA) and Hall effect (SHE) respectively [8]. It
can realize various complex functions by combining multiple
logic cells [9]. The write and read delay and energy
consumption of VCMA-MTJ device are low [9]. It could be
profitable for massive integration and application in future.
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 III. C3SRAM
A. The superiority of computers
C3SRAM is an IMC SRAM macro which is depended on
the capacitance coupling computing (c3) [10]. The prototype
macro is 256×64 in size and computes 64 256-input binary-
MAC operation (bMAC) in parallel. This macro can support
the networks of various size by used in a modular fashion. The
65-nm prototype chip demonstrates 671.5-TOPS/W energy
efficiency and 1-638 GOPS throughput, which is 3975×
improvement in energy–delay product (EDP), compared to the
digital baseline. The accuracy for the MNIST data set is about
98.3% and 85.5% for the CIFAR-10 data set [2]. The
architecture of C3SRAM IMC macro is shown in Figure 1.
Fig.1 Architecture of C3SRAM IMC macro [2].
B. Memory Array Operation
Fig. 2 shows the 8T1C bit cell layout of the proposed
design, the circuit diagram of the two-bit cells is showed in one
column, and the table of XNOR operands. Under the same
logic rule, the bit cell is 80% larger than the traditional 6T bit
cell, because one capacitor and the two additional pass
transistors occupy 27% of the bit cell area. The capacitor is
implemented as MOSCAP for high capacitance density. A
MOMCAP covering the area of a C3SRAM bit cell has 80%
lower capacitance than Cc(~ 5 fF ) [2].
Fig. 2. C3SRAM bitcell design and in-cell bMAC operand table [2].
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C. The bMAC processing of C3SRAM
The Fig. 3 shows the bMAC processing of C3SRAM. Two
steps are involved in this processing. Every step can be
finished in a half cycle duration. In step 1, every column’s
MBL is charged in advance via the footer TFT to
·VDR. To narrow the voltage oscillation on the
MBL nodes, VRST is set close to the voltage corresponding to
bMAC output of 0 (actually 0.4 V), because typical bMAC
outputs in BNNs have an arrow distribution close to 0 value. In
this step, MWL and MWLB of each row are reset to VRST, so
that their voltage is near to 0V on bit cell capacitors, and the
capacitors are access to the circuit in parallel so that the two
node can share reset to the same voltage, as shown in Fig. 3
(bottom left). In step 2, the footer is turned off. The 256 inputs
activation, which is denoted as Ini , is applied to 256
in parallel. If Ini = +1(−1) , MWL is driven
from VRST to VDR (VSS), whereas MWLB is driven to VSS
(VDR). If , both and MWLB remain at VRST
without consuming dynamic power [2]. When the weight is +1
(−1), the voltage ramping via T7 (T8) induces a displacement
current through capacitor in the bit cell, whose magnitude is
presented as below:
Ic = Cc  d V MWL ( B ) / dt ()
Fig. 3. Capacitance coupling based in-memory computation of bMAC [2]
The charge transferred from the bit cell to MBL is:
t1 1
QCi =  Icdt = CcVDR ()
0 2
where t1 is the time it takes VMWL to reach VDR. The shared
MBL voltage is set to as below:
 256
VMBL = CCVDR  ( XNORi) /( 256CC + C p )
1 AND B, otherwise when ‘C’ is 1, the output is A OR B [6].
Through these formulas, MOSCAP’s high capacitance
density provides a bMAC transfer curve with a wider full-scale
range (FSR) than the less capacity dense MOMCAP [2] does.
Given the same level of MBL parasitics, the FSR loss got by
MOMCAP would be about 80% higher than the one got by
MOSCAP.
D. Advantages and Limitations of C3SRAM
In order to make the speed and power of this method to be
fully used, such as those in the achieving of Vesti [11], are also
necessary to stop the memory macros from waiting for the next
input import or else it would take a lot of time in activation
data movement. Therefore, compared with a direct substitution
of SRAM which is depends on the traditional von Neumann
architecture, C3SRAM can be fully used in a stand-alone
module.
TABLE I. ACCURACY COMPARISON
Neural Network Baseline
Dataset
Network Topology Accuracy
In Ambit, three DRAM cells are used to accomplish simple
() logic computing. In Figure 4, when ‘C’ is 0, the output is A
However, DRISA consists of a mass of DRAM memory
arrays that can perform Boolean logic operations and various
functions by combining them in different ways [7].
B. Architecture of DRISA for Computing
The computing methods have two solutions, including
3T1C solution and 1T1C solution [7]. Compared to the
traditional DRAM, the former uses the cells themselves for
computing, it is composed of two read/write transistors and a
transistor for decoupling capacitor [7,12]. The latter adds extra
circuits which attached to the SAs for computing [7]. However,
both these two methods share the same shift design. The
solutions enable the in-situ computing as well [7].
C. Architecture of DRISA for Data Movement
For data movement, inter-lane SHF circuits, as shown in
Figure 5, are used within subarrays. It can thus shift a row from
and to its adjacent lane, and lane-FWD circuits in Figure 6 are
used for moving data between any two lanes [7].
Test
Chip

784FC-512FC-
MNIST MLP 512FC-512FC- 98.7% 98.3%
10FC

128C3-128C3-
MP2-
256C3-256C3-
CIFAR- VGG-like MP2-
88.6% 85.5%
10 CNN 512C3-512C3-
MP2-
1024FC-
1024FC-10FC

Fig. 5. The inter-lane SHF circuit [7]

Table Ⅰ shows that the comparison for the C3SRAM’s
accuracy of MNIIST and CIFAR-10. This accuracy result is This configuration help save the space since all lanes share
taken by directly measuring the whole process, this table can one data-shifting wire. The data can be move to both left and
prove that C3SRAM has high energy efficiency and throughput, right based on the ping/pong phases which decide the odd or
the mapping of C3SRAM could be used as computational even shift occurs [7]. As the Figure 5 shows, the four parallel
primitive for larger BNNs for harder machine learning tasks [2]. blue lines are even, ping, odd, pong respectively.
IV. A DRAM-BASED PIM ACCELERATOR-DRISA
A. DRISA
As several DRAM-based PIMs are mentioned in section 2,
in this section, the paper will focus on a novel PIM named
DRAM-based Reconfigurable In-Situ Accelerator (DRISA) [7].
The Ambit DRAM structure is shown in Figure 4.

Fig. 6. The lane-FWD circuit [7]

The configuration shown in Figure 6 is the lane-FWD

circuit. It supports the random read and write from or to any
Fig. 4. The hierarchical structure of Ambit [6] arbitrary line [7].

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D. Architecture of DRISA for Controllers
The controllers of DRISA include four levels, including
chip, group, bank, and sub array-level controllers [4,7]. The
first two levels are responsible for decode and data movement,
and the bank level convert the instructions and µ-operations
into addresses, vector lengths and control codes [7]. The
subarray level has address latches, decoders and counters. In
addition, the cell array is separated to data and compute regions,
which helps reduce the overhead to 19.02% [7]. However,
another previous article introduced three kinds of bank
scheduling: all-bank, per-bank, and bank-group. Besides, the
matrix sizes would also influence the performance scalability
[6].
Since the DRISA is a co-processor, its integration methods
are the same as GPU or FPGA [7]. However, for software
component, it requires a special frame programming language
as well as a corresponding compiler, like CUDA or AP and
SDK. For hardware support, both PCIe and DIMM are capable.
The PCIe has consistent power delivery supply and
sophisticated control system. The DIMM require DRISA looks
like DDR in interface but has an accelerator’s function [7].
E. Advantages and Limitations of DRISA
DRISA does not have the charge-leak challenge as every
bitwise logic operation is before copying data to the source and
target rows [7,13]. In addition, in the accelerating aspect,
DRISA shows 8.8x speed up and 1.2x better energy efficiency
compared to ASICS, and 7.7x speed up and 15x better energy
efficiency than GPUs [7].
However, when calculating floating points, DRISA has
limitations. Since all lanes in a subarray share the same
controller but the floating-point calculation is data dependent in
controller [4,7], as a result it is not beneficial to the accelerator
while taking floating points performance [7].
V. CONCLUSION
In this paper, we have discussed about the two different
PIM models for achieving in memory computing, and this
paper also discusses their advantages and disadvantages. Our
study also explains the process of they work, therefore this
paper can help the people selecting an appropriate models to
achieving IMC in the future and getting deeply understanding
of the process of realizing IMC.
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