.

delays
/ WIN (Tw)
wait state and
to 8086 system timing diagram During " 1,0122 Timings
1 ' '

I Ty / ( Ta )
'
I the buses the
rehired delay
'

Ti Ti same
signals remain
'
T Tz Ts Tw Tz
-
on
, , " , Ty
(a)
required count =

Address held at lakh doesn't

-
-

output change .
n -
1-
← period
1 I

! ! ! ! ! ! ! I / -
in
/ IT E. RJ doesn't
change during wait
no
.f dock states

1 i ! ! l '
state required ( ) to eneuite
-
. I , . n

↑ -
the
delay loop
once .

wait idle state

clock
one
cycle
( state for 10mHz ( say )
No
.LI/-atesfne-neution
-
0.1ms
machine 400ns ( 0.4ns )
read operation or write
operation
-

cycle ☒ or ex ,
count
-

4 -

cycle usually of label :

DEC ex 2
-

a machine cornish more

2 NOP
33
of
-

no - states .

•
JNZ label -

16
instruction
time required to fetch and execute an RET -
s

tor execution of loop once

-
instruction cycle
no -

f dock cycle
=
21-3+16 = 21

contain more
cycle
or
An instruction one
may time required for execution of loop once

machine
cycle .

= nT

And a machine cycle contains one or more

= 21×0.1×10-6
states .

INS
100ms =
2
Td
-
=
say ,

Tw
* wait state 100×10-33
-

i. N =

device 47619,0
required by
the =
↳ time
¥-6
count
=
BAO ] H =

ROM)
to send or receive data
function for delay 9
i. e
;
to
respond .
Unruly we write a

when This is more efficient

call it
necessary
.
.

Usually no Twin RAM C- : faster

response) when JNZ is satisfied q loop is initiated again

while
- 16 cycles
fuel
* say Queue is at some
point terminated
JNZ is not satisfied { loop is
is and at the same instant
CPU
processing
read
-

4 cycles .

there's no
ongoing
or write
operation
state Td = 4 ✗ ° 'm ' +
(2+33)×47619 ✗ 0 . In
-
Idle .

enact
-1M
+ 16×47618 ✗ 0.1Mt 4×1×0

put address bus

Say ,
T
,
→
processor
on
1- 8 ✗ 0 -
IN

ready to read the date

Tz →
processor 100 ms = 0 - IS
= 99.99ms ≈

{
write by processor
.

B. Ty →

count exceeds
for loos →
Say delay
=

FFFFH
if processor
is not
ready Tw
for this both inner and outer loops
write wide are created to meet the
delay time .

read wide operation

operation
'

I l
, '
!
→ MOV BX ,
count I

÷: i
'
BIBB

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NOP
CX .
count 2

i i
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t ' ' ! ! DEC BX

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ap ,
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y
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software
→ hardware [ INTR .NmI
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mainline what's the
advantage of writing
means
of getting interrupts
→ software
program -2
Interrupt hardware?
flags sp=sP interrupt over
Push

↓
> >
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service

[
instruction
-

interrupt clear
procedure TNT 2- software int - -

er ror condition
produced oneention clear TF
→ hardware
sp=sP -2 when NMI is set
by execution of (
Int type , push cs
just In t

E- NTO )
PUSH IP sP=sP - 2 IRET
instructor .

Fetch ISR
>
instead
of giving
how -
high signal
r
address
En : by
dividing
zero -

in the hardware and then

making
execution pop IP sP=sPtv prove
check for INT we can
directly
processor
,
after instruction ,
* every
software interrupt
POP cs sP=sP+r write the
corresponding
.

~
checks for interrupts .

pop flags sP=sPtr

INTR → hardware pin ,

interrupt
" ""
for

/ tmaskable
locations
→ each interrupt memory
↳ checks If
flag
→
current 4

/
instruction
interrupt
# starting
address
of ISP

I
internal
/ 3
t

interrupt vector
→ use
(32-255)

§
yes
interrupt acknowledge
=
interrupt Inta →
( or , interrupt pointer
& controller is
NO
9 8259
-

interrupt priority
table referred as

used multiple
•

Push when
vector table
interrupt
NMI flags
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TF 9

µ a•r
◦ • -

imempttnpes
YES GTF If are cleared .

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FF=l
-

PUSH
dedicated interrupts
1 CS QIP
0-4
µ , 7 STE in INT
?
q,
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_

> IF _

type
(5) ( divide by zero , ,
interrupt call interrupt 2
°ᵈe
interrupts
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service routine non -

8086 8259
overflow
TF _ execute user
break
point ,
-
type code ←

}
b ←
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y b
{ IRO
interrupt
f-
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°
interrupt <
procedure <
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←
inputs
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ene cute
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by INTEL
next
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80386
miwopw who
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pop flags
80486
I
return
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> INTR
interrupt INT
procedure for hardware software

/
or

( 2214
interrupts

machine
cycles

"
are
" " ° 2
acknowledge

{
""
00001 IP ( H)
sent to 8259 after (INTR → If = 1)
00002 CS CL)

00003 CS CH )
1st int acte mlc cycle
00004

{
type
- l
00005 ↓
8086 floats data bus line
00006
ADO -
AD
, }
00007
and then send int ack pulse
00008

{ £
◦ ◦◦◦ 9
On INTA olp pin
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type
0000A
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get ready
second int ack Mlc cycle
-
pulse through INTA Otp
003 FFH
then 8259 puts interrupt type [ ADO -
AD >
)
and it is need by 8086 .

Any low -

high transition signal at NMI

from sources interrupt requests
many ,

does type - 2
processor
are received by 8259 .
But 8259 prioritizes
after
allowing
to
after proc recognizes NME
,
it goes
among all requests ,
one

the contents of 00 other

:|:#
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/ abnormalities
can be dealt through NME .

when of
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type of only I
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distinguish b/w RAM { Rom
chips
line is used
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,
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highest A ,] is 1 for EPROM
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to select even bank chips -

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what if NMI
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in the above En .

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and
but then it
goes
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routine decoder
ifp A ,} Ao BHFT
to
checks for interrupts again q gets word transfer o o o even
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know that NMI is set and now it on

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enecutes
type 2 interrupt service routine
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byte transfer 0 0 I only even address RAM

or
Do -
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0 I 0
only odd address RAM

Interface
on
Dg Dig
-

2 4K ✗ 8 EPROM
ROM
{ odd address

/
even
chips

/
RAM word ' ° °
2 412×8

the address
range byte i ◦ I only even ROM
① - what is
memory
f each
chip .

byte 1 I 0
only odd ROM

reset
when Soso is
booting process

stored in Rom )
after
resetting ,
8086
goes to the

address FFFFOH accommodated in Rom chip .

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design in a
we

way
that the Rom
chip can accommodate

ffff OH address -

should be 18 bit each) for even E odd address banking .

chip pair
-

a
* * * Always memory

/
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Aia Aig An Alb A A A

13 ; -112 All Ato Ag Ag AT
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I

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i
EPROM 8K ✗ 8

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1
- - - - -

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am
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particular memory chip .( when the addresses

when chips have diff isizes → Hardware

all the
memory
all
connections

independently RAM chip ? to be made by

wring Us .
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start RAM address at 000000M

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1

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starting
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address A 000014
starting
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pair of memory chips ,
we
split

12143 -

8 KB 1- 4 KB ( powers L 2)
identical
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should be

12k$ 4kBt4kB 241dB

-
-

ZKB + ZKB -

2 ZKB

2k +2k

}
done
for
interfacing Spain
is
memory mapping
continuous as
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}
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,
I Rom

!
7-
unused address
livest used
decoder
in
?⃝
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#

- to read status of switches

Sw ,
to swg
HB Say address of port =
074014
LB
Ai -
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to be
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dedicated
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mapped isolated Ilo MOV ,

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memory
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,
DX

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devices viewed f- of FF te
,

viewed ( 0500h]
}
as MOV Al
Ilo devices Ito devices
,

as memory : dedicated to
felt
distinct Ilo denim { locations q ≤•◦ on
transfer
addressed accordingly addressed Parallel data
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accordingly .

:
FFFFFH
bit address
16
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-
man
2° 10
bit address simple I

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min g
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ax
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64 KB IIP s implies complex

hardware
☐ ✗=
Ga KB
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Me strobe /
I 0

µ_
is more
words Con as there
IIP
or 32 k
address decoding .

words
32k
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Any instruction
can

for this In Gout be used Also am Dat

ᵗᵗᵈ
.

be mode
addressing
can
instructions
used
used for can be
only AL, AX
wrto
? As there is flenibititl when date almost remains the same

reading
↳ mom time
( significant data
change)
.
i e no
;
-

fast in
operation ,

less complex
hardware
addressing -

simple Ilo
interfacing
is
adopted
operation gets
9
hardware En :
temp measurement
sluggish
.

more
becomes if
complete
. Now consider a
keypad ,
we use
simple
1=10 here ,
some i
/p data
given through
keypad might get lost

so instead once i
/p data is
put on the

bus
,
a low strobe signal is
given
=
ÉTB = ↑

through software ,
one can check whether

strobe is made low or not .

-
Poling
technique
 check for strobe selected here ?
can also
give an
interrupt to
En : out son ,
AL -

9. which port is

pulse .
-

interrupt technique E.
→ SNH
010-0 / °
-

I 000

when data is
changing very rapidly E i
/P → A. Ao
A acts
-
data is sent from port A
{ port as

still
device is
sending a strobe signal olp port here

loss ace
there
might be chance
of data
.

a
IN ALI 8411
all port cats
Cot
processor might not
acknowledge -
data
goes to port C
{
here
i / p port
.

as
that
pulses being sent to
the strobe are
dat
fast and
continuously
.

Same issue even → " " "

" ""
" " " "" " " '

when there strobe

pulses are
passed down
different might
wer to applications processor
from processor
,

to other devices
transfer
.

data schemes
of
.

use one these

Therefore ,
we have to ensure that the

strobe signal is acknowledged * "

"
"
"
mmabk
peripheral inwp.ae ,, , ,

8255
-
Handshake data transfer scheme

is used to handle all these diff schemes

for effective coordination .

and tells which scheme is to

processor
single handshake /
I 0 scheme :
used
-

→
be .

25110122
8255 programmable peripheral
interface
/p
É
peripheral ← easy implementation of
deni " parallel I10 in
-
=

port pa [ , ""

{ }
,
" ""
device
☐ A
" 393 Pas
8086
-

processor port
PA [3 38 ] PAG
,

i. A§ PAO [ 4 37 ] PAY
RI [ 5
36 ] JR
is [ 6
359 Reset
and [ 7 8255
34 ] Do
A , [ 8 PPI 33 ] D,

A ◦ [ 9 323 Dz
Here data
FB -

#y-
,

PC> [ 10
31 ] D
]

being sent
PCGC "
3° ] ☐
4

ACK
#
without
confirming Pls
PC4[ 13
[ '2
29 ] D;

! whether
processor pco [
,q
V8 ]

27
D8

not 3D >
is
ready PG
'
or [ is
"c
#- P
•
data Pack 25 ]

}
PB >
- PC ] [ 17
I
243 PBG
PBo[ 18

{
233 PBS
'9
PB , [
→ Double handshake I / 0 scheme : -
Port 223 Pity
[ 20
PB 21 ] PB }
, -

even more effective

9 devices
whether is ready or
241=10 lines b/w processor
Here device checks processor
Port A -8 bit Ilo port
not
Pat hit port
?False
B Ilo
device processor s
-

from to
① first STB

confirms that is ready through Port C -

s bit Ilo port

② processor it
4 bit i
/P Port
him 4- bit ports
-

-
two

Acknsignal . or

4 bit olp port

③ 2nd Bhisphulse from protestor
.

ST device to

control
^

bit
single
-

data
{ Device
puts lines .

on

bit 8- bit
: 8255 can do single , 4- bit {
from processor device
saying
④ low Ack to
ports
that data is read .

☐◦ -
p → g- bit bi -
directional data lines
,

And reads sends the date through

cycle goes
or
on
processor
.

data lines from ilp or

ofp ports respectively
Both
filing { interrupt techniques
used used for handshake

=
be Port be
un * c
pins can
.
-

↓ here port acts

/p parts ?
operations
. -
c as i .

.
but
complex
simple some activated 'll
but tedious just → Once Reset in 8255 is ,
it

should hardware
(processor initialize all
ports as i
/ p ports .

it structure
check for
) needed critical date
everytime is •
Ip ports ?
.

not
why as -
some

I will be sent out as

best when
junk data ?

7 diff processorsused
°
are being → A Ao of 8255
,
-

SOH O O
-
port A

B
82M 0 I -

port
8411 I 0 -
port C

8611 1 1 - control word register

?⃝
 ~
I → "" ↳ Forint when port ☐ is in mode -0
,
Pco , PG { Plz can
≤
put a
lines with Port A
used 1=10
Group
# # 4=>110 be as Same
goes
.

> A (8) ( IIP)

control PA
,
-
PAO

↓ G port Alolp) .

data
Porte =

bus T ) ←→ upper
# I /° mod
butter (4)
mode
initialized
" -2
Pc _

A be in
4 port
↑ only
> can

↑
Port < ≤
used as
bidirectional handshake
# cower data transfer .

RTs →
(4)
.

read /
FR →

write
>
Group Data can be i
/p or Otp on the same 8 lines
of Port A

control ≤
-

is
A →
control Port B
)
#-) DT
,

£ ( for bi dir HS
of
↳
→ mode -2 -

A. (g) Applications
PB -

PBO
☒"
"→
to
,
wants to entered the data bus for slave miwp~wTh
B
→
when processor
°
Group
Est control → for data to be transferred to discs .

lines

/
Mode - 2 Handshake

Port A PC ] to PC >
[ PC ]
Pc
,

3
4,5

, 6,7
-

-
i /P
0
/P
)
mode
0£ Here .
when
port is in mode -1

handshake Porte Port B Port a →

pco ,
pq ,
Pc, - handshake signals
48¥ %¥¥É%↑±w
no
are
signals
revived / ✓ × when
port B in mode -
0

Pc PC
Pcp
-

} , Pc , -

PB > PBO -

pa , -
pp ,
→
pco -
pcz used as I 0 / Port
~ A
code
"
pass control word to control word register for particular
mode a

handshake Port B PG PG Pez Pc ] the PCs PCGPC> Porta configure

signal to .

If / ,¥ / ¥BE☐É%±n
↑
/ ¥14T
µ,
control words
✓
→
Constructing
a
sending 8255

/
or
≤☐
ga y,
format
, ,,
,, ,
definition control word
g. µ, ,
"
↳ mode
◦
pa
_
pa ,
being operated
or
PB > PB , ,
-

ports
are
To what modes
-

the
ACKB FBA ◦r

ALKA
# handshake
-

control word format

Or
↳
1=10 TP signals bit get / reset

~ A
-

exclusively for port C

; set / rest the °
/p on

mode -2
a
pin of port C

B mode set )
put Part B Pco PG Pcz Pc ] the PCs PCGPC> Porta control word
1

maybe
mode mode
-
°
- '
II ↑ ↓ ¥% / a¥a / ( bi-directional
✓ bus ) " "° % " " %
IF "
•
✓ 3
INTRA
~ control Iisfa OFF
PA
-
Pao

f/
PB > PBO - >

Group B
Group A
21401 " 8255 PPI
portccwwer )

""
→ "

I = IIP
0 = ◦ If
Moy
:
.
.

port B
B in mode ° Port A
A
port
-

Both port {
.

Iip
→ IIP → , =

I =

◦ =
OIP
used

g
port
-

8- bit OIP
Port c. can be as . ◦ =

mode
mode selection
selection
mode set →
( or ) mode 0
4- bit ports mode
2 ◦ ◦ ° ◦ =
→
.

flag
=
active
◦ I model 1 = model
/P I
= =
↳
+ bit i '
I ✗ = mode 2
mode set

4bilP
I
(b) MSB
-

MSB ° -
bit set / rest
(b)
Bit set / reset control word for the above configuration
of go µ
-
=

of pins port C
, ☐ ☐ ◦ ☐ ◦
◦ ◦

Say ,

mode -1

M Ilp in
:
10 , , oooo = Both -
port A

B in mode l port B OIP mode -0

port
-

Both port A q in

functions as handshake lines port C

Otp
Porte

lines say
Handshake
,

mode -
1
in mode -0
10001110 = SEH
-
port A Otp
port
-
B Pco , PG , PCL INTR port B IIP in mode -
l
pc, -

strobe
A Ptt port
-

C upper Ilp
port Pc , peg qpc ,
as
-

]
,

Cilp ) Pc , IRF
( PG)
-

C
Port bit 3 as 0
/P
A Pez Fcb 9 PC > PCG Ack
port
-
-

§
,

(◦ ip) pe , ◦ ☐f
address
.

→ Say 70 -

port A
A2 ' A ' Y 8086 always connected
is
72 -
port to A , ,Ao Of 8255

nay , ,
,
,
, ,,
,
,
,
p, ,, ,

peg ,
Pci be
used •
76 -
control word register
can
him Ciws
as I 10 IN
code : MOV AL ,
SOH

OUT 7611 ,
AL
 A address
and INTRA is sent
port 010011 when both IBFA { INTEA becomes 1
Pc] becomes 1 .

→
say 711 0111 so
-

1 routine data is read

port interrupt and the
◦
73 ☐ to service
Now
processor goes
-

I 0
75 _
port C
I 1
But How to make
pcq as 1 ?
77 -
CWD

- in bit set /reset mode you can activate Pcq .

→ it 16 bit port address is given

A
Civil : 10110000 ( cot port ☐ can be
anything ]
Say 074011
-
port

B MOV AL BOH
0742
-
,

OUT 76th AL
0744 -
c ,

activate PC for INTEA ( 00001001 )

MOV AL , 09 14 11 to #
0746 - CWD

OUT 76 Al AL
,
-

MOV DX 0746M again : JMP again

,

HLT
latched is
MOV AL ,
SEH If NMI is there instead of INTRA ;
when data is G INTEA

OUT DX AL
,
activated , type -2
interrupt is done .

MOV DX 0740 H

[§
,

;É¥
COZ 55M 01010101
og
-

◦ ◦
MOV AL , 55th 11 or AAH
AAH -
10101010

÷
a- ☐× .
"
◦ ◦
◦ A
.
HLT

for alternate
blinking of LEDs

:
1200
IN AL, > OH
28110122 Bit set / reset )
control word ( Port C
Mov [ 050014] ,
AL

IRET

D> Pi Do
☐6 ☐
5 Dg Dz Dz
poling technique
:-
→ wring
/ I 1 >
Bit set / reset
✗ × I -_ set it is I
✗
check IBFA whether ◦ or -

◦ = reset
-

don't care If
'
1
'
read the data
Bit select for
-

port C

- O 0 I O O O O -
WH

"^
" "
°
° PG , PIG Pcs Peg ,
,
,
PC] . Pez , Pco

B¥
00001017
> 0 1 0 I 0 I 0 1 contents
IN AL > AH I / reading port c
again
:
= OBH ,

> O O I I 0 0 I '
Bi not
is 1
WH
Il check whether peg or

AND AL ,
,

>
O O O O I I 1 I Bz if I
IBF a
= 0 2-f =

JZ again
Bit set I/ code until becomes
/ repeats the IBF I
reset
flag
D= active IN AL , 70M

A
I → 7° -
Port MOV
@ 50011] AL
to set PCs to ,

72 -
port ☐

74 -
purtc mode
post AA / P port ; I
-

→ 0

76 -
cur

( connected
MOV AL , 80 to
PA > Pao
external device
]
-

I/ port olp port

making
c
OUT 76 ,
AL

°ÑA
}
MOV AL OBH "" ←
pq→;ÉÉÉÉi 1-
,
handshake
/ p signals
°
-

76 AL
↓ 1-
OUT ,
PEG →
AIKA

put mode -0 initialize it as

OIP port
'

to
→
Say port A IIP ; set pc , to 1

port ☐ Otp port ; mode -0

↳ PC} →
INTRA
JR- 0
port C lower IIP
PC 6,7
#>
CWR : I 0010001 =
91M I
/o

MOV AL 91M
from
,

sent to 8086
Al
OPTFA = 0 when data is 82-55 .

OUT 76th
( Porta )
,

W : 00001101 MOV AL ,
ODH
then it sends
OUT 7614 , AL
an
AIKA = 0

Now
INTEA is made 1 I → service routine
→ port A Ilp port ;
mode - 1
INTRA -_ .

I 07
Carr
:
0 0000 PCG -

0000 1101

switches
etc ;)
( ADC
PA > -
Pao ⇐ MOV AL , AOH

OUT 76th
when WMI is
given
,
AL

pcq ← StBa
pµ→:ÉÉÉ-
MOV AL, ODH 01200 i MOV Ali AA

OUT 70M AL
pc , → IBFA becomes 1 after data is latched out 76th AL ,

:{ _!
IBF ,

v
±"" "
MOV AL FOH
Inter
- internal signal -

interrupt ,

↳
OUT > OH AL
snftwaeehy
, ◦ ◦
enable is ◦ A

↳→
'
'
INTRA enable again
: JMP again
pig _

( internally connected Pcq) HLT

#
to
PC 6,7

I/o when software activates it

INT EA __
I
 r

→ seven
segment display interface :
,¥%
-

poling technique :
common
anode
¥
"
7411
ITTTTTTTI
_mnn_#
IN AL ,

AND AL H Az→A / PA ,
,

AM to PAs _ run
.
a

JNZ again
town win PAT
¢↳zqq_mm#{ b

_nn##-
→
> <
MOV AL AA PA ]
, ITRD →
RI
buffers d

nmmⁿʰ§
reset → reset Paz
OUT 70 AL

MGR
,

PA ,
-

Pao g
311101W → port A mode -2
operation -
☐◦ ≥
. % -

pa, .

¥
IIP OIP t
cathode

B)
common

1¥ EI EI EI EI
"↳ ≤ "
" " "° '
" TRB
-
NPN
→ a i%-m---

wnf→É
PG -
IBFB PG -

Otfp , a

PB ,

MY !
} {
-

t
Ebro & { {
" "↳
ATKB
-

' 2

_-
-

→
Intra ""

,_→→§§
e

•
h
PB The d
Internal signal IPCI DBFI }

-1
>

¥21
_

'

Interrupt enable
← at,<
a
pique
[ INTE )
¥ÑIÉI

IN
TEA -

Peg pAjPA◦#
INTEB FR PA PA PA PA , PA PAO
-

Por
WI - Displays , ,
PA
, PA¢ , ,

M PI←ÉBa
'
-

Ñp±→±ppa f
b d
IT → H a c e g
IIP
I
TIE? I 1 I O O I I 1 CFH
INTE
,a
-

PG 92M
2 I ° 0 I 0 0 I 0

INTE
,z
-
Pcz
3 I ° O 0
O O I I
86th

¥ 4 1 ' O o I I 0 0
CCH

5 I 0 °
I 0 I ° ° AAH
I
6

{ All Ao _M-Ér
/
-

gosh
A- A
pay
7
'
/ I 1 i µ f f ,
pas -mn
'

◦ I PAs -mn_.
Pay _mmiy display
SHL to select particular seven
segment
PA ] _m_ix
-

8256 Paz -M-B ? ✗ LAT ?

pa _mn_ixÉ
- Do
in ,

Dido Rao
_nn-DÉ÷
÷:
PBS
# t
_

PI ÑD PB #
°_ -
- ◦

,
5r→wÑ PB , → =L
PBL

reset → Reset PB
, -É=
PBO I s

Sw , -
{ 10k
→
↓tVcc
co-ordination and
flenibitity in mode
operations
-

advantage of 8255 .

esau )
mode Porta
}
0
port A OIP →
304
ˢ% B
Ilp mode
-
, 32h port
port ☐ then

34M poitc
36th UR

cut :
10000010 = 8211

code : AL 8211
} / configuration J
MOV
pom
,
,
OUT 3614,7L

" tone the switch patterns

}
IN AL ,
3211
-

OUT 30h ,
AL
(say Sws Sw
>
.
. . _
swo = FOH ) '

2-
-

D-
At
✓

:
MOV BX 0500M 4-BE
,
×
5 -171
-

MOV [ BX) AL
, !
✗
8-1>-1 -

HLT
I­
 011111 " ADC 0808/0809 Interfacing soc - start Jlonversion poling technique → IN AL , 5411
is not
of lonvertion 11 to check MSB 1
soc
CLK Eoc end AND AL got
or .

1 ↓
-

~
→ Eoc Jt
Control q
/ Pio →

→-
I
+
→ be wired
±"? → 8 channel) or RCL ,
ROL can
↓ ""

[
" £ ᵗʰ
"""" &
7- " ° " "
""
" "% "
Mr &
"
""
" - " °

"
%
Successive "" "" * °
" "
bit it
"
* ↳ = " " ☐ = "
switches """ "" • buffer
±, "p→ register ( Otp latch)
Otp

# ;
fifty → er ror is ten

}
D- Jv
analog
-

o
LSB
-
A

}
address if
latch ✓ ↑ 2. sv -
TF n en : FOH is
given some error

B IP ( OE )
address
◦
3 FM
-

and switch 1.25 ✓

-

" enable
lines
_
caewd tree
◦ on
◦ ✓
,

↑
25612
register
Address ilp select → matrix display
channel
§
ladder
8×8 LEDs
column
ports for
wire { wise activation
diff now
-
-

°" 'É
"
( port A) ( port B)
0 Ilp ,
Vre Vre
PBO PB >
PB , - - -

€
. . - - -

O O I I /P ,
5N 20 -

port f)

9
: : : matrix
B
i ;
i § display
22 -

f 2] c

9¥
:
-
i.
.
PAT
-
cwr
zq
1 IIP
I I
p > .

AL SOM
MOV ,

ME
AL
OUT 26h ,
.

set PAO
for every is AL ,ffH

ifI
successive ref
edge approx mov
-

tire

by the time of falling edge it starts conversion

of proud
'

out zone
AL

¥
,
"

soc -

pulse signal mov Ahrfn

:/
resolution Ab
data is the 9 lost 2211
.J bits Out
in more ,
the
.

more
,
no

need be checked conversion delay ( 100M$ ) :

§
to
Alison
-

parameters mov

ᵈ°ᵈʰfFʰÑ ( 64° " %) / ◦ "T 2° " A" " ↳ '*

I/
'

now LEDs

/-q↑¥↑¥
MOV Aliff "
pao our
will glow
OUT 2211 AL
,
[ 28
IIP I
JIIPZ
3

[ 2 27 ] IIP ,
I/
Py

f-
[ 3 26 ] IIPO for 1st column should 810W
shape
-

IIP
provide a
delay
shouldg.co#
,

25 ] ADDA 8ᵗʰ row

IIPG [ 4 G
20 ]
5 ADDB
IIP> [
→ ]
soc [ 6 ADDC
* use lookup table for smooth sinusoidal signal in DAC
2h ] ALE
[7
analog signal
Eoc DAC
change freg of
in
◦
Ip
peak change delay to
M ] value
03 CS reduce or
On MSB
W ]
OE [ 9 06
[ 10 19 ] 05
IK

Vcc [ 11 18 ] 0¢
1+1
[ 12 17 3 00 LSB
Vret
'b ] D
Vrefl
-

GND C 13

C '
4 15 ]
O 0
, ,

e) c- 7
port A -
IIP

{
✓ Vret
CJ Vcc ref B- ◦ IP
port
/ / 1-1
, ,

I m.de lower
- ◦ IP
◦ -0 port c
"
upper
-

IIP
" port c.

" { EOC
•" ' ◦ ◦ " °o°
→ a. cw
> soc ADC I
/ P, ← Analog i / p :

→ Ao
0809
→ Reset pro
=
9811

-1
RTs -0 RI
and
Jp → WÑ PBL
A B 1-
}
C

,
selected B
1st channel is port
,

/
AL 00
AH 03M M ◦✓

/
MOV AL 98th m°V ,

⑨ "T 52h AL OUT 34th AL

OUT -56 µ µ, ,
,

MOV AL , 01M

OUT
544 , AL
CALL
delay
MOV AL , ◦§µ-
OUT 54th AL
,
?⃝
?⃝
 't "
0211 8254 Software Programmable Times / counter sc , sco Rw , Rwo

0 counter
0 -0
0 0 counter latch command
-
0 I counter -
I

counter
← CLKO
I
0 I read / write LSB only
← GATE 0 0 counter -2
Data
0
bus # ← OUT °
1 i read back command I 0 read / write MSB only
a
☐ 7- Do buffer LSB first then MSB
I 1 read / write ,

← CLKI
counter
RI
← GATE '
bit data 1 mode
RW , ; Rwo
◦ =
load use 1
.

To 16 __
-

/ I
-

read
a

← OUT
ER- 0 I
write logic

⇐%
Az→ A

t
,
← Uk BCD Mz M MO
A → 2 Max ,
, Ao
← c. ATEZ
2 0 Binary counter FFFFM interrupt on
terminal
← OUT ◦ ◦ ◦ mode 0 -

count
2 .

^
is -10 1 BCD counter 9999
◦ ◦ 1 mode , _
hardware • ne -
shot

control
word _ ✗ I 0 mode 2-
pulse generator
register
✗ mode 3-
square
wave
generator
-
I ° ° mode 4- software triggered strobe

strobe
I 0 1 mode 5- hardware triggered

crystal oscillator can

provide stable clock pulse

}
counter -0

frequency
✗
-

high mode 3
cw : 00 I 10 1 11 = 3711
→

It'd be difficult for applications like interrupts which has low freq ( KHJ)
-
( 1000710
load 16-bit
count

data
for
we
go 8254 programmable timers
-

has
counter -0 20h
say MOV AL 37M
to → ,

predecessor mode of operations I 2m

-

various OUT 2611 AL

,

division
frequency 27M
.

get
-2
to MOV AL OOH

} for
,
" LSB
CWR 26th out ↳µ a,
8253 times ,

}
MOV AL IOH
,
It for MSB
82533
I 8254 out 2. µ , a,

3- 16 bit counters _

} I
Counter - I
2. 6MH3
upto → cw : 0 I 1 1 00 00 =
7011
mode -0
- maxi
/ PIK 8MHz
y, , , µ gun ,

read back feautre

✗ bit data
)
16 -

MOV AL > OH
read current count ,

(feasibility to
OUT 2611 ,
AL

MOV AL 70th
,

OUT 22 H AL
,

MOV AL ,
OFFH I / start always with
integer only
OUT 22ft ,
AL

selected
* Based on
address lines
, particular counters are .

be obtained
clock also
As we have independent { gate /
i ps
,
the 01ps can

independently .

Ai Ao Select

mode low or
Rising High
low
0 0 counter O
going
-

1 counter -
I
◦
◦
disables _
enables

counting
I 0
counter -2
counting
control word 1) initiates
1
I , writing
register _
_

2) Resets OIP
after next
clock

ilp in counters ? → to enable the

counting process .

why gate 1) disables

0 counter is disabled .
2
counting initiates enables
when
gate
-

2) sets olp counting counting

to
gate
as i
/P '

level triggered or
pulse immediately
high
↳
depends on the operation .

3 11 11
' '

can't be loaded
of 16 bit time 16 bits
-

at
though counters are ,
a

disables enables
from data bus ¢ _

counting
.

counting
5 -
initiates

54 Sco RW , Rwo Mu Mi Mo BCD counting

Sc -
select counter
031'" " software ( infinite loop) to come out
of it

hanging
when occurs ; so as

terminal count :
interrupt
-

mode on
used
watchdog
→ -0
timers can be .

' ( LSB 2) __

? %?
in
-Et generator generator
-
rate :
interrupt
-

or
- - - - - - - -
- - - -

:
-

-
→ mode -2 Timed
I 1 I

- - - i - - - - - - -
1- - - i - - - - - - - - - . . _ .
- -
' 4
;LSB=4
-

1-
.

CW
.
. -
=
.

i i i ' '

Jr - - - -
-
- -
:
- - -
- - - - - - - - -

l i
-
-

I
' '
"

;
'

÷
' i. - - -
- - - - - - - -

÷
- - -
. -
=
* :-.

'
l ,
y ;
-
-

y
- - - - - -
-

i
i -1-1-1-1
-

I 1
, i e I I

i
1
,

ji
a:X
i
. . - - -

- - -
- - - - - - - - - -
- - - -
- -

,
-

. .

I
y
-

i
-
-
y
- - - - - -

◦*,
_

'
i l " '
l
f5V
, ,

I
f ; ! f- i
,

I
- -

¥
-

i If a-gate
-

'
- - - -
-

; crate l
-

÷ i
- - - - - - - -
- - - -
-

wish
- - -
- - - - -
. . . _ -
- . . . _ . _

,
.

" '
i
1
I '

i|ʳ
1

IT
I
1 " "" " ^ °"
,
"
°
i
. I i ,
i
'
I i connives .

.
- -
t - -

so after I 3 I
1 1 2 2
,
i
,
1 I
I 3 ,
, ,

/ "
°
° i l '
I fit
I '
l i I 1

ii!÷.,,iz:##
" wads
!
,
'
" '
l '
I : : I i ! i 1
;) ,
,
e
reek
I i i : : i i : : i '
.
i i
i
i i !
'

i i : :
i ! iii. :
I
1

after clock
pulse clock pulse at the ◦
Ip for N clock pulses → divide
by N counter
loaded starts ist * one
every
once the count is ,
counting *

required get output high

.

to
@+ 1) clock pulses
are
5) before ( LSB ) is
given (say
the 1st count :]
If another count is ↳ D=
[ n' count )
being
the .

completed ,
the times completes the 1st count {
only then it starts
counting
counting won't stop immediately
.

becomes Zero the

when
gate ,
5141712, I '

↳ It stops
after a clock
pulse .

loaded count
En
Say 1kHz clock pulse { 100
: a .

Out I → only ↳ B. =
4
10,0¥ =
long → frequency of ◦
Ip signal .

OUT 2
→ only LSB =3

Out 3 → LSB = 3 first ,

then UB = L
9111122
◦

shot wave mode

retriggerable →
.

one : mode -3 square

-

→ mode -1 Hardware

for to happen cw=16 LSB 4

counting
:
done
.

is
Previously
-

level triggering
- -
- - -
- - -
- - -
- - - - -
- -
- - - - -

sufficient for wir

there pulse triggering is of gate - -
- -

"
"

"

"Y
"
"→

t.EE#:.M.-w-ir.--.-Yi?. i----i.?B---?:------.y-y------
.

en

UK
-
-
t -
÷ . . . _
¥ -

,
-
-

'
!
" ' :
-
:
- - -
- - - - - - - - -

a.*
+

; I ,
!
y
l

.IE/-!..---i--.-.--------;----
1-
l
I
Yi
' ' ' - - - -
- - - -

i
- -
- - -

+
-

or
- - -
- -
- -
.

i
'

! I
- - - - - - - - -

I
_

I
. . .
i

!
, ,

µ
, '
± .-
" i - -
.
. -

a-
- -
- - - -
= → - -

I 2
- -

4
-

1 I 2
"
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;
,
.

I i
'

i i
'
i :
; ; !
frequency J ↳Pᵈ° "

}
clock
freq
=
wave
wave
* 2.66mHz
→ 1kHz square
square count

process again 9
again provide retiring
continue the
counting → count
,
to =
2660

at count =L
everytime
in the above case .

= count (odd number )

waveform will be
But
during power failures , retriggering can't be done continuously -
_ ◦
Ip
high for one more
clock cycle
En clock cycle
Say 50µg >
: 20ms

high N¥
it
Every 20ms ,
you
have to
retigger -
◦
IP -

* even count wad → 50% duty Yue

high)
*
when there's no count reaches to zero ( output
power
N
.

olp
,
low -

and parameters
↳ Now
interrupt occurs all the

I
toned .

INTRNMI-subroutine and does

goes
to
necessary
operations
parameters
.

to store the
→ mode -4 Software triggered strobe : -

,iN22 8251
programmable communication interface

on -18
_ ( USA RT )
-

- -
-

F-
- - -
-

wñ
.

- - - - - - -

i
.

g-
- -

y
-

y
- - - -
-
-
- -
- -
- - -

,
-

transmit
/ ^
.it#..7.-i.F.H-.Ft-.F--f..H---,--i-...y---
1 ' '
1 butter → 1-
a" ,
1 ✗ ☐
,
'
I Data

! ! / 1 -

joie
1
I ,
l g-
Do bus

◦
v.
i
-

l
- -
l - - . - -

l - - -

butter ↑↓
i
IT t t TMM
→
I l

É!;!
-
transmit
◦
- -
- - - ' - -

y,
-

reset control
1
. I UK
→
→ need /
→
Tummy
'
I
-1 l l cus → write ←
TI
-3-1--2-1 i rñ
-

control
-

t
- - - - - -

i -2-1
-

-0
; ; ;
- .
- -
-
- - -
- -

:ii¥F-
Jr logic
-0

I /
Is - 1 ° Receive

buffer ← R✗☐
'
l I #
DTR ◦
(S P)

f- -3-1--2--4
-
-

I
l 1- modem
f- ntnr
' - - - -0
- - - - - -
- - -
-

; control
-1
- -

y
- - -
-

y
-
-

°
-
-

y
-

'
3 12
I
1 /
/ / ,
its _

RTs -0

receive
→
RXRNY
control ←
Rye

-
for low
going
strobe puke .

f w SYNDET

offers Ntl clock cycles .

internal
data bus
CIÑ
signal
→
is A
high gate given ,
.

continuous
low strobe control signal A2
-
101000190
loaded delay
the
going clip pin I →
-

be {
through software ,
count can
signal .

◦ → data signal -

10100019°

Q) after
Interrupt processor 10ms
;
Ik = 1.5mm Hr
control format
OUT A2 , AL
llsending the

10-6 AO AL 11 data
TE
75
= 6-67×10-17 Out >
transmitting
AO 11 serial data
IN AL
, receiving
1° ✗ 10-3 IN AL , A2 11 status information is received .

= 15000 → Nt /

-6.6%-7
count ,
N = 14999 Band mate → bits / see
=3 -197 H

Asynchronous serial
communication : -

transmitter
Cw
:
00110000 =
3014 us ART
- universal sync asyn
received

* → mode instruction format :-

* for 100ms → Ntl = 150000

factor
Dy Dg Dg Dg Dz Dz Di Du Baud rate
N =
149999
° I 0 I
→

/
EP
=
249 Ef H Sz S
,
PEN Lz Li B2 B ,

→ O O I I
a-
count #/ Sync -1 166%641
can't load this .
.

model
. .

instead , we can reduce clock frog using square

wave
→
0 I 0 1

mode
-

which
-

reduces the count .

° I 1
°
→

BE
-

So make Hardware connection from , Fits fits Fit

IPJ to i
/p of IK
J counter I
-

◦ counter -0

enable
→ parity 0 disable
1 = enable ,
=

"" ""

]
th
UKO -
→ even parity
mode -3 I =
Even ☐ = odd
0 +5W ,

gate
-

{
8254 out 0
I 1-51<1^7
•µ ,
↳ o o I I
→ no -1 stop bits

gatel tsv

}
-0

mode -0 invalid ¥ {¥
'

out
' - looms zit

transfer zokisand
for high speed data
.
_

0 sync comm -

counter
20M →
counter
I ↳ needs a clock
signal
MOV AL 37 22h →
expensive compared
,
↳ to
~
async
.

OUT 26 AL → counter
, 24
- WR
A- 400 zu
MOV
Band rate 16%

}
En :

count-OUT
20cal counter -1 format ?
for mode instruction
14g char size gbits what Is the
MOV AL 10
odd
parity
,

OUT 2° AL 0149 -
BCD
I
stop bit
, :

movn 7114 = cw

Ali @9)

{
Mov

/
☐ CD
AIS : -

01-01 1-110
= 5 EH
OUT 22h AL
9. ?
,

moral .

as
OUT 2111 AL
,
 → command instruction format : -

AL , 28th

} 11
* Mov

AL
sending data

format Out Ao
mode
setting
or ,
whether it is
*
How 8251
recognizes
Command format
setting ? IN AL , A2

§
will be
again :

Ang . After system reset ,

the first instruction passed AND
Ahoy 11 transmit data or AND Ali 01

considered
considered as mode format and the next one
as Jt again

,µ
Command format .

}
MOV AL , fs
for
OUT AO AL
loop sending
DI Dr 173
,
Di hundreds date
of
DG Dot Dz Do .

INC SI
F- H IR RTS ER SBRK RXEN DTR TXEN
data terminal

/
I
a ready '

forces to'0 IN AL AO
1 =
DTR Otp ,

receive enable MOV BX 10010M

→
I = enable Rxnpy ,

0 = disable it

↳ send meee was

◦ = normal operation
ems
reset
FE ) IN AL A2

}
( PE E again :

→ 1 reset all error flags '

◦ ' ,

data
=

11 receive
.

to send AND Ali 02

request
' '

→ Otp to o
I = force RTT
Tt
again
internal reset
→ returns 8251
I
format
=

to mode instruction
8251

→
enter hunt mode

" "" " " " "

ᵈᵈ
RJ
T*c←y
Rxc ←
- Band clock
IoT →
/ ZV

IoT -0 WRT
got
An -
CIÑ Tx☐s•→ 1- xD

2g 11
A44°H software reset
-

MOV

OUT A2 ,
AL
tear
for hardware revet → do
system reset manually Axis
1- R× ,

-
bizv
→ I
¥m
reset ,
?
]
Reset
to transmit
serially →

to receive
serially →

0011 0111 →
wring control signals

data transfer
faster rate →
parallel
interface
↳
ape →
general purpose

for normal date transfer ,

serial comm is best

* → status register
CFE )
D> Do Dr Dq ☐3 DL ☐I Do
framing
error

override error CDE )

DSR SYNDET FE OE PE TXEN R .

TXRDY parity
er ror CPE )
YRDY

} /Hardware
MOV AL , JEM
reset
out n-u.ae

} 11
Mov All 40h
software reset
OUT Ah ,
AL

move It when control signals

}
. 's " are

OUT A2 AL not used

,
?⃝
• 51111W microcontroller → CISC { RISC processors
t -7
microcontroller
80-51
reduced instruction
complex instruction
↳
single chip Ic suited for automation .

Pony
,
Get
set
computers
computers
machine control applications -
-

contains hardware -
hardware for only
for everything few operations
embedded in
single chip
-
acts as a min
computer . .

Everything
At)DÑ☐
Gimpy ) say
has
only
specific
on :
-

Application Er : say has all haeduuaee

"
ADD , SUB 'M°

."""
1)I V
1=10 s
-

takes up more
memory
CPU IRANI
/Rom1EpRom
EEPR0M_
parallel fog gofteuaee program
£"

timing Coz
repeated
"
place
"

¥
a ← En : add or sub takes .

{ R/ egister serial →

control → Harvard architecture

{ Von Neumann : -

unit t
additional device DAC
operation evident
.

→
faster in data
png*am9are
oscillator

,£- indep
or

act specific functional pwm ← as

blocks
Otp
CPU CPU

F
a

timers countess / interrupt 2

I ↓
logic
program
↑ ↓ ↑↓ date
memory memory memory

ehdog ) are required to come out

of software
8051 PIC → Harvard architecture . .

hangs
,

for pukes for machines 8086

switches
controlling pwm → von Neumann
Gate
_

width
( pulse
modulation )
gosimicwcontnll
* functional blocks on a
single IC

→ 8- bit microcontroller

control board
↳ reduced
size of
of preferred
.

a
bits in microprocessors .

Usually no are
m o re
-

↳ low consumption
power
preferred
.

Er :
Say 64-bit is most today .

↳ faster in
operation
↳ ease
of integration .

But in microcontroller ,
how no

-2 bits are
preferred .

ts high reliability
-
for cost effective usage .

↳ cost
of automation ↓

→ 5- type

temp
module -
thermocouple → K -

type
→
12MHz freq
ROM / EPROM / EEPROM

_→ ñ"Ist
Lrcb
temp

Separate 64 kbyte program memory

FFH does Gq kbyte

data memory .

ADCs also the

average ing
.

Jv -

2. 5V
-
7ft
* MUL DIV instructions available
§
.

◦ v -

OOH

{ microcontrollers
:

b/w microprocessors
-

differences teeth
→ Basic → Hmos technology ,
CHMOS uertiom also available .

Microcontroller 321=10 lines § -

bit ports
Mignon high bit manipulation
.

or

for moving two 32 I 0s /

many opcodes
one or .

external ( Po -
P}
)
data from memory
to Cpu

two
types of bit Manto multiplexed
one or
→ 16 bit address bus to
port 0 { port 2 .

handling
instructions .

concerned with rapid concerned

q date
with
rapid movement of bits
movement
of code
within the
addressed to chip chip .

from emit

read date
read data
perform limited
use :
prime ,

calculations
perform en tensive
calculations .
To control
data
on that .

environment on that
store data in mass calculation .

device
Storage
.
17(1)22 Architecture
of 8051 microcontroller
microprocessors
are
dynamically expandable
but microcontrolless have fixed programs

YourEner
ATMAL series
of microcontrollers.
PC DPTR
I lo E D)
ALLAS semiconductors.

address

I
bit
get
to

Using portos2 together, we can

efo -..........Ad
austries, amorean
I
E

.
CoN
↑

stix-timebutter I Regbark 3 T CON

Regbank 2

RESET-menrest ! Regbank l

I o
Elow

meg S
TLI

amn
bank o
= >

interupts -

sports:--
T HI

F counter-
Internal Betis sais
3

memory
control senaldealt
some
ports
have multifunctionality
↳all have
spine. A spins xpports=32pins->10
lines Cout of 40 pins of soil
external addresses can be accerned.
so that
connected to
port 092

str-special function registers.

Internal RAW
SROM 10 pins
parts with
programmable
timers, counters

serial data communication.

clock ets
upo components: program
counter (PC), Alr,
working registers,
8bit CPU with
AGB register
↳> accumulator

microcontrollers - bitwise control

↳
independent control

16 -
bit
program counter (PC) a data pointer (DPTR)
8-bit status word (PSW)
program

XTALI, XTALL ->

digital pins for clock.

8 -
bit stack pointer (SP)
ROM -> type of rom differs with versions
of skil

↑ Ks

interparvimn oustoneis
I tend dam

-ite

-forthe both bit

abylecdoon
as

same
les

32 110
pins -

4 bit ports (P0.41,

P2, 0s)

times counter: To ETI

2 - 16
bit

SBUF
full duplex serial data receiver/transmitter -

TCOM-timer control
Control register
PLON
-

time mode
TMoD-

E
*

IP
SCON-

&externals internal intempt sources.

Oscillator aak ekts.

 bit addonable
A
88 * 8-bit
subit
site
8-bit 89 shit SC 8-bit 8o 88

MOD CON
T

Iho ·HE THE

TE Sen control
purpose timer
register Timer control
register.
Grea
2D

2
F
bit addvenable
*
of Rom *
8. 8 to
ED
cree
&

If is to E
113

IS math register
17

1) 2

10f
9I
I
scon shut poor sw
08

07
Redbank o serial data
register
OO

8 883 8 82
16-bit
-

SP DPH DPL PC
counter
stack pointer data
pointer program

* * *
so & o* Ao Bo

porto ports portz port s

Port latches
21112
Program
enter (PC):

↑FFFH
FEFFH Patanenorebates)
r instructions are
fetched by
auto
incrementing
PC.

↓program
acto
external doesn't have address (usually any
other
register
program external
our hip external any
can be referred worth

memory
program
its
register).
memory
some
of there locations
R:- data
pointer register.
used for
controlling
#

1000t
of 4)
805 operations of peripherals
(SFRs) DIP
OFFFH
internal 64k Ctimers/counters) ↳ addresses for internal a external code date access.

program <serial ports)

memory
Cinterrupts) ...

Conor
registen:
-

0000t
0000t

alerta crystaelected
·
↑CON, TMOD, IF, IP, SCON, PCON.
EA 0
=

pin -FA=1
extendly status word (PSW): similar to
flag register.
two
-

· scillator at is on-chip
ports for
32 to line
32 11.059 Mnny

decimals mined so that

P
RS, RSoor

FirstE E E E E
Cy AC to
for
-

colculations will be simple

S serial commo

cy-carly
reason
for using specifically 11.059ty
-cuxillary

3
Ac
p5 rather than 11 or 12

MMy or-overflow - math

flag
RST "-pality

Fotwer Progte user fleg

E
isoI nero
·

3
Fo

I
cow

unit:-
Timing
or Fogramming:
-

A
synchronize
with clock pulse 90. P., P2,is ->8-bit ports 132 to lives.

PTEN, RT, NE generated by

signals configured ilp ports
are
control
-

ALE, an
Once the system is RESET, they're
to acces
control unit
timing a
'O"is written-olp
device. when
the off chip
to reconfigure on it, write"? Pass
fit?

Restors.
general purpose
or

working
I
register
Poto pin connected externally
to lok pull up register
stack pointer
=
4 gen purpose

Ygg
banks
32 -> 4 register
each bank I
counter
(Ro-R.)
program

FE
2 - AEB
ofregisters
special
is

-> accumulator
Aneg
CADD,JUB, MUL, DIN, boolen bit manipulation]
d bitwise
operations
a re
predominent
PT
can be in minocontrolles
used for all

data transfer blu sost a external devices.

ineg ->
along with A. MULE DIV * Say you
wa n n a
toggle all bits of port of Back: Mor A, #55H

for on-chip MOU Po, A

a
A
C ALL DELAY
ACALL
type f -
stack from oth location.
two
(within 2K) Mor A. #OAAH
*
pointer starts
memory
sub-routin
instructions
MOU
Po, A
in cAc
AGALL DELAY

&
tCA22
(long call) S TMp Back
for off-ship T
external 12 OM

(within 64K)
 50%-duty cycle

opport
I generate
with

be
Duevote
wave

Pooral: ,
say you
wa n n a
square

HOFE
to addren a date multiplexed line here: SETB P1.2
again: CPL P1.2

MoU Po, A
ACALL DELAY ACALL DELAY

Back: mor A, Po i.e. ADo-ADT

CLR PI.O SIMP again
Mor PI, A
C ALL
A DELAY

S JMp Back
STMP here

duty cycle to 10%

change
the
23(1122 say you wanna

here: SETB P 1.2

not
or do port
ACALL

CALL
&
DELAY

DELAY

internally pull up registers CLR PI.O

doesn't need any extend pull up registers) C ALL

A DELAY

STMP here

r
·

oi port
madef
Porredress line can
DELAY sub-routine
+ cx
syn
f

*
↑OU 124, #OFFH

Icuto decrement
used.
pull up registers
be
again: JNER4, again
internally
RET
to read opk address,
say
porto sport
I can
work together.
bit instructions
->
single
used address
part is
being
when as
the

it can't be used as SETB bit

or date bus,
Cut bit
for that moment
to ports CPL bit

JB bit, target

POTCorientent from 0 port,it has some alternate functions

JWi

JBC
bit,

bit,
target
target

I
Pz. O RxD Consider Oven
application,
&serial communication
on

when is increased
be switched on temp
Pz ( Tx1
say a buzzer has to

RostEEOGoutocideforexteer runter
to some value.
interrupts

I
soil a Butter

sootton
I
out
an

ec.S wRG orvidemesteal memory

wishfor pulse

used
only
to lines if 425 goes high
F405
on
are
In 8751,8951 -

JND 425, here

here:
back: kou P1, #ciH low pulse
I giving high
to
& ETB P.. 3

ACALL DECAY
CLR P1. 3
Mor PI, FOAAH s TMP here

ACALL DELAY

SJMP Back say you wanna display status of the switch on LED

switch-p..4-ilp port
reset
Ports status upon
Pop port
LED is

have value -
Eff
all
ports

S ETB P1. 4
programming
10
* Bit manipulation bit
flag it is
only
Astoring
in as
mor 6,41.4 Caney
accell-
-

single bit MOU P2.5, C

acces-
8-bit
-
port simp
again
otoldin also

SETB** programmed programming

& ET B ↑
can
*
be
through a

(set bit)
post no
0, 1, 2, 3)
say you
venna toggle all bits of is continuously

Sn: SETB Po.I

#include 1.h>
CLR P1.2
(regs
void main (void)
toggle bit P1.4 continuously 9
say you wa n n a

for (i,i)

P..4 CPLP.4
30
SETB
again: again:
=0x55; in Lex
CALL
A DELAY
CALL DELAT
&
Ildeta
P
CLP P.. 4 1 =
0XAA;
s jmp
again
ACALL DELAY 3
sTMp
again 3
 say you wanna activate a
particular bit, To enable or disable the counter we use GATE signal
means.
signed
have
This LATE be both software or
can
given by
#include <regs1.h>
shit - > poutibit4, "O GATE 02
=

void main (void)

sware
-> TR pins (timer start pins) triggering
9
o
unsigned intz; Ro - timer
↑

TR1 timer I

1)
-

for (t=0; t c =
100; t+

counting process
90,00
the
SETD TRO I timer starts

=
0; port(bit=0; CLR TRO II to
stop counting
port(bit= 19

-4,0
1,
=

likewise SETT TRI

CLR TRO

3
derived from enternal sources.

easing refile machine code

when CATE 1 -
counting is

file
(hardware)
->
a
program tcount external events, set GATE=1

file.
file lengthy compared assembly
is
to
but a

control
icon-> timer
register
- > 8051 timew Bit Symbol
- 16 bit
TUN.7 TFI -
times I overflow flag
2 time I counter
events CON. G control bit
happening TR1 run
↑

I
to count times
delay; counter-
-

time
timer - to generate overflow flog
↑CoN.5
timeno

TFo-timero
outside microcentroller
-

soil controller can

load 16 bits?
run control they
How sbit

timews To not
of 0000+
it to
Ans: use one the
times, set
using
THO T10
3 timer -
O
20 00010000 I only timer i s used in orbit times mode.

TH1
+113 times -
1

->
through TROSTR1 times can be started or
stopped by instructions

2 pizz
timer
counts to max value -> sets
flag TFORTF
Timer - a
register
+
->
CON

Mor TCO. #4FH

11 #refer to data

F1 TRI TFO TRO IE ITI ERO ITO

R2,
↑

mov THO

mode
Tmop
register-timer power
4-bit -

interrupt function
-> 8-bit
which sets the mode
of times registers
register operation
upper 4-bit-timer

GATE CIT M, MO CAPE CI M, Mo

->
Mode 1
programming:

-- (can bed from 00001 to FFFFH) -> TL TH

sost-up
*
punter

( timer
-
O
timer -

5351-down counter

tmoD
Both time- stimento
model can
be set
simultaneously using once an initial value is beded in to or TH
↑HO TH 1

SETBTRO II for timer - O

M. MO
II for timer-1
eased
SETD TRI
O · mode-o 13-bit times mode
modela
mode
O I mode-l 16-bit times
Say you gave
an
initial count Effort - now it starts counting
I 0 mode-28-bit autoreload & once it reaches frrFH,
00001
it was over from firFH to

will be set high

CT ->cockI timer
Timer
=>

flag
delay generator /event
counter
CLR+nO 11 to stop timer after TF = 1

reset to 0.
delay generator.
is
time reload thatL 9+F
cli used as timer
repeat
the prown,
-

= 0 -> ↓

clock for time delay is the

crystal frequency of sor

sFiro-Fic-ITovertion
source

connected in
Can crystal is

↓ XTALI, XTAL2)
↓
flogo

frequency of times
P1.4 to square
wave with 50% duty
cycle; timer
-
o
f

crystal free of sost

th frequency of
·

mode-1
an: rs-Ffff
11 time O
MortMoD, #olt
-

count ->12
19-924B KMy
=

HOF3H
here: mor
TLO,
Delay:
az outera 21.6KMy
SETB TRO &
MOUTHO, #OFEH
again: JNB TFO, again b
CPL
P1.4 22R + RO 1.085 MS
ACALL
Delay CLR TFO
Ms
5 JMP here RET 13x1.085
time
delay
=
:
: