Electrical Engineering

https://doi.org/10.1007/s00202-019-00901-x

ORIGINAL PAPER

Interleaved quadratic boost DC–DC converter with high voltage gain

capability
Vijay Joseph Samuel1 · Gna Keerthi1 · Prabhakar Mahalingam1 

Received: 8 April 2019 / Accepted: 9 December 2019

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Abstract
In this paper, a novel high-gain DC–DC converter which is suitable for integrating low-voltage renewable energy source
with a common DC bus is presented. The proposed converter is synthesised from a quadratic boost converter (QBC). Two
QBC structures are interleaved to reduce the current ripple at the input port (12.9% of input current). The voltage conver-
sion ratio of the proposed interleaved quadratic boost converter (IQBC) is extended by using the voltage lift technique. The
energy storage inductors are judiciously coupled to realise a compact IQBC. Experimental results obtained from a 24 to
380 V, 100 W prototype converter validate the novel gain extension method and proposed design concepts. Under full-load
condition, the practical efficiency value of the proposed converter is 92.49%. By implementing a simple closed loop, the
output voltage of the proposed converter is regulated and maintained constant at 380 V when the input voltage and load
current change. Under practical conditions, the percentage voltage regulation and the time response characteristics of the
proposed IQBC are extremely satisfactory.

Keywords  DC–DC power converters · Power conversion · Power electronics · Quadratic boost converter · Voltage lift
technique

1 Introduction In non-isolated DC–DC converters, it is customary to

In recent years, distributed energy sources like photovoltaic
(PV) and wind energy systems have been making a tremen-
dous impact by (1) fulfilling the ever-increasing electrical
energy demand and (2) meeting the stringent environmental
pollution norms [1, 2]. Generally, the PV panel yields low
voltage (in the range of 12 to 60 V) at its output. Due to the
well-known drawbacks of series-connected PV configura-
tions, a high-gain DC–DC converter is the best solution to
meet the load voltage requirement [3, 4].
Generally, non-isolated converters are preferred over their
isolated counterparts due to the difficulties associated with
transformer core saturation and leakage inductance [5]. For
high-voltage-gain (> 10) applications, conventional boost
converter (CBC) and interleaved boost converter (IBC) suf-
fer from extreme duty ratio operation, high voltage stress on
the switches and diode reverse recovery problems [6].
* Prabhakar Mahalingam
prabhakar.m@vit.ac.in
1
School of Electrical Engineering, Vellore Institute
of Technology, Chennai Campus, Chennai, India
extend the voltage gain by employing any one or more of
the following techniques: introducing gain cells [7], diode-
capacitor multiplier (DCM), voltage multiplier cell (VMC),
switched capacitor (SC) cells and coupled inductors (CIs)
[8, 9]. Though modular multilevel converters (MMCs) pro-
vide a high voltage gain of about 10, they are rarely adopted
due to their higher component count and relatively lower
efficiency [10].
Generally, extending the voltage gain by using DCM cells
and VMC results in additional power loss across the diode-
capacitor pairs [11, 12]. To realise higher voltage conversion
ratios, extending the converters’ voltage gain by adjusting
the turns ratio of CIs is a preferred option [13, 14] com-
pared to the usage of additional components. Various CI
topologies like cascaded CI, stacked CI, multi-winding CI,
integrated CI and interleaved CI boost converters are also
proposed [15]. However, the leakage inductance of the CIs
causes a voltage spike across the switch. In [16], a CI-based
high-gain converter with lossless passive snubber is pro-
posed to reduce the high-voltage spike across the switch.
In [13], multi-winding CI-based flyback converter with
ripple-free input current is proposed; the turns ratio of the

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Vol.:(0123456789)

CI is adjusted to achieve the required high voltage gain. A
three-winding CI-based high-gain converter is proposed in
[17]. Nevertheless, owing to their manufacturing complexi-
ties, multi-winding CI-based converters are seldom used.
Voltage gain is extended by using CI in conjunction with
(1) voltage doubler [18, 19], (2) switched capacitor [20, 21]
and (3) VMC [22–24].
In this paper, to meet the high voltage gain requirement, a
novel converter is synthesised from a basic quadratic boost
converter (QBC). By interleaving two QBC structures and
clamping the voltage level using a voltage lift capacitor,
the proposed converter provides the required voltage gain
of 15.833. The paper is outlined as follows: Sect. 1 intro-
duces various gain extension techniques; Sect. 2 provides
the circuit description of the proposed converter; its operat-
ing principle is elaborated in Sect. 3; the design details are
presented in Sect. 4; experimental results and their infer-
ences are explained in Sect. 5; some salient features of the
proposed converter are compared with some existing state-
of-the-art converters in Sect. 6; and the concluding remarks
are summarised in Sect. 7.
2 Circuit description of the proposed
converter
Figure 1 shows the power circuit diagram of the proposed
converter. In the proposed converter, L1, D1 and D2–S1
combination operate similar to a CBC; L3, D3 and D4–S2
form another CBC structure. Capacitors C1 and C2 act as
the output capacitors of the CBC. They also provide the
stiff DC input which is required for operating the next CBC
stage which is formed by L2–S1 and L4–S2 combinations.
Since the first CBC acts as a source to the second stage,
the structure is commonly known as a quadratic boost con-
verter (QBC). Two such QBCs are interleaved to form the
proposed interleaved quadratic boost converter (IQBC). The
Fig. 1  Power circuit diagram of the proposed IQBC
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Electrical Engineering
voltage obtained from the first QBC structure is connected
to the output port of the second QBC through the voltage
lift capacitor (CLift) and the intermediate diode Dint. The
intermediate diode Dint acts as the boost rectifier diode of
the upper QBC and prevents CLift from discharging its stored
energy during operation under steady-state conditions.
Diode (Do) serves similar to the classical output diode in
all boost derived converter topologies, while capacitor Co is
used to obtain ripple-free voltage at the output.
Inductor pair L1–L2 is wound on the same magnetic core
and forms a coupled inductor (CI). The inductors L3 and
L4 form another CI (similar to the CI formed by coupling
L1–L2). Though two CIs are employed, their main role is
to reduce the size and weight of the converter; they do not
contribute to voltage gain.
3 Operating principle
The operating principle of the proposed converter is
explained using four modes which occur in one complete
switching cycle. Since the converter is synthesized from an
interleaved structure, the switches S1 and S2 operate with
180° phase shift. When the duty ratio (D) is greater than 0.5,
four operating modes occur which are explained below. The
power circuit operation is easily and clearly explained using
the following valid assumptions: (1) all the passive elements
and semiconductor devices are ideal, (2) the converter oper-
ates in continuous conduction mode (CCM) and (3) all the
inductors are initially pre-charged.
3.1 Mode 1: (to–t1)
Mode 1 commences at time t = to, when gate pulses are
applied to S1 and S2. As S1 and S2 are turned ON, current
starts to flow through all the inductors L1–L4, and the induc-
tor current linearly raises and charges the inductors. Result-
antly, the energy stored in the inductors raises. Capacitors
C1 and C2 act as source and aid in charging the inductors L2
and L4. Consequently, the voltage across the inductors L2 and
L4 starts building up towards VC1 and VC2 , respectively. Since
L1 and L2 charge towards Vin through S1 and S2, respectively,
diodes D2 and D4 are forward-biased. Capacitors C1 and C2
are charged to a potential which is the same as that of a CBC.
Therefore, diodes D1 and D3 are reverse-biased. As S2 is ON,
the anode of Dint is clamped to ground potential. Hence, Dint
remains OFF.
The voltage across lift capacitor CLift is held at a constant
value. The potential difference between output capacitor Co
and CLift reverse-biases the output diode Do. The output
capacitor Co supplies the power demanded by the load. The
equations governing Mode 1 are given by
Electrical Engineering

vL1 (t) Mode 3 ends at instant t = t3, when the current through L1
iL1 (t) = t (1) and L2 reaches IL1 ,max and IL2 ,max , respectively.
L1

3.4 Mode 4: (t3–t4)
vL2 (t)
iL2 (t) = t (2)
L2 In Mode 4, switch S1 is turned OFF at time t = t3, while S2
continues to remain in ON state. Inductors L1 and L2 transfer
vL3 (t) their stored energies to C1 and Co, respectively. Hence, diodes
iL3 (t) = t (3) D1 and D2, respectively, remain in forward- and reverse-biased
L3
condition. The voltage induced across L2 gets added to the
potential developed across CLift, forward-biases Do and charges
vL4 (t) Co besides supplying the power demanded at the output. As S2
iL4 (t) = t. (4)
L4 is ON and CLift discharges, Dint remains in OFF state.
The equations governing Mode 4 are given by
At instant t = t1, L3 and L4 are completely charged; the
current through them reaches their respective maximum val- Vin − vC1 (t)
ues, namely IL3,max and IL4,max , thus marking the end of iL1 (t) = t (7)
L1
Mode 1.
vC1 (t) − vCLift (t) − Vo
iL2 (t) = t (8)
3.2 Mode 2: (t1–t2) L2

Mode 2 starts at t1 when S2 is turned OFF for enabling L3 ic1 (t)

and L4 to transfer their stored energy, while S1 continues to
conduct. As S1 is still ON, the current through L1 and L ­2
raises linearly through D2 and S1. Consequently, the energy
stored in L1 also continues to rise and the voltage induced
across L1 increases gradually towards Vin. Similarly, voltage
across L2 increases towards VC1 . The stored energy in L3 for-
ward-biases D3 and charges ­C2. Since S2 is turned OFF, the
stored energy in L4 is transferred to CLift as Dint is forward-
biased. Further, as Dint conducts, the potential developed
across CLift reverse-biases diode D4. As Do is reverse-biased,
the load demand is taken care of by the output capacitor Co.
The equations governing Mode 2 are given by
Vin − vC2 (t)
iL3 (t) = t (5)
L3
vC2 (t) − vCLift (t)
iL4 (t) = t. (6)
L4
Mode 2 ends at time t = t2, when the current through the
inductors L3 and L4 reaches their respective minimum values
IL3 ,min and IL4 ,min.
3.3 Mode 3: (t2–t3)
vC1 (t) = t (9)
C1
ic2 (t)
vC2 (t) = t (10)
C2
icLift (t)
vCLift (t) = t. (11)
CLift
At time t = t4, inductors L1 and L2 are discharged and their
currents reach IL1 ,min and IL2 ,min , respectively.
Mode 4 ends and the next switching cycle commences
when switch S1 is turned ON again to charge the inductors L1
and L2. Figure 2a–c shows the equivalent circuit during Modes
1–4, and the characteristic waveforms are depicted in Fig. 3.
The operating principle of the proposed converter is
explained for a duty ratio of D > 0.5; the two switches S1 and
S2 conduct simultaneously for a short duration. Interestingly, if
the switches are operated at D = 0.5, the operation of switches
would be exactly complementary to each other. Hence, the
complete operation would consist of two modes only—Modes
2 and 4; since the two switches do not conduct simultaneously,
Modes 1 and 3 would not be required.

In order to charge the inductors L3 and L4, switch S2 is turned
ON at time t = t2 and marks the beginning of Mode 3. The
state and behaviour of all the circuit elements are similar to
Mode 1. Hence, the governing equations of Mode 3 are also
similar to that of Mode 1.
4 Steady‑state analysis and design details
In this section, the voltage gain of the proposed converter
and other design equations are derived from basic principles.

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Fig. 2  Equivalent circuit of the proposed converter during a Modes 1

and 3, b Mode 2 and c Mode 4 Fig. 3  Characteristic waveform of the proposed converter

4.1 Voltage conversion ratio vL1 (ON) = Vin (12)

The voltage gain expression for the proposed converter is

obtained from the volt-second balance concept. By applying
vL1 (OFF) = Vin − VC1 . (13)
Kirchhoff’s voltage law (KVL) during Mode 2 and Mode 4,
the voltage induced across the inductor L1 is expressed as

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Electrical Engineering

The voltage induced across the other inductors, namely through D2 and S1. Interestingly, the voltage developed across
L 2, L 3 and L 4, is obtained in a similar manner and is C1 is the same as that of a CBC. Similar justifications are
expressed through (14)–(19): applicable for determining the voltage stress on D3. Therefore,
the voltage stress on D1 and D3 is determined as
vL2 (ON) = VC1 (14)
Vin
VD1 = VD3 = . (23)
(1 − D)
vL2 (OFF) = VC1 + VCLift − V0 (15)
In terms of output voltage, the voltage rating of diodes D1
vL3 (ON) = Vin (16) and D3 is given by
Vo
vL3 (OFF) = Vin − VC2 (17) VD1 = VD3 = (1 − D). (24)
2
The voltage stress on diodes D2 and D4 is obtained when the
vL4 (ON) = VC2 (18) switches S1 and S2 are in OFF state, respectively. The cathode
of D2 is clamped by the voltage developed across the negative
vL4 (OFF) = VC2 − VCLift . (19) plate of CLift, while the anode of D2 experiences the potential
developed across C1. Therefore, the net voltage stress on D2
Applying volt-second balance concept and simplifying, is derived as
the voltage gain of the proposed converter is derived as
1 1 D
V 2 VD2 = V −
2 in
Vin = Vin . (25)
M= o = , (20) (1 − D) (1 − D) (1 − D)2
Vin (1 − D)2
Diode D4 is located at a position which is similar to D2.
where D is the duty ratio of the switch. The voltage gain Hence, its voltage stress is also given by (25). In terms of Vo,
of the proposed IQBC is double that of a QBC due to the the voltage stress on D2 is D4 is expressed as
adopted voltage lift technique; the energy stored in the first
QBC structure is transferred to CLift (unlike in a classical DVo
VD2 = VD4 = . (26)
QBC structure) and results in gain enhancement. 2
Diode Dint is reverse-biased during Modes 1, 3 and 4. Dur-
4.2 Voltage stress across the switch ing Modes 1 and 3, the cathode of Dint experiences a poten-
tial developed across the positive plate of CLift (negative plate
Since the proposed two-phase IQBC is developed from a of CLift is grounded through S1) and the anode is grounded
classical QBC and the switches are located at the output end through S2.
of each QBC structure, the voltage impressed across them During Mode 4, as Do conducts, the potential at the cathode
is obtained as of Dint is equal to the output voltage. S2 is already ON, and the
anode terminal is at ground potential. Hence, the voltage stress
Vin
VS1 = VS2 = . (21) on Dint is expressed as
(1 − D)2
⎧ 1
Vin for Modes 1 and 3
Expressing the voltage stress in terms of output voltage, ⎪ (1 − D)2
we obtain VDint =⎨ (27)
⎪ 2
V for Mode 4
V0 ⎩ (1 − D)2 in
VS1 = VS2 = . (22)
2 The output diode Do remains in the reverse-biased state
during Mode 2. From Fig. 2b, by applying KVL the voltage
stress on Do is determined and given by (28):
4.3 Voltage stress on diodes
1
The voltage rating of the diodes is determined from the reverse
VDo = Vo − VCLift = Vin . (28)
(1 − D)2
voltage impressed across them. When S1 and S2 are ON, diodes
D1 and D3 are, respectively, reverse-biased; the potential dif-
ference across their anode and cathode terminals determines
their voltage rating. The cathode terminal of D1 is clamped at
the voltage level of C1, while the anode terminal is grounded

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4.4 Current stress on semiconductor devices Inductors L2 and L4 are operated as energy storage induc-
tors for the second stage to eventually obtain a QBC struc-
The current stress on the switches S1 and S2 is determined ture. Capacitors C1 and C2 provide the required voltage input
when they are in ON state. When S1 is ON, the inductors L1 to L2 and L4, respectively. Therefore, the value of L2 and L4
and L2 charge through D2 and S1. Hence, the current flowing is obtained using
through the switch is the sum of the inductor currents IL1 and
VC1 D VC2 D
IL2 . Thus, the current stress on S1 is given by L2 = and L4 = . (36)
2f ΔiL2 2f ΔiL4
IS1 = IL1 + IL2 . (29)
Capacitors C1 and C2 will be charged to a voltage level
Similar justification is applicable to obtain the current which is the same as that of a CBC. Thus, the value of L2
stress on the switch S2 and is expressed as, and L4 is derived as
IS2 = IL3 + IL4 . (30) Vin D
Lx =
(1 − D)(2f ΔiLx )
, x = 2, 4. (37)
Diodes D1–D4 are located closer to the input side. There-
fore, their current-carrying capacity needs to be closer to The value of C1 and C2 is obtained from the charging cur-
the input current magnitude. Fortunately, as an interleaved rent and voltage ripple impressed across them. The capaci-
structure is employed, the total current is shared. The cur- tance value is obtained from (38):
rent stress on diodes D1 and D2 is the same as the inductor
current IL1 , whereas diodes D3 and D4 are rated to carry the 2 Io D
current flowing through inductor L3 ( IL3 ). The diode current
Cx =
(1 − D)(f ΔvCx )
, x = 1, 2. (38)
stresses are expressed as
In the proposed converter, CLift is located at the farthest
ID1 = ID2 = IL1 and ID3 = ID4 = IL3 . (31) end of gain extension stages. Consequently, the maximum
potential developed between CLift and ground is equal to the
The diode current stress in terms of input current is
output voltage Vo. Therefore, the current through CLift is
expressed as
same as Io and the value of CLift is obtained from (39):
Iin
IDx = , x = 1, 2, 3, 4. (32) 2 ICLift D 2 Io D
2 CLift = = . (39)
f ΔvCLift f ΔvCLift
The current flowing through Dint is the same as the induc-
tor current IL4 and is expressed as The value of the output capacitor is computed based on
the load current and ripple voltage impressed across it. Thus,
IDint = Iin (1 − D)2 . (33) the value of Co is given by
Do is the regular output rectifier diode. Hence, the current Io D
stress on the diode Do is the same as the output current and
Co =
f ΔvCo
. (40)
is given by
IDo = Io . (34)

5 Hardware results and discussion

4.5 Design of passive components
The proposed converter is synthesised from the basic IBC
structure. Hence, the value of energy storage inductors L1
and L3 employed in the proposed IQBC is derived using the
fundamental expression given in (35):
Vin D
Lx =
2f ΔiLx
, x = 1, 3, (35)
where f is the switching frequency and ΔiLx is the magnitude
of individual inductor ripple current.
To experimentally validate the proposed concept, a pro-
totype of the proposed high-gain DC–DC converter with
the specifications given in Table 1 is fabricated and tested.
Table 2 gives the component details of the converter. STM-
32F411RE microcontroller is programmed appropriately to
generate the gate pulses for the switches. IRF25600 dual
MOSFET driver is employed to amplify the gate pulses.
Tektronix TPS2024B four-channel digital storage oscillo-
scope (DSO) is used to capture the required voltage and cur-
rent waveforms at appropriate test points using high-voltage
probes (P5210) and current probes (A622).

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Electrical Engineering

Table 1  Specifications of the proposed converter

Parameter Value

Input voltage (Vin) 24 V

Output voltage (Vo) 380 V
Output power (Po) 100 W
Switching frequency (f) 40 kHz
Duty ratio (D) 0.65

Table 2  Components used in the prototype converter

Circuit element Part no. (ratings)

Switches S1, S2 FDP33N25 (250 V, 33 A, 94 mΩ)

Diodes D1–D4, Do MUR420 (200 V, 4 A, 0.71 V)
Diode Dint UF5404 (400 V, 3 A, 1 V)
CIs (L1/L2, L3/L4) 200 μH/1.5 mH
Capacitors C1–C2 100 μF/100 V (electrolytic)
Capacitor Co 100 μF/450 V (electrolytic)
Capacitor CLift 4.7 μF/450 V (polypropylene)

The experimental waveforms indicating the gate pulses

(CH1, CH2), the magnitude of voltage applied at the input
port (CH3) and the voltage obtained across the load ter-
minals (CH4) are shown in Fig. 4a. Since an interleaved
structure is employed in the proposed IQBC, the gate pulses
are phase-shifted by 180°. However, as the duty ratio of the
switches is D = 0.65, the gate pulses overlap with each other
for a small time duration which is about 15% of the total time
period. When an input voltage of 24 V is applied, the con-
verter yields 380 V at the output with the switches operating
at a nominal duty ratio of D = 0.65 at 40 kHz frequency. The
voltage conversion ratio is 15.833 under experimental condi-
tions. Further, the value of voltage gain is in accordance with
the expected value as predicted in (20).
Figure 4b demonstrates the voltage gain extension which
is adopted in the proposed converter through the voltage
waveforms and their values obtained at key nodes. The volt-
age across capacitors C1 and C2 (CH2 and CH3, respec-
tively) is the same as the output obtainable from a CBC;
the voltage value is about 65 V which confirms the proper
operation of the first stage. The voltage obtained across the
plates of CLift (CH4) is half of the output voltage. In the
proposed IQBC, C1 and C2 serve as an input source to the
subsequent stage. The voltage obtained across CLift validates
the voltage lift technique which is adopted in the proposed
IQBC. It is interesting to note that by judiciously connecting
CLift, the voltage gain is enhanced without using additional
components.
Figure 5a depicts the input voltage (CH1) and the voltage
stress on the switches S1 and S2 (CH2, CH1) as compared
to the output voltage (CH4). Since the switches operate
Fig. 4  Experimental waveforms demonstrating a voltage gain capa-
bility and b the voltage gain extension concept
with a duty ratio of D = 0.65, both S1 and S2 remain in ON
state for a smaller duration of about 15% of the total time
period. Switches S1 and S2 are located at the output end of
each QBC structure. Therefore, the voltage stress impressed
across S1 and S2 is only about half of the output voltage; the
voltage gain extension obtained using CLift aids in reducing
the voltage stress. The voltage waveforms across S1 and S2
obtained during experiments clearly demonstrate that the
effect of leakage inductance due to the use of CIs is absent;
switches are not subjected to voltage spikes. Since the CIs
are employed for realising a compact converter (and not for
gain enhancement), the converter is carefully synthesised to
minimise the effect of leakage inductance.
Figure 5b proves the correlated operation between S1 and
the power diodes (D1 and D2) located in one interleaved
phase.
Based on the operating principle, when S 1 is turned
ON, diode D1 is reverse-biased, while D2 is turned ON. In

13

Fig. 5  Experimental waveforms demonstrating voltage stress on a S1
and S2, b D1 and D2 correlated with S1; voltage stress is compared
with output voltage
other words, switch S1 and D2 operate in a similar manner,
while D1 operates complementarily to both S1 and D2. The
behaviour is confirmed by the practical waveforms of volt-
age across D1 (CH1), D2 (CH2) and S1 (CH3). Further, the
magnitude of voltage stress experienced by D1 and D2 is
compared with the output voltage (CH4). As D1 is located
closer to the input, its voltage stress is just 18.75% of Vo. As
voltage gain progressively increases, D2 experiences a volt-
age stress magnitude which is about one-third (34.375% to
be precise) of the output voltage. The voltage stress values
closely match the predicted values and confirm the proposed
concept.
Figure 6a shows the properly coordinated operation of the
diodes D1–D4 employed in the proposed IQBC.
The individual diodes of the two diode pairs (D 1–D2
and D3–D4) in each QBC cell operate complimentarily
to each other; D1 compliments D2 while D3 compliments
13
Electrical Engineering
Fig. 6  Experimental waveforms depicting a voltage stress on D1–D4
(CH1–CH4) and b correlated operation of S2, Dint, S1 and Do
D4. However, as the duty ratio is more than 0.5 (D = 0.65),
there is a slight overlap between the diodes located in one
interleaved phase and the other. For instance, D1, D3 and
D4 remain in the same state (ON or OFF) for a short time
duration as observed in Fig. 6a. This behaviour is in perfect
agreement with the operating principle. Further, the voltage
stress magnitudes of all the diodes match very closely with
the theoretical values predicted using (23)–(26).
The experimental waveforms depicted in Fig. 6b validate
the precisely correlated operation of Dint and Do with the
switches S1 and S2.
The switch S1 and output diode Do operate in a perfect
complementary manner; the experimental voltage wave-
forms captured across S1 (CH3) and Do (CH4) confirm the
operating principle.
The operation of intermediate diode Dint and S2 is also
complementary to each other. Interestingly, the reverse volt-
age level that is impressed across Dint (CH2) depends on
Electrical Engineering
the state of S1 also [besides depending on the state of S2
(CH1)]. When both S1 and S2 conduct for a short time inter-
val, the voltage stress on Dint is half of the output voltage,
whereas the reverse voltage across Dint is the same as Vo
when S2 alone is ON. The stepped voltage waveform (CH2)
obtained during experimental conditions confirms the com-
plete behaviour that is theoretically elaborated and depicted
in the characteristic waveforms (Fig. 3). Further, the practi-
cal voltage stress values of Dint and Do closely match with
the analytical values obtained in (27) and (28).
Figure  7 shows the experimental waveforms of cur-
rent through L1 (CH1), L3 (CH2) and input current (CH3).
Owing to the interleaved structure, the total input current
is shared by the two inductors. Though the introduction of
CLift causes slight asymmetry, the overall converter per-
formance is satisfactory. Further, due to the phase-shifted
operation of the interleaved phases, the net ripple content
at the input is reduced. However, as the duty ratio is more
than 0.5 (D = 0.65), the input current ripple is about 12.9%
of the total current and is more suitable for renewable energy
applications.
The practical full-load efficiency of the proposed IQBC
is computed from Fig. 8; the waveforms are captured at the
input and output ports. From the experimental waveforms,
the full-load efficiency is computed to be 92.49%. Since an
interleaved structure is employed, the total power is shared
among the two QBC cells. Resultantly, the power loss across
the diodes and other components is reasonably low and
results in good efficiency value.
The proposed converter is intended for integrating a PV
source into a 380 V DC bus. Hence, it is essential to maintain
the output voltage at a constant value of 380 V even when the
input voltage or load current undergoes changes. Therefore, a
simple closed-loop control is implemented. A potential divider
network is used to sense the output voltage and is applied as
Fig. 7  Waveforms showing current through L1, L3 and input
Fig. 8  Practical input voltage (CH1), input current (CH2), output
current (CH3) and output voltage (CH4) waveforms to compute effi-
ciency at the full-load condition
feedback to the microcontroller, which changes the duty ratio
of the switches S1 and S2 so as to maintain the required output
voltage at 380 V.
Figure 9a shows the practical waveforms of input voltage
(CH1), output voltage (CH2) and load current (CH4). When
a step change in the input voltage occurs, the output voltage
is restored quickly to its nominal value of 380 V after being
subjected to minor variations. Practically, the proposed IQBC
delivers the required load power (at a reasonably constant load
current magnitude) when the input voltage varies from 20.9
to 27.8 V.
Figure 9b depicts the output voltage which is regulated and
maintained constant at 380 V when load current undergoes a
step change. The proposed IQBC provides a constant voltage
at its output under (1) full-load (267 mA), (2) lightly loaded
(198 mA) and (3) slightly overloaded (304 mA) conditions.
Thus, the experimental results clearly demonstrate the flawless
operation of the closed-loop control which aids in maintaining
a constant 380 V at the output port when the line voltage or the
load current changes.
The efficiency curves under simulated and practical condi-
tions are presented in Fig. 10. The proposed converter yields
a maximum efficiency of 92.49% at a power level of 100 W.
Further, the simulated and practical values closely match with
each other.
The photograph of the prototype converter is shown in
Fig. 11, and the photograph of the complete experimental
setup which is used to test the converter is shown in Fig. 12.
13

Fig. 9  Experimental waveforms depicting the voltage regulation char-
acteristics of the proposed IQBC when a input DC voltage varies
from 20.9 to 27.8 V and b load current varies in the range of 198 to
304 mA
Fig. 10  Efficiency curve of the proposed converter under simulated
and experimental conditions
13
Electrical Engineering
Fig. 11  Photograph of the proposed converter
Fig. 12  Photograph showing the experimental setup
6 Performance analysis and comparison
with few existing converters
To comprehend and appreciate the superior/beneficial fea-
tures of the proposed IQBC, it is compared with few simi-
lar state-of-the-art converters presented in [13, 19, 24].
Table 3 provides the comparison details.
6.1 Voltage gain
The proposed converter yields the highest voltage con-
version ratio among the other state-of-the-art converters.
All the converters considered for comparison use CIs for
extending the voltage gain. However, in the proposed
IQBC, CIs are used only to reduce the component count;
they do not contribute to voltage gain.
In the proposed converter, the highest voltage gain is
achieved even without the involvement of CIs. Therefore,
the superior voltage gain capability of the proposed con-
verter is validated and graphically demonstrated through
Fig. 13. The converters considered for comparison are
operated at duty ratio values less than 0.65. Nevertheless,
Electrical Engineering

Table 3  Comparison of the Attributes Converters presented in references Proposed converter

proposed converter with some
existing converters [13] [19] [24]

Input voltage (Vin) 30 18-25 48 24

Output voltage (V0) 200 200 380 380
Voltage gain (M) 7 8 7.91 15.83
Duty ratio (D) 0.47 0.61 0.55 0.65
No. of magnetic components 2 (1 multi-winding 2 (1 CI, 1 1 CI 2 CIs
CI, 1 simple induc- simple
tor) inductor)
Turns ratio CIs(n) 1.5 and 4 3 2.5 2.73 (turns ratio does not
contribute to voltage
gain)
No. of switches employed 1 1 2 2
No. of diodes employed 3 3 4 6
No. of capacitors used 4 4 5 4
Total component count (TCC) 10 10 12 14
M/TCC​ 0.7 0.8 0.66 1.13
Switch stress (% of V0) 28 15 34.2 50
Full-load efficiency (%) 93.5 97.3 95.4 92.49
Gain extension technique CI CI CI + VM Voltage lift

Fig. 14  Radial chart to demonstrate some attributes of the proposed

and state-of-the-art existing converters

Fig. 13  Voltage gain plot(s) to validate the gain capability of the pro-

posed converter compared to some state-of-the-art converters
even when the other converters are operated at D = 0.65,
the proposed converter yields the highest voltage gain.
6.2 Total component count (TCC) and M/TCC​
be the highest for the proposed converter; the M/TCC ratio
of the proposed converter is about 1.5 to 2 times more than
other converters. Thus, the use of more components is firmly
justified. The salient features of the proposed IQBC are dem-
onstrated through Fig. 14.

The proposed converter uses the highest number of com- 7 Conclusion

ponents compared to other state-of-the-art converters. For-
tunately, the proposed converter is judiciously synthesised
to yield the highest voltage gain. Resultantly, the ratio of
voltage gain (M) to total component count (TCC) works to
A non-isolated interleaved quadratic boost converter was
developed, and the voltage lift technique was employed to
achieve high voltage gain. The four energy storage inductors
were wound on two separate magnetic cores to reduce the

13

component count and obtain a compact converter. When a
DC source of 24 V was applied at the input, the converter
delivered a power of 100 W to the load at 380 V; the practi-
cal voltage conversion ratio was 15.833. The maximum effi-
ciency value of the proposed IQBC was 92.49% at the full-
load condition. Since the interleaved phases were uniformly
phase-shifted, the input current ripple was reduced to only
about 13% of the total input current. The converter output
voltage was regulated using a simple closed-loop control
technique. To test the converter performance under dynamic
conditions, the load current was varied from 198 to 304 mA;
the dynamic response of the proposed converter was excel-
lent. Further, to verify the line regulation characteristics,
the input voltage to the converter was varied from 20.9 to
27.8 V; the operating point of the converter was restored to
its nominal value (380 V) within a very short time duration
with negligible overshoot and undershoot. The main desira-
ble features of the proposed IQBC are (1) compact structure,
(2) low input current ripple and (3) higher voltage conver-
sion ratio. These desirable features make this converter an
attractive choice for use in sustainable energy microgrids.
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