Analog Integr Circ Sig Process (2010) 65:197–208
DOI 10.1007/s10470-010-9471-y
Systematic design of wideband DR modulators for WiFi/WiMAX
receivers
Pukar Malla • Hasnain Lakdawala •
Ravi Naiknaware • Krishnamurthy Soumyanath
Kevin Kornegay
Received: 6 August 2007 / Revised: 23 November 2007 / Accepted: 8 March 2010 / Published online: 30 April 2010
Ó Springer Science+Business Media, LLC 2010
Abstract Modern multi-standard receivers in deep-sub-
micron technologies pose significant design challenges on
the analog baseband. Moving this analog filtering to the
digital domain simplifies the design, yielding a process-
scalable implementation. However, analog-to-digital con-
verter (ADC) specifications now become more stringent
and must be obtained by comprehending the standard and
the system. Assuming a receiver NF of 5.96 dB and SNR
degradation of 0.36 dB by the ADC, the proposed dual-
mode WiFi/WiMAX receiver attains an input sensitivity of
-74 dBm (20 MHz channel bandwidth). To accommodate
the high dynamic range and the anti-alias rejection needed
for the system, a Delta-Sigma (DR) ADC is proposed.
Single-loop and Multi-Stage Noise-Shaping (MASH)
architectures that achieve a SNR of 69 dB at a low
P. Malla (&)
Cornell Broadband Communication Research Laboratory,
Cornell University, Ithaca, NY, USA
e-mail: pukar.malla@cornell.edu
P. Malla  H. Lakdawala  K. Soumyanath
Communications Technology Laboratory, Intel Corporation,
Hillsboro, OR, USA
H. Lakdawala
e-mail: hasnain.lakdawala@intel.com
K. Soumyanath
e-mail: krishnamurthy.soumyanath@intel.com
R. Naiknaware
Wi-Chi, Inc., Portland, OR, USA
e-mail: ravi@wi-chi.com
K. Kornegay
Georgia Electronic Design Centre, Georgia Institute
of Technology, Atlanta, GA, USA
e-mail: kornegay@ece.gatech.edu
•
oversampling ratio (OSR) of 8 for a conversion bandwidth
of 40 MHz (108 Mbps, OFDM) are investigated at system
level. Based on thermal noise, harmonic distortion, and
power tradeoffs, a DR ADC design that meets the design
specifications is presented.
Keywords Delta sigma modulator  ADC  WiFi 
WiMAX  Multi-standard  Receiver
1 Introduction
OFDM communication systems such as WiFi (IEEE
802.11a/b/g) and WiMAX (IEEE 802.16d) place stringent
constraints on the receiver design to attain high data rates.
Current WiFi systems support 54 Mbps, and increasing this
rate using MIMO techniques (IEEE 802.11n) is desirable
for growing multimedia applications. For Metropolitan
Area Networking, WiMAX systems target channel band-
widths from 2.5 to 20 MHz. To optimize cost and area,
recent architectures continue to trade analog baseband
filtering for digital channel selection in multi-standard
receivers, necessitating higher resolution ADCs [1, 2]. In
this paper, we describe a system-based approach to deter-
mine the requirements of and to design an ADC that meets
such difficult receiver design targets.
2 Receiver specification
2.1 RF front-end
Table 1 shows the specifications for IEEE802.11a and
IEEE802.16e receivers [3, 4]. 64-QAM modulation scheme
at coding rate of 3/4 has the highest SNR requirement for
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198 Analog Integr Circ Sig Process (2010) 65:197–208

Table 1 IEEE design specifications In traditional architectures as shown in Fig. 1, the ana-
Modulation Coding SNR (dB) Input Data rate
log baseband consists of a multi-pole filter to remove any
rate sensitivity (Mbps) interferers and multiple variable-gain amplifiers. While this
WiFi WiMAX (dBm) design minimizes the ADC dynamic range (DR) require-
ment, analog high-order baseband filtering and high-gran-
QPSK 1/2 5 5 -80 12
ularity gain are difficult to realize in modern process
3/4 7 8 -78 18
technologies with reducing voltage supply.
16-QAM 1/2 10 10.5 -73 24
Figure 2 depicts the proposed receiver in zero-IF
3/4 14 14 -71 36
mode. It uses a single-pole filter in the analog domain and
64-QAM 2/3 18 19 -66 48
most of the channel select filtering is implemented in the
3/4 19 21 -65 54
digital domain. Reduced filtering has the following
implications:
both standards. The maximum input bandwidth for each
1) Degraded alias rejection before the ADC.
standard is 20 MHz. WiFi receivers can be designed using
2) Increased ADC DR to accommodate larger interferers.
a zero-IF architecture. For WiMAX systems, flicker noise
constraints due to small carrier spacing could warrant a Table 2 shows the design specifications for the proposed
low-IF mode and thus, a 40 Msps ADC for both I and Q receiver. The receiver operates at input sensitivities of
channels is adopted. To increase throughput of WiFi -74 dBm in the WiFi (20 MHz) mode to attain SNR
systems, a higher bandwidth zero-IF mode (40 MHz, requirements of Table 1. In WiFi (40 MHz) and WiMAX
108 Mbps) is required. (20 MHz) modes, the input sensitivities reduce to -71 and

Low Multi-pole High Low

Granualrity Channel Granualrity Resolution
MIXER VGA1 Select Filter VGA2 ADC
I

90°
S PHYSICAL
LAYER
LO
LNA

MIXER Low Multi-pole High Low

Granualrity Channel Granualrity Resolution
VGA1 Select Filter VGA2 ADC

Fig. 1 Traditional receiver architecture

RF/ MIXER 1-pole LPF Modulator ADC

ANALOG DIGITAL
Channel
Select
I Filter VGA

90°
PHY
S LAYER
LO

LNA

Q Channel
VGA
Select
Filter

MIXER 1-pole LPF Modulator ADC

Fig. 2 Proposed receiver in zero-IF mode

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Analog Integr Circ Sig Process (2010) 65:197–208 199

Table 2 Receiver specifications

Design specification WiFi WiFi WiMAX

Channel bandwidth (MHz) 40 20 20

Receiver mode Zero-IF Low-IF
Input sensitivity (dBm) -71 -74 -69
RF gain (dB) 42
Frontend loss (dB) 2
Implementation loss (dB) 2
System NF (dB) 5.96
System IIP3 (dBm) -27
RF NF (dB) 3.60
RF IIP3 (dBm) -25
ADC reference (Vdiff peak) 0.7
SNR degradation by ADC (dB) 0.36
ADC SNR (dB) 69 72 69
Fig. 3 Spectrum of the proposed receiver at the DR ADC output
before decimation filter

-69 dBm, respectively. Since the receiver operates in low-

IF mode for WiMAX operations, the ADC conversion
bandwidth is chosen to be 40 Msps. In all modes, a mod-
erate gain of 42 dB, a one-pole low-pass filter, radio NF of
5.96 dB, a 0.36 SNR degradation by the ADC, and a
16.9 dB back-off from ADC full-scale are assumed on the
front-end to accommodate harsh interference conditions.
If pipelined architecture was chosen for the ADC, a
high-order anti-alias filter or a high OSR is required. DR
ADC architecture is ideally suited for this application
because besides reducing the anti-alias rejection require-
ment, it employs OSR towards more aggressively pushing
the quantization noise out of the signal band. The blockers
are also digitized and the digital decimation filters provide
filtering of both quantization noise and blockers. Moreover,
a DR ADC trades higher speed operation for voltage res-
olution of an analog signal and scales better in deep-sub-
micron regime.
Figure 3 shows the output spectrum of the DR ADC
with the ACI and AACI interferers of -66 and -50 dBm
respectively as specified by IEEE, a -30 dBm HIPERLAN
blocker at 50 MHz and an input signal of 20 MHz channel
bandwidth. Matlab system simulations inclusive of noise,
gain and nonlinearity models of the RF front-end and the
ADC show that the specifications of Table 2 can attain the
IEEE SNR requirements of 802.11ag, 802.16e and 802.11n
standards.
2.2 ADC
The method to derive ADC SNR in Table 2 is as follows:
(1) Find the receiver NF, NFtotal, given the input
sensitivity, Pinsens, input bandwidth, B, and the
required SNR inclusive of the baseband implementa-
tion loss, SNRmin, at the ADC output
NFtotal ¼ Pinsens  SNRmin  10 log 10ðkTBÞ ð1Þ
(2) Find the ADC NF, NFADC, and the RF front-end noise
at the ADC input, NFRFE, given the chosen ratio of
total NF allotted to the ADC, ratio and the front-end
gain, GRFE,
NFADC ¼ ratio  NFtotal ð2Þ
NFRFE ¼ ð1  ratioÞ  NFtotal ð3Þ
NRFE ¼ 10  log 10ðkTBÞ þ GRFE þ NFRFE ð4Þ
(3) Find the ADC SNR, SNRADC, given the ADC noise
factor, nfADC, front-end noise at ADC input, nRFE, and
the ADC reference power, SREF,
nADC ¼ ðnfADC  1ÞnRFE ð5Þ
SNRADC ¼ SREF  10 log 10ðnADC Þ ð6Þ
Figure 4 shows the relationship between ADC power
consumption and NFADC. The power consumption is based
on (7, 8), where P is the power consumption, FOM is the
figure of merit, ENOB is the effective number of bits and
fNYQ is the Nyquist bandwidth.
P ¼ FOM  2ENOB  fNYQ ð7Þ
ENOB ¼ ðSNR  1:76Þ=6:02 ð8Þ
In this study, we used a FOM of 0.9, which is the best
published FOM for a low OSR WLAN DR ADC [5].
Reducing NFADC from 0.4 to 0.1 requires increasing the
ADC power consumption from 78.4 to 159.6 mW. In other
words, 90.2 mW is spent to improve the input sensitivity
by 0.3 dB. As seen from (5, 6), the NFtotal and thus the
input sensitivity can be improved more efficiently by

123
200
245
225
205
185
Power (mW)
165
145
125
105
85
65
45
0.05 0.15 0.25 0.35 0.45 0.55
NF (dB)
Fig. 4 Power vs. ADC noise figure
improving NFRFE; by expending much less than 81.2 mW,
LNA NF can be improved more than 0.3. Consequently,
the lowest possible NFADC may not yield the most power-
efficient overall receiver design. In our design, we chose
NFADC to be 0.36 dB.
OFDM systems have a Peak-To-Average-Power-Ratio
(PAPR) back-off requirement of 12–17 dB. Matlab system
simulations, assuming a 16.9 dB back-off from the full-
scale of 0.7 V differential peak (12 dB for PAPR, 4 dB for
RF front-end gain variations, and 0.9 dB for ADC maxi-
mum stable input range), show that the receiver front-end
and the ADC require modest IIP3 of -25 and 17.3 dBm for
the respectively to meet the linearity constraints of the
proposed receiver. This ADC IIP3 translates to a Third-
Harmonic-Distortion (HD3) of -51 dBc. For the lowest
power design, the DR ADC was designed to be limited by
thermal noise.
Consequently, the ADC Signal-To-Quantization-Noise-
Ratio (SQNR) was chosen to be 78 dB (9 dB higher than
the required SNR). ADC sampling rate of 320 Msps (and
thus, OSR of 8) was chosen based on the limits of CMOS
process technologies at 90 nm.
3 ADC selection
This section compares two DR ADC topologies that meet
the design targets outlined in Sect. 2 of SNR of 69 dB,
SQNR of 78 dB at OSR of 8 and input bandwidth
of 20 MHz. The maximum input signal is at -9 dBFS
(-30 dBm blocker after one-pole filtering and gain); under
this condition, HD3 of -51 dBc needs to be accomplished.
After a brief architectural study of each topology, the
system implementations are compared through simulations
123
Analog Integr Circ Sig Process (2010) 65:197–208
using MATLAB and MIDAS [6, 7] and the final ADC
topology for the proposed receiver is selected.
3.1 Single loop
3.1.1 Architecture
Different designs [8, 9], employing a 5th order 4-bit, have
been proposed to accomplish high SQNR at OSR of 8.
Such higher order filter structures result in lower maximum
stable input range (Umax) of about -4 dBFS, aggravating
the thermal noise requirements on the ADC and post-ADC
blocks. High order limits the noise transfer function (NTF)
0.65 0.75 0.85 0.95 gain at infinity (Hinf) to 3 or less. As a result, some in-band
zero optimization is warranted to reduce in-band quanti-
zation noise; the feedback coefficients for zero insertion in
the NTF are small and matching considerations require
larger capacitors, thus increasing the over-all ADC area.
The proposed alternative is a 4th order 5-bit solution,
where reduction in the filter order and 1-bit increase in
FLASH bits yields a higher Umax. At the same time, Hinf
can be increased to 6, further suppressing the in-band
quantization noise. However, doubling of FLASH levels
doubles the comparator offset requirement. Over-all, this
solution is selected over 5th order 4-bit for its power-per-
formance superiority.
Figure 5 compares the signal transfer function (STF)
curves for feedback and feedforward architectures; no NTF
zero-insertion, Hinf of 6, and 5-bit FLASH are used.
Feedback architectures can provide some out-of-band
filtering through the STF shaping and are more suited for
the proposed receiver. On the other hand, feedforward
architectures can comprise of out-of-band STF peaking at
higher frequencies, resulting in system instability in the
presence of blockers [10].
15
10
Feedback
5 Feedforward
STF (dB)
0
-5
-10
-15
0 20 40 60 80 100 120 140 160
Frequency (rad)
Fig. 5 Feedback and feedforward STFs
Analog Integr Circ Sig Process (2010) 65:197–208 201

Moreover, the feedforward architecture requires addi- 3.2 Mash

tional circuitry to implement the analog summation [8, 9,
11]. In addition, the first integrator gain is larger than that
in the feedback case increasing the unity gain bandwidth
constraint on the first two opamps.
Feedforward architectures benefit from reduced inte-
grator output swing and better distortion performance [12].
However, this feature is not critical in our proposed
receiver with the 16.9 dB back-off from full-scale, result-
ing in moderate ADC linearity requirement. Finally, a 4th
order 5-bit feedback structure was chosen.
3.1.2 System
MIDAS system-level simulations with non-ideal effects of
kT/C noise, harmonic distortion, opamp finite gain, slew
rate, finite bandwidth, DAC nonlinearity, and coefficient
quantization yield the system requirements as depicted in
Fig. 6 [13]. The figure shows a single-ended schematic
block diagram. The input and the feedback capacitors in
the first integrator are merged to minimize thermal noise.
Next to each capacitor, the number of unit capacitors is
shown. Whereas the switches are not shown, delaying
integrators are assumed.
A Data-Weighted-Averaging (DWA) scheme suffi-
ciently addresses DAC nonlinearity issues assuming
capacitor mismatch of 0.1% [14]. Integrator outputs are
scaled to half of fullscale to minimize opamp output
distortion.
The loop coefficients indicate that the first and the
second stages of the design are equally important. Even
though, the second stage benefits from first-order noise
shaping, it is presented with a signal attenuated by 20 dB.
As a result, thermal noise and the opamp requirements of
the first two integrators become similar. Consequently, the
noise requirement necessitates doubling the total input
sampling capacitor size for each integrator.
3.2.1 Architecture
Designs reported in [15, 16] achieve required SNR at OSR
of 8. The 2-1-1 topology in [16] is more sensitive to
coefficient mismatch [17] than 2-2 topology reported in
[15] and thus the latter was selected. Feedback filter
topology was selected for each of the two loops for better
interferer immunity. 4-bit and 3-bit FLASH ADCs were
used respectively in the first loop (LOOP1) and the second
loop (LOOP2) of the proposed 2-2 topology. An interstage
gain of 4 was chosen to avoid the need for multipliers in
the digital noise cancellation logic.
3.2.2 System
Figure 7 shows a single-ended schematic block diagram of
the proposed 2-2 MASH. Delaying integrators are
assumed. The quantization error of the first loop is sampled
onto the first integrator of LOOP2 as the difference
between V1 and Y1 as shown in the figure. A higher
coefficient gain before the first integrator compared to the
single-loop design results in the non-idealities of second
integrator being less critical in the ADC performance than
the first integrator. DWA algorithm is necessary only in the
feedback path of LOOP1 to address capacitor mismatch
issue. Monte-Carlo simulations show that a capacitor
matching of 2.5%, resulting in digital-analog gain mis-
match and coefficient variation on the integrator stages is
tolerable.
The integrator output swings of the first and second
integrators were kept at 40% and 60% of full scale to
minimize distortion requirements of the opamps. The first
opamp of the LOOP2 provides an interstage gain of 4 and
thus the unity gain bandwidth requirement is comparable to
the second opamp of LOOP1. HD3 of -48 and -45 dBc

Fig. 6 Single-loop system AdB=30dB AdB=30dB AdB=30dB AdB=30dB

implementation HD3=-43dBc HD3=-42dBc HD3=-40dBc HD3=-40dBc
nTau=4.5 nTau=4.5 nTau=4.5 nTau=4.5
SR=300V/µs SR=300V/µs SR=300V/µs SR=300V/µs
Cin=650fF Cin=650fF Cin=325fF Cin=160fF
Merged cap 217 88 38 16

31 49 53 47
V
U

31 31 31 31

31 31 31 31

DEM
Logic

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202 Analog Integr Circ Sig Process (2010) 65:197–208

Merged cap 40 12
12 20
Y1 V1 4.Z-2
U

12 AdB=50dB 12 AdB=45dB DEM

HD3=-46dBc HD3=-40dBc Logic
12 nTau=4.5 12 nTau=4.5
SR=300V/µs SR=300V/µs V
Digital
Cin=300fF Cin=300fF Noise
12 Cancellation

12 20 6
40
10
Y2 V2
(1-z-1)2
24
AdB=50dB 6 AdB=50dB
6 HD3=-40dBc HD3=-40dBc
nTau=4.5 nTau=4.5
6 6
SR=300V/µs SR=300V/µs
Cin=42.9fF Cin=37.5fF
6

Fig. 7 2-2 MASH system implementation

on the first and the second opamps of LOOP1 suffice to MASH topologies typically have two disadvantages. They
meet HD3 of -51 dBc for the ADC with an input signal of require higher DC gain and inter-stage gain control to
-9 dBFS. Higher harmonic distortion performance is not ensure adequate matching between the digital and the
required of the opamps since the input signal is 16.9 dB analog transfer functions and thus suppress quantization
backed off from full-scale. noise leakage of first loop.
The minimum DC gain needed in single-loop architec-
3.2.3 Comparison ture is about 30 dB. In reality, a higher gain of about 50 dB
is necessary to support the swing at the opamp output,
Table 3 shows the comparison between single-loop and while keeping the opamp HD3 at about -45 dBc. Monte-
MASH implementations from opamp design perspective. Carlo simulations depicted in Fig. 8 assuming capacitor
mismatch of 2% over 50 runs show that either system
Table 3 Delta sigma ADC opamp comparison behaves similarly.
The single-loop design requires more than twice the size
Parameter MASH Single-loop
of capacitors than in MASH because of the smaller coef-
Opamp1 Opamp2 Opamp1 Opamp2 ficient gains before the first two integrators. Consequently,
the MASH design is more power-efficient than single-loop,
Input capacitor (fF) 300 300 650 650
while meeting similar settling constraints. Furthermore, the
HD3 (dBc) -46 -40 -43 -42
single-loop DR ADC design requires one more bit on the
DC Gain (dB) 50 45 30 30
FLASH ADC. This increases power and complexity due to

Fig. 8 Monte-Carlo simulation

histograms

123
Analog Integr Circ Sig Process (2010) 65:197–208 203

70 4.1 Loop filter

65
SNR(dB)

Figures 10 and 11 show the single-ended version of the

60
implementation of LOOP1 and LOOP2. Figure 12 shows
SINGLE SNR
55
MASH SNR
the timing diagram for the implementation. Delaying
50
integrators were employed in either loop. The input sam-
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 pling capacitor and the DAC feedback capacitors are
Input Level (dBFS) shared between the two phases of each cycle to reduce
70 kT/C noise. Non-overlapping clocks were generated
on-chip. Bottom plate sampling was used to mitigate sig-
SNDR(dB)

65
nal-dependent charge injection. Since linearity require-
60 ments are relaxed, transmission gate-based switches were
SINGLE SNDR
55 MASH SNDR
used. The input capacitor is shared between the signal path
and the feedback path in the first integrator of LOOP1 to
50
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 reduce the total input capacitor size, and thus power con-
Input Level (dBFS) sumption. Interstage gain of 4 between the two loops was
implemented using capacitive gain in the first integrator of
Fig. 9 SNR, SNDR comparison
LOOP2 as shown in Fig. 11.
Differential telescoping opamps, as shown in Fig. 13,
were used for all the opamps for the high speed, low power
the need for 16 more comparators and halving of the
and low noise properties. Scaling of 0.4 and 0.6 of the full
comparator offset. Similarly, the number of bits in the
scale on the first two opamps, combined with benign
DEM logic doubles, thus doubling the digital power
HD3 requirement, makes this topology suitable for our
consumption.
design. Switched capacitor common mode feedback was
The HD3 requirements of the opamps in the two systems
employed.
are similar. MASH requires slightly higher HD3 since the
Table 4 summarizes the OTA performance of the first
distortion induced by LOOP1 affects the performance of
integrator, assuming worst-case corner for each of the
the digital noise cancellation logic.
parameters. Since the remaining integrators benefit from
Figure 9 shows the SNR and SNDR curves of the two
noise shaping, their input sampling capacitor sizes are
topologies as a function of the varying input signal levels.
scaled down and the opamp gain reduced as per the noise-
An input signal at 3 MHz is used as the input so that the
shaping order to save power.
third and fifth harmonic distortions fell in the signal
bandwidth of 20 MHz and 4096-point FFT is used to cal-
culate the modulator performances. Although single-loop
4.2 FLASH ADC, DEM and DAC
designs have lower distortion at close to fullscale, at
-9 dBFS, the maximum possible input signal in our
Fully differential design was used as shown in Fig. 14.
receiver design, the two ADC topologies yield the same
Since the two FLASH ADCs benefit from second and
SNDR. Additionally, the SNR plots show that MASH
fourth order noise shaping, the comparator offset require-
yields 0.6 dB higher maximum stable input range, resulting
ments were relaxed. Each comparator consisted of a
in lower power (higher front-end gain and lower ADC
preamplifier, a regenerative latch and a SR latch. The
resolution) or increased system stability (higher ADC input
preamplifier was implemented as a differential amplifier
back-off). The latter was chosen in this design. Based on
biased in weak inversion for high gm/Id and provided 8-dB
the comparison, the MASH topology is more optimal to
gain. A differential resistive ladder was used to generate
attain the ADC design targets for our proposed multi-
the reference voltages. Each comparator consumed 225
standard receiver.
and 45 uA of digital and analog current. Architectural
coefficient between the output of second opamp in LOOP1
and the FLASH ADC was implemented using reference
4 Circuit implementation scaling as shown in Fig. 14.
Thermometer code from FLASH ADC is sampled onto
The 2-2 MASH system presented in Sect. 3.2 was imple- unit capacitors in the feedback path as shown in Figs. 10,
mented in a 90 nm Intel CMOS process using switched- 11. Nonlinearity issues from DAC capacitor mismatch is
capacitor integrators, full-scale of 0.7 V differential and addressed using Data Weighted Averaging (DWA) algo-
power supply of 1.3 V. rithm, which consumes 1.54 mA of current.

123
204 Analog Integr Circ Sig Process (2010) 65:197–208

Fig. 10 LOOP1 single-ended implementation

Cf1=20*10fF Cf1=5*10fF

p1d p2 p1d p2 p2d

LOOP1X2 LOOP2X1 LOOP2X2 LOOP2

p2d Cs2i p1 p2d Cs2l p1 p1d p2

Cs3n
i=0, ..39 l=0, ..9 n=0, ..5
Vref[n] platch

p1d p2
Cs2i=10fF
p1d p2 Cs2l=10fF 6
p1 Cs2j=10fF
Cs2j Cs2m=10fF
Cs2k=10fF
Cs2m p1
LOOP1V[0..11]

j=0, ..23
LOOP2V[0..5]
Vrefp Vrefn
p2d
m=0, ..5
Vrefp Vrefn
6
p1d p2

Cs2k p1

LOOP2V[0..5]

k=0, ..5
Vrefp Vrefn

Fig. 11 LOOP2 single-ended implementation

5 Simulation results

Schematic simulation was run using Cadence Spectre.

Capacitor mismatch was not introduced in the simulation
and DEM functionality was verified at system level using
MIDAS. Figure 15 shows a 4096-point FFT output spec-
trum of the 2-2 MASH system. A -1 dBFS input signal at
Fig. 12 System timing diagram 3.671875 MHz is chosen so that the third and fifth

123
Analog Integr Circ Sig Process (2010) 65:197–208 205

0
Vb

M7 M8 -20

Output Magnitude (dBFS)

p1 p1
p2 p2
-40

C2 C1 C3 C4
-60

p1 p2 p2 p1
M5 M6 -80
Vcm
-100
Vout
-120 LOOP1
2-2 MASH
M3 M4 -140
1 10 20 160
Frequency (MHz)

Fig. 15 LOOP1 and 2-2 MASH output spectrum

Vin M1 M2 Vin
SNR, and SNDR of 79.6, 72.8 and 60.6 dB respectively at
-0.5 dBFS.
Ib Thermal noise was not included in the schematic
simulation. The SNR in Fig. 16 is calculated using (9),
where QN is the quantization noise power and TN is the
Fig. 13 Gain-boosted telescopic opamp topology total thermal noise power. TN is calculated using (10),
where and M is the oversampling ratio and C is the input
Table 4 LOOP1 First Integrator OTA Performance capacitor of the first opamp (360fF in our design). We
Gain (dB) 65 estimate the total thermal noise by increasing it by 1.3
PM (°) 70 times to account for opamp noise contribution [18]. IIP3
UGF (MHz) 1600 can be derived from HD3 based using (11) and (12),
Slew rate (V/ls) 2000 where A is the input signal amplitude, a1 is the funda-
Load (fF) 750 mental and a3 is the third-order multiplier coefficient of a
HD3 (dBc) -75 non-linear system.
pffiffiffiffiffiffi
Input-referred Noise (nV Hz) 0.12 Umax
SNR ¼ ð9Þ
Settling (# of ss @400 MHz) 6.5 Q N þ TN
Power (mW) 3.9 kT
Voltage supply (V) 1.3 TN ¼ 2  3:3  ð10Þ
MC
 
1 a3 2
harmonic distortions fell in the signal bandwidth of HD3 ¼ 20  log 10 A ð11Þ
4 a1
20 MHz. The HD3 of the modulator is -61.4 dBc. Fig-  
ure 16 shows SQNR, SNDR and SNR as a function of 4 a1 1
IIP3 ¼ 10  log 10  þ 30 ð12Þ
input signal level. The modulator exhibits a peak SQNR, 3 a3 50

Fig. 14 Differential LOOP1 d<11> d<10> d<9> d<8> d<7> d<6>

FLASH ADC
4.5R R R R R R
vrefp

vin R

vrefn
4.5R R R R R R

d<0> d<1> d<2> d<3> d<4> d<5>

123
206 Analog Integr Circ Sig Process (2010) 65:197–208

80 80
Laboratory at Intel Corporation and the Cornell Broadband Com-
75
munication Circuits Laboratory at Cornell University.
70 SNDR, SNR, SQNR (dB)
70
SNDR, SNR, SQNR (dB)

60 65

60
SNDR
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55
SQNR

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Input Signal Level (dBFS)
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SQNR
end for a multistandard WLAN receiver. IEEE Microwave and
10
Wireless Components Letters, 15(5), 321–323.
0 3. IEEE Standard 802.11-1999, Part 11: Wireless LAN Medium Access
Control (MAC) and Physical Layer (PHY) Specification, 1999.
-80 -60 -40 -20 0 4. Part 16: Air interface for fixed broadband access control systems,
Input Signal Level (dBFS) http://standards.ieee.org/getieee802/download/802.16e-2005.pdf,
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EDGE/UMTS/WLAN Tri-Mode DR ADC with -92 dB THD.
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Peak SQNR 79.6 dB 8. Balmelli, P., & Huang, Q. (2004). A 25-MS/s 14-b 200-mW RD
Mod. in 0.18-lm CMOS. IEEE Journal of Solid-State Circuits,
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bit DRA/D and D/A converters using data weighted averaging.
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Analog Integr Circ Sig Process (2010) 65:197–208
Pukar Malla received his
Bachelors in Science degree
from Swarthmore College, PA
in 2002 with Honors Major in
Engineering and Honors Minor
in Economics and Masters in
Science from Cornell Univer-
sity, NY in 2006. From 2002 to
2004, he worked as Micropro-
cessor Design Engineer at Sili-
con Graphic Incorporated,
Mountain View, CA on clock
distribution networks and at
Advanced Micro Devices, Aus-
tin, Texas on cache design.
Between 2005 and 2007, as Research Scientist at Communications
Technology Laboratory in Intel Corporation, Hillsboro, OR, he con-
ducted his research on cognitive multi-standard WiFi/WiMAX
receivers and wideband Delta Sigma ADCs. After attaining a Ph.D. in
Electrical and Computer Engineering from Cornell University with
Minor in Business Management in 2007, he has been working as
Chief RF/Systems Architect at MediaPHY, a Silicon Valley start-up
commercializing low-power video-over-wireless chips. His research
interests are in low-power, cognitive, multi-standard wireless
receivers and mixed-signal circuits and systems.
Hasnain Lakdawala received
his undergraduate degree in
1995, from the Indian Institute
of Technology, Bombay India,
and the Master’s degree from
the University of Hawaii,
Manoa, HI in 1997, both in
Electrical Engineering. He
received his Doctorate degree in
Electrical and Computer Engi-
neering from the Carnegie
Mellon University, Pittsburgh
PA in 2002. From 2002 to 2004,
he was a Product Architect at IC
Mechanics Inc, Pittsburgh PA
responsible for the development of single chip CMOS based HDD
shock sensors. He has been a Research Scientist at Intel Corporation,
Hillsboro, OR since 2004. His research interests include RF and
analog circuits for WLAN transceivers that exploit scaled CMOS
processes.
Ravi Naiknaware received the
B.Tech. and M.Tech. degrees in
Electrical Engineering from
Indian Institute of Technology,
Bombay, India in 1989 and
1991, respectively and the Ph.D.
in Electrical and Computer
Engineering from Washington
State University, Pullman, WA
in 1999. From 1991 to 1994, he
was with Texas Instruments,
Bangalore, India, where he was
engaged in design solutions for
Linear and Mixed Signal appli-
cation groups. In 1999, he
joined Maxim Integrated Product, Hillsboro, OR, where he was
engaged in wide-band high-frequency high-resolution data converters
and ultra low-power data converters and analog front-ends for multi-
band, multi-standard wireless base-stations and consumer wireless
207
applications, respectively. From 2005 to early 2007 he was a
Research Scientist at Intel Corporation, Hillsboro, OR in the Com-
munications Circuit Laboratory, where he was involved in architec-
tural and circuit-level research in WiFi/WiMAX radios. Currently he
is the Founder and Chief Technology Officer of Wi-Chi, Inc., Port-
land, OR. Wi-Chi, Inc., engaged in commercial development of
advanced emerging technologies. His areas of technical interests
include high performance RF and analog-mixed signal circuits,
advanced wired and wireless communication systems, microwave
systems, antennas and computer aided design.
Krishnamurthy Soumyanath
(IEEE SM since 2009) (Sou-
mya) is an Intel Fellow and is
currently Chief architect of Intel
Platforms research, at Intel labs.
Soumya joined Intel in 1996,
working in the Circuits
Research Laboratory and lead-
ing the high-performance cir-
cuits research group. His team
developed several high-speed
data path components used in
microprocessors. During his
Intel career, Soumya has held
a number of engineering and
management positions in the area of semiconductor circuit design. He
has published more than 50 papers and has had more than 30 patents
issued. He is currently responsible for leading research and devel-
opment activity on circuits and architectures for next-generation
transceiver devices. His team’s efforts are focused on increasing the
abilities of digital processing in wired and wireless communications
systems and in making them compatible with scaled CMOS devices.
Soumya earned his bachelor’s degree in electrical engineering from
the National Institute of Technology in Tiruchirappalli, India in 1979
and his master’s degree in the same discipline in 1985 from the Indian
Institute of Science, Bangalore. He received his Ph.D. in computer
science and engineering from the University of Nebraska in 1993. In
addition to circuits of all kinds, his research interests include classical
Tamil poetry and Palm leaf manuscripts.
Kevin Kornegay received his
B.E.E. from Pratt Institute in
1985 and his M.S. and Ph.D.
from the University of Califor-
nia at Berkeley in Electrical
Engineering and Computer Sci-
ence in 1990 and 1992, respec-
tively. In the early part of his
career, he was employed in
industrial research positions at
AT&T Bell Laboratories in
Murray Hill, N.J. and at IBM
Thomas J. Watson Research
Center in Yorktown Heights,
N.Y. From August 1994 through
December 1997, he was an assistant professor in the School of
Electrical and Computer Engineering at Purdue University. In 1997,
Professor Kornegay was the Dr. Martin Luther King, Jr. Visiting
Professor in the EECS department at MIT. From January 1998
through December 2005, Professor Kornegay was on the faculty in
the School of ECE at Cornell University, where he led the Cornell
Broadband Communications Research Laboratory and was the faculty
advisor to the 2003 World Champion CUAUV team and to the
Cornell chapter of the National Society of Black Engineers. In 2006,
Professor Kornegay joined the School of ECE at Georgia Tech as the
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208 Analog Integr Circ Sig Process (2010) 65:197–208

Motorola Foundation Professor, where he is involved with the Conference, the International Solid-State Circuits Conference, the
Georgia Electronic Design Center. In addition, he currently serves on Radio Frequency Integrated Circuits Symposium, and the Interna-
the technical program committees of the Custom Integrated Circuits tional Conference on Circuits and Systems.

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