2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
Wide Band Linear Voltage-to-Current Converter Design
Chun Wei Lin, Sheng Feng Lin, Chi Fu Wang
Department of Electronic Engineering,
National Yunlin University of Science & Technology, Yunlin, Taiwan
linwei@yuntech.edu.tw
Abstract - In this work, we propose a wide band linear
voltage-to-current converter (VIC) with mobility
degradation compensation. By use of NMOS output stage
and grounding NMOS input stage, PSRR enhances as well
as body effect decreases. In addition, through utilizing the
sum of two current sources operate in linear and saturation
region respectively, the nonlinearity of complementary
parabolic voltage to current characteristics caused by
mobility degradation are reduced. A feedback loop is then
inserted to increase bandwidth, so that the proposed VIC is
useful in further applications. A practical chip was
fabricated by TSMC 0.35 Pm 3.3V CMOS process with its
measured transconductance ( Gm ), bandwidth, and
operational range are 0.975~1.032, 85.5MHz, and 1.2V
respectively. The experiment results show that the
proposed design significantly improves bandwidth and the
nonlinearity effect of VIC originated from mobility
degradation.
Keywords: voltage to current converter (VIC), mobility
degradation, transconductance ( Gm ), PSRR
1. Introduction
Voltage to current converter (VIC) is widely used in
Gm-C filter, data converter, voltage control oscillator,
built-in self-test circuit and so on. Bandwidth and
linearity are the usually concerned specifications of VIC
which dominate whether its performance is adequate.
However, the velocity saturation and mobility
degradation effects brought from advance of fabrication
process raise the difficulty to design a high performance
VIC. The nonlinear effects of VIC mainly including
nonlinear second-order V-I characteristic, body effect,
velocity saturation, mobility degradation, temperature
variation, power noise and so on [1-4]. Regarding to
these subjects, many design techniques were proposed in
past few years [5-11]. The general method to design a
linear VIC is by utilizing extra circuitry to provide
current compensation which cancel the second-order
term in original V-I characteristic of transistors. This
second-order nonlinear term can be cancelled by
subtraction of two current sources operate in linear and
saturation region respectively [12-14]. Under the NMOS
input structure of these techniques, we have to neglect
the body effect to meet design requirement which maybe
978-0-7695-3978-2/10 $26.00 © 2010 IEEE
DOI 10.1109/DELTA.2010.24
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infeasible for implementation. On the contrary, the input
stage must be equal and large enough for PMOS input
structure. In addition, the power noise rejection ability
of PMOS-based VIC is poor because the power noise
directly affects the drain-source voltage of transistor and
results in unstable current output.
Nevertheless, the mobility degradation of short
channel device is evident and raises more complicated
nonlinear terms. The mobility degradation is inversely
proportional to the dimension of transistors on the whole.
In order to reduce the effect of mobility degradation, a
mobility degradation coefficient was adopted to modify
the current equations of transistors [10]. This revision of
transistors V-I characteristic is beneficial to implement
linear VIC in deep sub-micro process.
The remainder of this paper is organized as follows.
Section 2 discusses about mobility degradation effect.
Section 3 describes the proposed method and its design
flow. We present mathematical explanation to
demonstrate its theory in this section as well. Section 4
and section 5 will show experiment and measurement
results of a practical design and conclusion.
2. Mobility degradation effect
When we describe the relationship between gate
voltage and drain current of a transistor, we usually
assume the carrier mobility is constant. However, the
carrier mobility varies with the intensity of electric field
and it decays with velocity saturation of the carrier [18].
The mobility degradation effect of VIC circuit is
obvious that the produced current will be decreased. The
following equations describe conventional VIC are used
to explain this phenomenon. The drain currents of
transistors operate in linear and saturation region are:
2
VDS _ Lin
I Lin K Lin [(VGS _ Lin  VT )VDS _ Lin  ] (1)
2
1
I Sat K sat (VGS _ Sat  VT ) 2 (2)
2
If K Lin K Sat K , Vin VGS _ Lin and VGS _ Sat
is driven to VDS _ Lin  VT , then
I out I Lin  I Sat K (Vin  VT )VDS _ Lin (3)
115
As the result of Eq. (3), it exhibits linear Vin  I out
relationship. Nevertheless, as shown in Fig. 1, a simple
simulation shows that Vin  I out curve is not expected
linear relationship because the mobility degradation
effect reduces the output current. In the BSIM model
[16], the mobility degradation of carrier was well
modeled and it also formulated the effect of mobility
degradation according to several important factors
which are body effect, gate bias, thickness of oxidation
layer and threshold voltage. If mobility degradation
effect is set to be zero, then the simulation results will
show expected linear Vin  I out relationship as shown
in Fig. 1.
Through the simple experiment, we know that
mobility degradation effect should be concerned if we
intend to design linear VIC. We therefore need to
modify the equation describes the mobility of carrier
[15][17]. In regard to consider on intensity of electric
field of carrier, the modified equation describes mobility
of carrier is expressed as:
P0
P eff
1  T (VGS  VT )
, where T is mobility degradation factor.
The mobility degradation factor actually relates to
vertical electric field ( VGS ), horizontal electric field
( VDS ) and dimension of transistors. With fixed VGS ,
the T increases with VDS increases in linear region,
but contrarily decreases in saturation region. In addition,
T decreases both in linear and saturation region with
respect to increased dimension [18]. In other words, the
mobility degradation factor is inversely proportional to
Base on consideration of mobility degradation
factor, we propose a wide band linear VIC design shown
in Fig. 2. The NMOS output stage is adopted instead of
using PMOS [13] to enhance power noise rejection
ability. The NMOS input stage is further grounding, so
that body effects decrease as well. To drive the M Lin
into linear region, the feedback loop with an operational
amplifier and bias V X clamps the drain of M Lin to
an adequate low voltage. As the result of mobility
degradation effect, the distribution of mobility
degradation factor and the current-voltage relationship
of current sources operate in linear and saturation region
are complicated. As shown in Fig. 3, the I-V
characteristic of linear and saturation region appear to be
complementary parabolic curve analogously. We
intuitively sum up these two current and reasonably
deduce the result should be linear-like relationship.
Therefore, we have to find out certain conditions that
reduce the difference between linear-like and pure linear
relationship.
(4) The current equations of transistors operate in
linear and saturation region with mobility degradation
effect can be expressed as:
K Lin
I Lin
1  T Lin (Vin  VT )
(5)
2
VDS _ Lin
u [(Vin  VT )VDS _ Lin  ]
2
K Sat
I Sat (Vin  VT ) 2 (6)
1  T Sat (Vin  VT )
Vx
+

dimension of transistors and it approaches to constant

M5 M6
value if transistor size is quite large. M1 M2

Vin I out
M3 M4
C1
Without mobility degradation M Sat MLin
M7 M8
Current (A)

C2

Fig. 2. Structure of VIC

With mobility degradation

Linear region
Current (A)

Vin (V)

Fig. 1. Vin  I out relationships of conventional VIC Saturation region

with and without mobility degradation effect.

3. The proposed VIC design Fig. 3. I-V characteristic of two current sources in
3.1 Concept of proposed method Fig. 2. with mobility degradation effect.

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Because VDS _ Lin is clamped to be V X with a small T
MIN ( AT Lin [1  ( Lin ) 2 ]) H (9)
value, then the summation of current can be expanded T Sat
by Taylor series as:
Before we determine dimension of transistors, we have
I out I Lin  I Sat to perform several iterations on choosing ratio of
K Lin K Sat transistor size to approach minimal H .
# (Vi ) A  (Vi ) 2 The iteration process begins from reasonable
1  T Lin (Vi ) 1  T Sat (Vi )
choosing the initial size of M Lin with its
# AK LinVi  ' (7)
corresponding T Lin . For TSMC 0.35 Pm 3.3V CMOS
, where
A VDS _ Lin , Vi (Vin  VT ) , process, the T Lin is within 0.1~0.7. We therefore chose
T Lin 0.4 and calculated the size of M Lin be
' ( K SatVi 2  AK LinT LinVi 2 ) 
(W / L) Lin 12.5 P / 2 P through Eq. (8) with fixed
( AK LinT Lin 2Vi 3  K SatT SatVi 3 )  (W / L) Sat 1P / 2 P . Because of mobility degradation
( K SatT Sat 2Vi 4  AK LinT Lin 3Vi 4 )  ....... factor varies with gate-source voltage, drain-source
voltage and dimension of transistors, we have to
and the higher order terms are neglected. In order to calculate T Lin and T Sat value with respect to various
obtain the linear I-V characteristic, ' should be zero Vin through Eq. (5)(6) and evaluate H value in Eq. (9).
and hence derive following equations. After that, the iterations on tuning size of M Lin will be
hold till H of Eq. (9) is minimized. For instance, the
K Sat T T
AT Lin AT Lin ( Lin ) AT Lin ( Lin ) 2 (8) iteration on tuning size of M Lin began from
K Lin T Sat T Sat
(W / L) Lin 12.5 P / 2 P and after decreased the
Because AT Lin is a very small value, then Eq. (8) can transistor size to (W / L) Lin 5 P / 2 P , the H was
be further rewritten as: almost minimized. The fine tuning was next
K Lin !! K Sat accomplished and obtained the final transistor size,
(W / L) Lin 5.1P / 2 P .
Base on discussion in section 2 that the mobility
degradation factor is inversely proportional to dimension 3.2 Bandwidth enhancement
of transistors, we know relationship between T Lin and
The feedback loop includes C1 , C2 , M 7 , and
T Sat will be:
M 8 is used to increase bandwidth of VIC. The output
T Sat !! T Lin
signal is divided by capacitors and drives M 7 and
We therefore obtain the relationship: M 8 to saturation and linear region respectively.
Consequently, the complementary parabolic I-V
T Lin characteristic of M 7 and M 8 is similar to the
AT Lin !! AT Lin ( )
T Sat relationship between M Sat and M Lin . To explain the
effect of this feedback loop, we simplify Fig. 2 to a
The result is unfortunately out of expectation that signal flow graph as shown in Fig. 4.
incompatible with Eq. (8).
If we analyze the nonlinear term, ' , in Eq. (7) the  ȕLin
id8
polarity of even-order and odd-order terms are positive
and negative respectively. Therefore, we attempt to find id .Lin id 2
gm.Lin Ai1.2
a condition that adjacent terms in ' will almost be
cancelled one another and its value also be reduced.
vin Ai3.4 iout
gm.Sat Ai5.6 i
Base on this concept, we do not find the condition fits id .Sat d6
Eq. (8) anymore but find a condition almost fits this id7
equation. That is:  ȕSat

Fig. 4. Signal flow graph of Fig. 2.

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 Through frequency response analysis, the open measured transconductance compared to that of
loop and close loop transfer function of this circuit pre-layout-simulation and post-layout-simulation. It
includes a zero and three poles can be briefly expressed seems the linearity of circuit is fairly good. The
as following equations. measured Gm sweeps around a variation region,
0.975~1.032, which increases slightly compared to
iout simulation result, 0.983~1.007.
Gmo ( ) open Ai 3.4 u ( g m.Lin Ai1.2  g m.Sat Ai 5.6 )
vin We compared our method with several published
Gm (1  s / z1 ) techniques and summarized into Table I. With 1.2V
(10) input range and consideration of mobility degradation
(1  s / p1 )(1  s / p 2 )(1  s / p3 ) effect, the normalized Gm is similar to other methods.
, where Aim.n is current gain from M m to M n . The bandwidth is significantly improved to 85.5MHz
Gmo and the current error is within 1.8% under r10%
Gmc (11)
Gmo power supply variation as well. In addition, we also
1 ( E Lin  E Sat ) verified our design under both typical and corner models
g m.Lin  g m.Sat
and summarized results in Table II. No matter in typical
, which assume Ai1.2 Ai 5.6 . or corner models, the circuit exhibits good linearity.

C1 ( g m7  g m8 ) Z out
E E Lin  E Sat (12)
C1  C2
, where Z out is output impedance.

As a result of this feedback loop, the bandwidth is

hence increased (1  Gm E ) times. The Fig. 5 shows
the difference of frequency response with and without
improvement. The bandwidth of circuit is obviously
enhanced to almost 10 times.
Fig. 6. Photograph of chip.
IJįıĵ

IJįıĴ

IJįıij
ŏŰųŮŢŭŪŻŦťġňŮ

IJįıIJ
ŮŦŢŴį
űųŦŴŪŮ
IJįıı
Improvement űŰŴŵŴŪŮ
Gm (dB)

ıįĺĺ

ıįĺĹ

ıįĺĸ
IJįĶ IJįĸ IJįĺ ijįIJ ijįĴ ijįĶ ijįĸ ijįĺ

ŊůűŶŵġŷŰŭŵŢŨŦĩŗĪ

Fig. 7. Transconductance curve of implemented VIC.

Frequency (Hz)

Fig. 5. Improvement of bandwidth.

4. Chip implement and measurement
The circuit in Fig. 2 had been implemented by
TSMC 0.35 Pm 3.3V CMOS process with V X is
biased to 0.2V. The photograph of implemented chip is
shown in Fig. 6. The top layer of chip was pre-opened
eight observation windows, so that we can use probe
station to probe internal nodes directly. The
measurement results are also reported in Fig. 7 show the
5. Conclusion
In this paper, we have proposed a wide band
linear voltage-to-current converter with mobility
degradation compensation. This design is based on
utilizing the sum of two current sources which
operate in linear and saturation region respectively.
By summing complementary parabolic voltage to
current characteristics caused by mobility degradation,
the nonlinearity effect can be significantly reduced. In
addition, the use of NMOS output stage and
grounding NMOS input stage, PSRR enhances as
well as body effect decreases. A feedback loop is also
inserted to increase bandwidth, so that the bandwidth

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is significantly improved. The theoretical analysis Acknowledgement
and design flow are developed well and a practical The authors would like to thank National Chip
chip was fabricated with its measured Implementation Center (CIC) for technical support
transconductance and bandwidth is 0.975~1.032 and and chip fabrication.
85.5MHz respectively under 1.2V operation range.
The experiments show very good result and
demonstrate the practicability to apply this design to
those applications with strict current demand.

Table I. Comparison of several techniques

[3] [5] [13] [15] [18] This work
Tech. 0.18um 0.35um / 3.3V
Input Range (V) -0.5 - 0.5 -0.7 - 0.7 1.2 - 2.4 -0.8 - 0.8 1.6 - 2.8 1.6 - 2.8
No. of transistors 30 38 40 30 18 20
-3dB BW (MHz) 125 5 0.7 8 9.87 85.5
Normalized Gm 0.967 - 1.028 0.973 - 1.024 0.891 - 1.018 0.979 - 1.014 0.986 - 1.007 0.975 - 1.032
ǻIout with 20%
52.6 4.2 31 26.8 1.2 1.8
Vdd variation (%)

Table II. Post-layout-simulation of corner model

ġ TT FF FS SF SS
Tech. 0.35um CMOS 3.3V
Input Range (V) 1.6-2.8
-3dB BW (MHz) 85.58 108.85 70.09 76.61 65.58

Normalized Gm 0.983-1.008 0.962-1.013 0.959-1.011 0.981-1.007 0.97-1.01

ȋIout with 20%

1.82 2.12 1.96 2.39 1.93
Vdd variation (%)

6. Reference “Technique to improve linearity of transconductor

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