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IEEE PEDS 2015, Sydney, Australia

9–12 June 2015

FPGA Based Controller Drive of BLDC Motor

Using Digital PWM Technique
A. Tashakori, M. Hassanudeen and M. Ektesabi
Swinburne University of Technology, Melbourne, Australia
atashakoriabkenar@swin.edu.au

Abstract—Permanent magnet Brushless DC (BLDC) mo tors Synchronous AC Motors (PMSMs) and the other type with
have been extensively used in industrial, automotive and trapezoidal-wave back-EMF that are called Permanent Magnet
aerospace applications in the last decade. This paper presents a
Brushless DC (BLDC) Motors. BLDC motors produce larger
Field Programmable Gate Array (FPGA) based control drive for
BLDC motors using digital pulse width modulation (PWM) speed torque compared to PMSMs [7]; however they have more torque
controller. Presented BLDC motor commutation technique is ripples. Schematic diagram of a three phase BLDC motor drive
based on three inbuilt Hall Effect sensors. A novel algorithm is is shown in Fig. first.
proposed to implement a closed loop PWM speed controller
using FPGA for BLDC motors. Motor speed is controlled through
a predefined value or manually by the user. The proposed
method is modeled by Xilinx Integrated Software Environment (ISE)
Simulator and MATLAB/Simulink. Performance of the proposed
FPGA based control drive of BLDC motor is also evaluated
through experimental test setup. Simulation results and effec
tiveness of the proposed method are proved and validated by
experimental data.
I. INTRODUCTION
In specific applications such as Electric Vehicles (EVs),
electric motor has an essential effect on the overall per form of
the system. In such applications, efficient and reliable control
and operation of the overall systems are mainly dependent on
the selected motor type and its control drive.
Correct selection of electric motor drive is highly dependent on
application requirements. BLDC motor is a novel conventional
DC motor that has electronic commutation. They have been
widely used in industrial applications since 1970's. BLDC motors
are the main choice for in-wheel traction applications due to
their high efficiency and precise controllability [1].
Motor comparison studies also recommend BLDC motor as the Fig. 1. Schematic diagram of a three phase BLDC motor drive
best choice for high performance passenger EVs [2].
High efficiency, high speed ranges and high power/torque to Electronic commutation of the BLDC motor is based on
size ratio are main advantages of BLDC motors compared to position of permanent magnet rotor. Rotor position is either
other electric motor types [3]. BLDC motors need less main detected through inbuilt sensors or through sensorless algo
tenance due to the elimination of the mechanical commutators rithms by back-EMF zero crossing detection (ZCD). Position
and brushes. BLDC motors have faster dynamic response due detection sensors provide signals based on rotor position. Hall
to their low inertia (permanent magnet) rotor compared to Effect sensors are generally used for low resolution application
induction motors [4]. Low rotor losses and low acoustic noise and optical encoders are generally used for high resolution
are also other benefits of permanent magnet BLDC motors [5]. applications. Back-EMF sensing, back-EMF integration, free
BLDC motors are becoming increasingly popular in industrial, wheeling diode conduction of unexcited phase, flux link age
automotive and robotics application nowadays due to their based, third-harmonic analysis of back-EMF are various BLDC
immediate advantages. Therefore a developing low cost and motor sensorless control techniques [8]. Reduction of motor
efficient BLDC motor control drive by including new techniques, maintenance, extra wiring, temperature sensitivity, cost and
tools and circuits is in high demand [6]. complexity of motor construction are main advantages of
There are two types of permanent magnet synchronous sensorless control algorithms [9]. However control algorithms
motors based on their back Electro-Motive Force (EMF) wave complexity, starting and low speed commutation difficulties are
forms. Permanent magnet synchronous motors with sinusoidal main drawbacks of sensorless BLDC motor drives [10].
wave back-EMF that are well known as Permanent Magnet Therefore sensorless drives need a starting algorithm to speed

978-1-4799-4402-6/15/$31.00 c 2015 IEEE

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up the BLDC motor to the point that is able to sense back
EMF [11].
In this paper, BLDC motor commutation is based on three
inbuilt Hall Effect sensors. Hall Effect sensors are typically
mounted at the non-rotating end of BLDC motors in 120
electrical degree phase difference. Each sensor signal is high
for 180 electrical degrees according to rotor position during
one electrical rotation of the BLDC motor [10]. Commutation
points of the BLDC motor are determined by decoding the Hall
Effect signals. The six-step commutation technique is used to
switch the three phase Variable Source Inverter (VSI) drive of
BLDC motor in six switching sequences. In this technique only
two BLDC motor phases are energized at each switching
sequence while the remaining phase is inactive. Reversing of
the switching sequences changes the motor rotation direction.
Speed of the motor is directly proportional to the width of the
position sensor signals. Ideal line voltages, back-EMF voltages,
commutation signals, phase currents and six-step switching
pattern of the three phase BLDC motor are shown in Fig. 2.
Fig. 2. Ideal three phase BLDC motor signals and switching pattern
Digital Signal Processors (DSPs) were used to drive BLDC
motors. Modern control systems employ mi crocontrollers that
are basically an integration of DSP and powerful peripherals
in a complete package [12]. Microcon trollers are computing
systems that can perform loops, timings, conditionings and
complex math calculations. On the other hand FPGAs are
integrated circuits designed to be programmed using a
hardware description language (HDL). In comparison to
microcontrollers, FPGAs are generally used for simpler
operations however they have higher processing speed.
FPGAs also perform complex computations and calculations
faster than DSPs due to the inherent parallel architectures.
The FPGAs offer fast time to market, low design/manufacturing
cost and risk, extremely high processing performance and pro
grammability [5]. Another major advantage of using FPGAs is
the possibility to validate the designed control algorithm by
using simulation tools before hardware implementation.
Spartan-3E and the Basys 2 are FPGA boards are used to
implement the BLDC motor control in this study.
This paper presents a simple FPGA based control drive of
the BLDC motor using digital PWM technique. Details of the
proposed FPGA based speed controller is discussed in the
next section. Simulation and experimental results of the
developed FPGA based BLDC motor drive is presented and
discussed later on the following respectively. This study also
provides a platform for future development and implementation
of high performance and efficient FPGA based BLDC motor
drives for EV applications.
II. THE PROPOSED FPGA BASED PWM CONTROLLER
Hysteresis current control and PWM switching techniques
are the most widely used speed controllers in BLDC motor
drives [4]. In BLDC motors, speed is directly proportional to
applied line voltages. Variable DC link inverters and PWM
switching techniques are main methods to adjust voltage in
VSI drives. In the first method, VSI DC bus voltage is adjusted
to achieve desired speed where in PWM technique a duty
cycle controlled high frequency signal is logically added to
switching signals of the inverter to control the VSI average
output voltage. PWM signal can be applied to either upper
side switches, or lower side switches or all six switches of VSI
[3]. PWM signal is applied to upper side switches of the inverter
in the proposed method in this paper.
PWM signal can be generated digitally using processors or
through an analogue electronic circuit using comparators. High
noise susceptibility, temperature and voltage level sensitivity
of electronic circuit are main drawbacks of analogue methods;
however on the other hand flexibility, less environmental noise
susceptibility and ease of generation through programming by
microcontrollers or FPGAs are main advantages of digital
methods [13]. The counter-based, the delay-line and hybrid
delay-line/counter architectures are main PWM generation
topologies used in digital controllers [14]. The counter based
PWM generator topology is used in this paper due to its
simplicity and ease of implementation. In this method, the
PWM signal is set high as the counter is triggered by a clock
signal and is set low after number of predefined clock cycles.
Number of clock cycles is directly related to the required duty
cycle of the signal . Although counter-based method is simple
and compatible for FPGA based systems, but it needs a high
clock frequency that increases power dissipation [14].
A FPGA based PWM technique is reported by Sathyan et
al. two effective duty cycle values have been chosen to control
the speed of the BLDC motor [4]. Duty cycle of the PWM
signal is switched between high and low predefined values
based on speed error to adjust the BLDC motor speed.
In this paper, speed of the motor is sensed through Hall Effect
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signals and the proposed controller increases or said the
duty cycle of the PWM signal based on the speed error. Duty
cycle of the PWM signal is changed based on a predefined
value. One percent change of duty cycle value is chosen for
increase/decrease steps in this study. Stability of the BLDC
motor PWM speed controllers are analyzed and an ideal PWM
signal duty cycle is introduced according to the reference
speed and load torque that defines stable performance of the
BLDC motor [10]. The proposed FPGA based PWM controller
in this paper is able to determine the duty cycle value which
is near to the introduced one in [10], instead of changing the
duty cycle value between two possible states. Therefore
the proposed technique increases the efficiency of the BLDC
motor control drive.
III. SIMULATION RESULTS
The proposed BLDC motor controller, developed coding
and algorithms for the counter based PWM generation through
the FPGA boards are discussed and presented in this section.
The proposed BLDC motor PWM control algorithm is
modeled in Simulink using Simscape library. Data of the
experimental BLDC motor given in Table I is used in the motor
drive model. BLDC motor commutation is done according to
the inbuilt Hall Effect position sensors signals. A three phase
voltage source inverter is modeled using Metal Oxide Semi
conductor Field Effect Transistor (MOSFET) switches based
on experimental inverter drive. Six-step switching algorithm
is used to drive the BLDC motor VSI drive (refer to Fig.
2). Matlab codes have been written and embedded into the
model to generate a duty cycle controlled PWM signal, detect
motor speed from position sensors signals and implement the
proposed control algorithm. PWM signal is added to the upper
side switches of the inverter.
TABLE I
SPECIFICATION OF EXPERIMENTAL BLDC MOTOR
description Value Unit
DC voltage 24 DRAW
Rated speed 3000 RPM
0.28 Nm
Rated Torque
Phase resistance 2015 ohm
Phase inductance 4.60 mH
Intertia 4.43e-6 kg.m2
Torque constant 0.069 Nm/A
Poles 8 -
BLDC motor model is run at full speed (3000 RPM) under
no load Condition. Line voltage and corresponding Hall Effect
signal of the phase A are shown in Fig. 3. As can be seen
the presented simulation results are exactly as the same as the
presented ideal signals in Fig. 2.
Correct commutation of the BLDC motor, implemented
PWM speed control technique were main design objectives
of the FPGA based BLDC motor drive. The controller is
also designed to be able to start, stop (reset), change rotating
direction, increased and decrease of the motor speed
Fig. 3. Simulated BLDC motor line voltage and Hall Effect signal
by external switches on the FPGA board. Xilinx ISE is used
to generate control algorithm VHDL codes for Spartan 3E
and Basys 2 FPGA boards. Xilinx ISE software allows for
synthesis, simulation and implementation of the code generator
ated. Input and output signals of the developed BLDC motor
controller are shown in Table II.
TABLE II
I/O SIGNALS OF THE DEVELOPED BLDC MOTOR CONTROLLER
Signals I/O description
Clock Input It is derived from the 50MHz oscillator
available in the Spartan 3E board
Start Input It activates the motor controller (user control)
Reset Input It stops the motor controller (user control)
Position Inputs Three inbuilt Hall Effect sensors are used
sensors to obtain permanent magnet rotor position
Speed up Input It increases the motor speed (user control)
Speed down Input It said the motor speed (user control)
Direction Input It changes direction of rotation (user control)
Switching Outputs Six PWM switching signals to drive the
signals BLDC motor inverter
Every count is based on the system clock. The counter
system is used to step down the 50MHz FPGA board clock to
5 kHz for PWM switching frequency. Therefore, the counter
has been set to count 10000 times at each period. After each
period, the program checks the status of 'speed up' or 'speed
down' input signals/switches. If they have been activated, the
program first checks if there is a possibility to increase or
decrease PWM duty cycle and implements the appropriate
action. The counter system is used in order to generate duty
cycle controlled PWM signal. The program sets PWM signal
to logic one while the counter is counting up to the duty cycle
set value. The remaining time controller sets PWM signal to
logic zero. Therefore the desired duty cycle is achieved by
controlling the 'on time' of the PWM signal at each period.
Correct performance of the developed algorithm to generate
the desired duty cycle controlled PWM signal is the key
process in speed control of the BLDC motor.
Correct commutation signals of the BLDC motor is derived
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Fig. 4. Simulation results in the Xilinx software

from three inbuilt Hall Effect sensors signals that are inputs 3E and Basys 2 are programmed and used as the experimental
to the controller. A Finite State Machine (FSM) program is BLDC motor control drive. FPGA based experimental test rig
running in an infinite loop to commutate BLDC motor. of the BLDC motor is shown in Fig. 5.
Six states are defined based on input Hall Effect signals and
according to the six-step inverter switching topology.
The program detects the current rotor position and checks
the direction input signal at each state. Thus the program
chooses the next state to generate correct commutation
signals according to the current state and direction of rotation
input signal. The generated duty cycle controlled PWM signal
is logically added to the switching signals of the VSI upper
side switches.
The proposed control algorithm is coded using Xilinx ISE
and the simulation results are shown in Fig. 4. Commutation
signals are generated in a sequence for one electrical rotation
of the BLDC motor. As can be seen, six step inverter switch
ing topology is used to commutate the BLDC motor. The
generated PWM signal is only added to upper side switches
of the VSI. As shown in simulation results, inverter switches Fig. 5. BLDC motor experimental test rig
on the same leg are not activated at the same time to avoid
short circuit of the inverter DC link. Simulation results also The FPGA board gets the Hall Effect signals directly from
show that duty cycle of the generated PWM signal is correctly inbuilt sensors of the BLDC motor. Commutation of the motor
changing according to speed up and speed down input signals. mainly depends on correct reading of Hall Effect signals. In
Speed up and speed down signals can be controlled by user order to check and confirm not existing of any invalid Hall
to change the speed, however they vary by the program in effect sensors signals as well as commutation sequences
the closed loop control scheme. Simulation results prove states in advance and during the motor operation, LEDs on
correct performance of the proposed FPGA based control the FPGA board and Microchip LV development board are
drive of BLDC motor using digital PWM technique. used for visual observation. The FPGA controller produces
PWM and commutation signals at a voltage level of 3.3 volts.
IV. EXPERIMENTAL RESULT
Thus switching signals is pulled up to 5 volts that is required
The proposed control system is implemented to control a by the inverter driver. The PWM switching frequency is 5 kHz.
low voltage experimental BLDC motor. Experimental BLDC The experimental BLDC motor drive is tested under no
motor specifications are given in Table I. Inverter drive of the load condition at full speed (3300 RPM) and 1000 RPM to
Microchip Low Voltage (LV) development board consists of investigate performance of the proposed FPGA based control
three half-bridge gate drivers using MOSFETs are utilized to drive. Experimental BLDC motor line voltage and Hall Effect
drive of the experimental BLDC motor. FPGA boards Spartan signals at different speed operations are shown in Fig. 6. As

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can be seen in Fig. 6-a, PWM duty cycle value is 100% to
apply the maximum voltage to the BLDC motor for full speed
operation. Good agreements between the experimental results
shown in Fig. 6-a and simulation results in Fig. 3 validate
correct performance of the proposed control drive and the
BLDC motor simulation model. High frequency PWM switching
of the BLDC motor is shown in Fig. 6-b for BLDC motor
operation at 1000 RPM reference speed. Experimental results
prove correct performance of the proposed FPGA based
control drive of BLDC motor using digital PWM technique
speed controller.
Fig. 6. Experimental BLDC motor line voltage and Hall Effect signal
V. CONCLUSION
In this paper, a novel FPGA based BLDC motor drive using
digital PWM speed controller is presented. The presented
control algorithm is simple and excellent the performance of
the BLDC motor PWM speed controllers using FPGAs.
High frequency duty cycle controlled PWM signal is generated
using counters. The FPGA controller changes the duty cycle
of the PWM signal according to the speed error and based on
a constant value instead of switching between two predefined
high and low duty cycles. Therefore the proposed FPGA based
BLDC motor drive is more efficient and has more smooth
speed response. The proposed control algorithm is modeled
in ISE Simulator and Simulink. Effectiveness of the proposed
FPGA based BLDC motor drive is evaluated through exper
imental data. Good agreements between experimental data
and simulation results prove correct performance of the
proposed FPGA based drive of the BLDC motor using digital
PWM speed controller.
ACKNOWLEDGMENT
The authors would like to thank Swinburne University of
Technology, Malaysia Automotive Institute and the Common
wealth of Australia through the Automotive Australia 2020
CRC for providing funding for this research.
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