ETU 07322 - Digital Electronic Lab Manual

DAR ES SALAAM INSTITUTE OF TECHNOLOGY
DEPARTIMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING
DIGITAL ELECTRONICS LAB MANUAL
(ETU 07322)
FOR
SEMESTER I
Digital Electronics Lab Manual

Course Objectives:
This laboratory work enables students to get practical experience in design, realization and
verification of
 Demorgan‟s Theorem, SOP, POS forms
 Full/Parallel Adders, Subtractors and Magnitude Comparator
 Multiplexer and Demultiplexers using logic gates
 Encoders and Decoders
 Flip-Flops, Shift registers and Counters.
Course Outcomes:
 On the completion of this laboratory course, the students will be able to:
 Demonstrate the truth table of various expressions and combinational circuits using logic
gates.
 Design, test and evaluate various combinational circuits such as adders, subtractors,
comparators, multiplexers, demultiplexers, encoders and decoders.
 Construct flips-flops, counters and shift registers.

Contents
S/N NAME OF EXPERIMENT PAGE

No.
1 Experiment No: 1 Introduction to Digital Laboratory Equipments and IC’s 4
2 Experiment No: 2 To study basic gates (AND, OR, NOT, NAND, NOR, EX- 9
OR) and verify their truth tables.
3 Experiment No. 3 Implementation of the Given Boolean Function using 11
Logic Gates in Both Sop and Pos Forms.
4 Experiment No. 4 To Study the Half Adder 12
5 Experiment No. 5 To study about full adder and verify its observation data 14
6 Experiment No. 6 To realize the Full Subtractor circuit using basic logic gates 16
and verifies their truth tables
7 Experiment No. 7 To Design and Verify the Operation of Magnitude 18
Comparator
8 Experiment No. 8 To verify the truth table of 4- bit adder and 2's compliment 19
subtractor circuit using a 4-bit adder IC(7483)
9 Experiment No: 9 Implementation of 4x1 Multiplexer and 1x4 Demultiplexer 21
using Logic Gates
10 Experiment No. 10 To design and implement encoder and decoder using 23
logic gates and study of IC 7445 and IC 74147
11 Experiment No. 11 Verification of State Tables of RS, JK, T and D Flip- 26
Flops using NAND Gates
12 Experiment No. 12 Design, and Verify the 4-Bit Serial In - Parallel Out Shift 28
Registers
13 Experiment No: 13 Design and Verify the 4-Bit Synchronous Counter 30
14 Experiment No: 14 Design and Verify the 4-Bit Asynchronous Counter 32
15 To introduce the modeling, simulation and implementation of digital circuits 33
using Xilinx's FPGA VIVADO HLx Editions design tools.

Experiment No: 1
AIM:- Introduction to Digital Laboratory Equipments and IC’s.
THEORETICAL CONCEPT:-
The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken in the centre).
Each bus strip has two rows of contacts. Each of the two rows of contacts are a node. That is,
each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips
are used primarily for power supply connections, but are also used for any node requiring a large
number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each
side of the centre gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit components
into the contact receptacles and making connections with 22-26 gauge wire. There are wire
cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power
supply connections to separate bus strips.
Fig 1. The breadboard. The lines indicate connected holes.
The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated
circuits) used during the experiments. Incorrect connection of power to the ICs could result in
them exploding or becoming very hot - with the possible serious injury occurring to the
people working on the experiment! Ensure that the power supply polarity and all
components and connections are correct before switching on power.

Building the Circuit:
Throughout these experiments we will use TTL chips to build circuits. The steps
for wiring a circuit should be completed in the order described below:
1. Make sure the power is off before you build anything!
2. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus
strips on your breadboard.
3. Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on
the chip package)
4. Connect +5V and GND pins of each chip to the power and ground bus strips on
the breadboard.
5. Select a connection on your schematic and place a piece of hook-up wire between
corresponding pins of the chips on your breadboard. It is better to make the short
connections before the longer ones. Mark each connection on your schematic as you go, so
as not to try to make the same connection again at a later stage.
6. Get one of your group members to check the connections, before you turn the power on.
7. If an error is made and is not spotted before you turn the power on. Turn the power off
immediately before you begin to rewire the circuit.
8. At the end of the laboratory session, collect you hook-up wires, chips and all equipment and
return them to the demonstrator.
Tidy the area that you were working in and leave it in the same condition as it was before you
started.
Common Causes of Problems:
1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.
In all experiments, you will be expected to obtain all instruments, leads, components at the start
of the experiment and return them to their proper place after you have finished the experiment.
Please inform the demonstrator or technician if you locate faulty equipment. If you damage a
chip, inform a demonstrator, don't put it back in the box of chips for somebody else to use.
Example Implementation of a Logic Circuit:

Build a circuit to implement the Boolean function 𝐹 = ̅̅̅̅̅̅
𝐴̅ ∙ 𝐵̅ .
Quad 2 Input 7400 Hex 7404 Inverter

Fig 2. The complete designed and connected circuit
Sometimes the chip manufacturer may denote the first pin by a small indented circle above the
first pin of the chip. Place your chips in the same direction, to save confusion at a later stage.
Remember that you must connect power to the chips to get them to work.
Table 1: Useful IC Pin details

IC NUMBER Description of IC
7400 Quad 2 input NAND Gate
Quad 2 input NAND Gate (open
7401
collector)
7402 Quad 2 input NOR Gate
Quad 2 input NOR Gates (open
7403
collector)
7404 Hex Inverts
7421 Dual 4 input AND Gates
7430 8 input NAND Gate
7432 Quad 2 input OR Gates
7486 Quad 2 input EX-OR Gate
74107 Dual J-K Flip Flop
74174 Hex D Flip Flop
74173 Quad D Flip Flop
7474 Dual D Flip Flop
7475 Quad Bi-stable latch

IC NUMBER Description of IC
7400-NAND Gate 7402-NOR Gate
7404-NOT Gate 7408-AND Gate
4‐i/p NAND Gate 3‐i/p AND Gate

7432 OR Gate 7486 EX-OR
Fig. 3 Logic gate IC pin details
SPECIFICATION OF APPARATIUS USED:

LED, IC’s, Wires, 5 volt DC supply, Bread Board and digital IC’s.

Experiment No: 2
AIM: - To study basic gates (AND, OR, NOT, NAND, NOR, EX-OR) and verify their
truth tables.
AND Gate: The AND operation is defined as the output as (1) one if and only if all the inputs
are (1) one. 7408 is the two Inputs AND gate IC.A&B are the Input terminals & Y is the Output
terminal.
Y = A.B
OR Gate: The OR operation is defined as the output as (1) one if one or more than 0 inputs are
(1) one. 7432 is the two Input OR gate IC. A & B are the input terminals & Y is the Output
terminal.
Y=A+B
NOT GATE: The NOT gate is also known as Inverter. It has one input (A) & one output (Y). IC
No. is 7404. Its logical equation is,
Y = A NOT B, Y = A’
NAND GATE: The IC no. for NAND gate is 7400. The NOT-AND operation is known as
NAND operation. If all inputs are 1 then output produced is 0. NAND gate is inverted AND gate.
Y = (A. B)’
NOR GATE: The NOR gate has two or more input signals but only one output signal. IC 7402
is two inputs IC. The NOT- OR operation is known as NOR operation. If all the inputs are 0 then
the O/P is 1. NOR gate is inverted OR gate.
Y = (A+B)’
EX-OR GATE: The EX-OR gate can have two or more inputs but produce one output. 7486 is
two inputs IC. EX-OR gate is not a basic operation & can be performed using basic gates.
Y=AB
Fig. 4 Logic gate symbols

SPECIFICATION OF APPARATIUS USED:
Power Supply, Bread board, Connecting Leads, IC’s (7400, 7402, 7404, 7408, 7432, and 7486)
PROCEDURE:
1. Fix the IC’s on breadboard and gives the supply.
2. Connect the +ve terminal of supply to pin14 and -ve to pin7.
3. Give input at pin1, 2 and take output from pin3. It is same for all except NOT & NOR IC.
4. For NOR, pin1 is output and pin2 and 3 are inputs.
5. For NOT, pin1 is input and pin2 is output.
Note the values of output for different combination of inputs and draw the circuit.
PRECAUTIONS:
1. Make the connections according to the IC pin diagram
2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.
OBSERVATION DATA:
Table 1: Truth Table for AND, NAND, OR, NOR and EXOR
INPUTS OUTPUTS
A B 𝐴̅ 𝐵̅ 𝐴∙𝐵 ̅̅̅̅̅̅
𝐴∙𝐵 𝐴+𝐵 ̅̅̅̅̅̅̅̅
𝐴+𝐵 𝐴⊕𝐵
0 0 1 1 0 1 0 1 0
0 1 1 0 0 1 1 0 1
1 0 0 1 0 1 1 0 1
1 1 0 0 1 0 1 0 0
RESULT AND COMMENTS: We have learnt all the gates ICs according to the IC pin
diagram.

Experiment No. 3
AIM:- Implementation of the Given Boolean Function using Logic Gates in Both Sop and Pos
Forms.
Karnaugh maps are the most extensively used tool for simplification of Boolean functions. It is
mostly used for functions having up to six variables beyond which it becomes very cumbersome.
In an n-variable K-map there are 2ⁿ cells. Each cell corresponds to one of the combination of n
variable, since there are 2ⁿ combinations of n variables. Gray code has been used for the
identification of cells.
Example- SOP: 𝑌 = 𝐴𝐵 + 𝐴𝐶̅ + 𝐵𝐶

POS: 𝑌 = (𝐴 + 𝐵)(𝐴 + 𝐶)(𝐵 + 𝐶̅ )
SOP Form
POS Form
Fig. 5: SOP and POS circuit diagrams
SPECIFICATION OF APPARATUS USED:- Power Supply, Digital Trainer, IC’s

(7404, 7408,7432) Connecting leads.
PROCEDURE:
1. With given equation in SOP/POS forms first of all draw a K-map.
2. Enter the values of the O/P variable in each cell corresponding to its Min/Max term.
3. Make group of adjacent ones.
4. From group write the minimized equation.
5. Design the circuit of minimized equation and verify the truth table.
PRECAUTIONS:
1. Make the connections according to the IC pin diagram.
RESULT AND COMMENTS:-Implementation of SOP and POS form is obtained

with AND and OR gates.

Experiment No. 4
AIM:-To Study the Half Adder.
A half adder is a logic circuit that performs one-digit addition. The half adder is an example of a
simple, functional digital circuit built from logic gates. The half adder adds to one-bit binary
numbers (AB). The output is the sum of the two bits (S) and the carry (C).
EXPERIMENTAL SET UP:-
Fig. 6: Half Adder connection
SPECIFICATION OF APPARATUS USED:-

I.C’s 7486, 7408, wires, LED, Bread Board, 5 Volt supply.
PROCEDURE:-
1. Write OBSERVATION DATA for variables A, B. solves this OBSERVATION
DATA with the help of K-map.
2. Connect the circuit as shown and get the output of Sum and Carry separately.
3. Firstly, we will put IC’s.
4. Take input from Pin no. 1 and 2 of IC no.7486 and take output at Pin no.3.
5. Pin no.3 is connected with LED.
6. Short Pin no.1 of IC no.7486 to Pin no.2 of IC no.7408.
7. Similarly, short Pin no.1 of IC no.7486 to Pin no.1 of IC no.7408.
8. Take output at Pin no.3 of IC no.7408 and connect to LED.
9. Connect the Pin no. 14 to the 5 volt supply for all IC’s used in the circuit.
10. Connect Pin no. 7 to ground for all the IC’s
PRECAUTIONS:-
1. Supply should not exceed 5v.
2. Connections should be tight and easy to inspect.
3. Use L.E.D. with proper sign convention and check it before connecting in circuit.

OBSERVATION DATA:-
Table 2: Truth Table for Half Adder
INPUT OUTPUT
A B Sum Carry
1 1 0 1
1 0 1 0
0 1 1 0
0 0 0 0
RESULT AND COMMENTS:- the observation data of half adder verified.

Experiment No. 5
AIM:-To study about full adder and verify its observation data.
A half adder has only two inputs and there is no provision to add a carry coming from the lower
order bits when multi-bit addition is performed. For this purpose, a third input terminal is added
and this circuit is used to add An, Bn and Cn-1 where An and Bn are the nth order bits of the
numbers A and B respectively and Cn-1 is the carry generated from the addition of (n-1)th order
bits. This circuit is referred to as FULL-ADDER.
EXPERIMENTAL SET UP:-
(a)
(b)
Fig. 7: Full Adder, (a) Sum and (b) Carry

IC-(7486, 7408, 7432), Connecting wires, LED, Bread board, Cutter, 5v supply

PROCEDURE:
1. Write the OBSERVATION DATA for variables An, Bn and Cn-1.
2. OBSERVATION DATA was solved with the help of K-map.
3. Circuit was connected and the output of sum and carry was got separately.
4. Connect the pin no.14 to 5v supply of all IC’s used in circuit.
5. Pin no. 7 will be grounded of all IC’s.
PRECAUTIONS:-
3. Use L.E.D. with proper sign convention and check it before connecting in circuit
OBSERVATION DATA:
Table 3: Truth Table for Full Adder
Input Output
An Bn Cn-1 Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RESULT AND COMMENTS: - the observation data of full adder is verified.

Experiment No. 6
AIM:-To realize the Full Subtractor circuit using basic logic gates and verifies their truth tables.
Full Subtractor is a logical circuit, which performs Subtraction of three bits and provides an
output with a Difference and Borrow, It can be built using 2-half Subtractor and an OR gate.
EXPERIMENTAL SET UP: - Full Subtractor
Fig. 8 Realization of full Subtractor using basic and EXOR gates

Power Supply, Bread board, Connecting leads, and IC’s (7404, 7408, and 7432).
PROCEDURE:
1. Write the OBSERVATION DATA for variables An, Bn and Bn-i.
2. OBSERVATION DATA was solved with the help of K-map.
3. Circuit was connected and the output of Dn and Bn-o was got separately.
4. Connect the pin no.14 to 5v supply of all IC’s used in circuit.
5. Pin no. 7 will be grounded of all IC’s.
PRECAUTIONS:-
3. Use L.E.D. with proper sign convention and check it before connecting in circuit
OBSERVATION DATA:
Table 4: Truth Table for a Full Subtractor
Input Output
An Bn Bn-i Dn Bn-o
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0

Input Output
An Bn Bn-i Dn Bn-o
1 1 1 1 1
RESULT AND COMMENTS: - the observation data of full Subtractor is verified.

Experiment No. 7
AIM:-To Design and Verify the Operation of Magnitude Comparator
Comparator compares the value of signal at the input. It can be designed to compare many bits.
The adjoining figure shows the block diagram of comparator. Here it receives to two 2-bit
numbers at the input and the comparison is at the output.
EXPERIMENTAL SET UP: - Comparator
Fig. 9: Magnitude comparator circuit

Power Supply, Bread board, Connecting leads, and IC’s (7404, 7408, and 4077).
PROCEDURE:-
1. Make the connections according to the circuit diagram.
2. The output is high if both the inputs are equal.
3. Verify the truth table for different values.
PRECAUTIONS:-
3. The Vcc and ground should be applied carefully at the specified pin only
OBSERVATION DATA:-
Table 5: Truth Table for one bit Comparator
Input Output
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
RESULT AND COMMENTS:- The comparator is designed and verified

Experiment No. 8
AIM:- To verify the truth table of 4- bit adder and 2's compliment subtractor circuit using a 4-bit
adder IC(7483)
IC 7483 is a 4 bit adder. In binary, subtraction can be performed by using 2's complement
method. In this method negative number is converted into its 2's complement and it is added to
the other number. The result of this addition is the subtraction of origin numbers.
If we modify the adder circuit, such that 2's complement and simple representation are presented,
we can perform addition subtraction as required. EXOR gate is used as a controlled
inverter/buffer for this purpose. Use it as buffer for addition and inverter for subtraction.
EXPERIMENTAL SET UP: -
Fig. 13 4- bit adder and 2's compliment subtractor circuit using a 4-bit
adder IC(7483)
SPECIFICATION OF APPARATUS USED:- IC’s 7483, 7486, Bread board and Connecting
leads.
PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply Vcc and ground signal to every IC.
3. Observe the input and output according to the truth table.

PRECAUTIONS:
OBSERVATION DATA:-
Table 9: Truth table for each stage of a 4-bit parallel adder.
Cn-1 An Bn Sn Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RESULT AND COMMENTS::

The truth table of 4- bit adder and 2's compliment subtractor circuit using a 4-bit adder IC(7483)
are verified

Experiment No: 9
AIM:- Implementation of 4x1 Multiplexer and 1x4 Demultiplexer using Logic Gates.
MULTIPLEXER: Multiplexer generally means many into one. A multiplexer is a circuit with
many Inputs but only one output. By applying control signals we can steer any input to the
output .The fig. (1) Shows the general idea. The circuit has n-input signal, control signal and one
output signal. Where 2n = m. One of the popular multiplexer is the 4 to 1 multiplexer, which has
4 input bits, 2 control bits and 1 output bit.
DEMULTIPLEXER: Demultiplexer means generally one into many. A demultiplexer is a logic

circuit with one input and many outputs. By applying control signals, we can steer the input
signal to one of the output lines. The circuit has one input signal, m control signal and n output
signals. Where 2n = m. It functions as an electronic switch to route an incoming data signal to
one of several outputs.
4 X1 MUX 1 X 4 DEMUX
(a) (b)
Fig. 10: Circuit diagram using logic gates (a) Multiplexer and (b) Demultiplexer

Power Supply, Digital Trainer, Connecting Leads, IC’s7 4153 (4x1 multiplexer).
PROCEDURE:

PRECAUTIONS:
OBSERVATION DATA:
Table 6: Truth table for (a) Multiplexer and (b) Demultiplexer
(a) (b)
Select line Output Output select Output
line Selected
S1 S0 Data S1 S0 Data
0 0 I0 0 0 O0
0 1 I1 0 1 O1
1 0 I2 1 0 O2
1 1 I3 1 1 O3
RESULT AND COMMENTS:

Verify the truth table of multiplexer and demultiplexer for various inputs.

Experiment No. 10
AIM:- To design and implement encoder and decoder using logic gates and study of IC 7445 and
IC 74147.
ENCODER:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n
input lines and n output lines. In encoder the output lines generates the binary code
corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal
digit and three output that generate the corresponding binary code. In encoder it is assumed that
only one input has a value of one at any given time otherwise the circuit is meaningless. It has an
ambiguila that when all inputs are zero the outputs are zero. The zero outputs can also be
generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into coded
output where input and output codes are different. The input code generally has fewer bits than
the output code. Each input code word produces a different output code word i.e., there is one to
one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded
information is present as n input producing 2n possible outputs. 2n output values are from 0
through output 2n-1.
Fig. 11: Logic diagram for Encoder

Table 7:Truth Table for Encoder
Input Output
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
Fig. 12: Logic diagram for Decoder
Table 8: Truth Table for Decoder

Input Output
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
PROCEDURE:
1. Connect the circuit as shown in figure 11 and 12.
PRECAUTIONS:

RESULT AND COMMENTS::

Thus the design and implementation of encoder and decoder using logic gates and study of IC
7445 and IC 74147 were done.

Experiment No. 11
AIM:- Verification of State Tables of RS, JK, T and D Flip-Flops using NAND Gates
RS FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. When inputs R=0 and
S=0 then O/P remains unchanged .When inputs R=0vand S=1 the flip-flop is switches to the
stable state where O/P is 1i.e. SET. The input condition is R=1 and S=0 the flip-flop is switched
to the stable state where O/P is 0i.e. RESET. The input condition is R=1 and S=1 the flip-flop is
switched to the stable state where O/P is forbidden.
JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal element to use. The
variable J and K are called control I/Ps because they determine what the flip-flop does when a
positive edge arrives. When J and K are both0s, both AND gates are disabled and Q retains its
last value.
D FLIP–FLOP: This kind of flip-flop prevents the value of D from reaching the Q output until
clock pulses occur. When the clock is low, both AND gates are disabled D can change value
without affecting the value of Q. On the other hand, when the clock is high, both AND gates are
enabled. In this case, Q is forced to equal the value of D. When the clock again goes low, Q
retains or stores the last value of D. a D flip-flop is a bistable circuit whose D input is transferred
to the output after a clock pulse is received.
T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock edge, giving an
output which is half the frequency of the signal to the T input. It is useful for constructing binary
counters, frequency dividers, and general binary addition devices. It can be made from a JK flip-
flop by tying both of its inputs high.
SR Flip-Flop D Flip-Flop
JK Flip-Flop D Flip-Flop
Fig. 14 flip-flop circuit diagrams

SPECIFICATION OF APPARATUS USED:- IC’ S 7400, 7402, Bread board and Connecting
leads.
PROCEDURE:
PRECAUTIONS:
OBSERVATION DATA:-
Table 10: Truth Table for Flip-Flops
SR FLIP FLOP:-
CLOCK S R Q
1 0 0 NOCHANGE
1 0 1 0
1 1 0 1
1 1 1 ? UNDEFINED
D FLIP FLOP:-
CLOCK D Q
1 0 0
1 1 1
JK FLIP FLOP:-
CLOCK J K Q
1 0 0 NOCHANGE
1 0 1 0
1 1 0 1
1 1 1 Q’
T FLIP FLOP:-
CLOCK T Q
1 0 NOCHANGE
1 1 Q’
RESULT AND COMMENT:-Truth table is verified on bread board.

Experiment No. 12
AIM: – Design, and Verify the 4-Bit Serial In - Parallel Out Shift Registers.
Shift register is used to shift the data there 4 type of shift register: SISO, SIPO, PISO, PIPO. The
difference is the way in which the data bits are taken out of the register. Once the data are stored,
each bit appears on its respective output line, and all bits are available simultaneously. A
construction of a four-bit serial in - parallel out register is shown below
Fig. 15 4-Bit Serial In - Parallel Out Shift Registers

Digital trainer kit and 4 JK flip flop each IC 7476 (i.e dual JK flip flop) and two AND gates IC
7408.
OBSERVATION DATA:-
Table 11: Truth Table for SIPO Shift Register
Clear FF0 FF1 FF2 FF3
1001 0 0 0 0
1 0 0 0
0 1 0 0
0 0 1 0
1 0 0 1
PROCEDURE:
1. Make the connections as per the logic diagram.
2. Connect +5v and ground according to pin configuration.
3. Apply diff combinations of inputs to the input terminals.
4. Note output for summation.
5. Verify the truth table.
PRECAUTIONS:

RESULT AND COMMENT: 4-bit Serial In – Parallel Out Shift Registers studied and
verified.

Experiment No: 13
AIM:–Design and Verify the 4-Bit Synchronous Counter
Counter is a circuit which cycle through state sequence. Two types of counter, Synchronous
counter (e.g. parallel) and Asynchronous counter (e.g. ripple). In Ripple counter same flip-flop
output to be used as clock signal source for other flip-flop. Synchronous counter use the same
clock signal for all flip-flop.
Fig. 16: 4-bit synchronous counter
SPECIFICATION OF APPARATUS USED:- Power supply, bread board and 4 JK flip flop
each IC7476 (i.e dual JK flip flop) and two AND gates IC7408.
OBSERVATION DATA:
Table 12: Truth Table for 4-bit synchronous counter
States Count
O4 O3 O2 O1
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10

States Count
O4 O3 O2 O1
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
PROCEDURE:
PRECAUTIONS:
RESULT AND COMMENT: 4-bit synchronous counter studied and verified.

Experiment No: 14
AIM: – Design and Verify the 4-Bit Asynchronous Counter.
Counter is a circuit which cycle through state sequence. Two types of counter, Synchronous
counter (e.g. parallel) and Asynchronous counter (e.g. ripple). In Ripple counter same flip-flop
output to be used as clock signal source for other flip-flop. Synchronous counter use the same
clock signal for all flip-flop.

4-Bit Asynchronous counter
Fig. 17 4-Bit Asynchronous counter

Digital trainer kit and 4 JK flip flop each IC 7476 (i.e dual JK flip flop) and two AND gates IC
7408.
PROCEDURE:
PRECAUTIONS:
RESULT AND COMMENT: 4-bit asynchronous counter studied and verified.

Experiment No: 15
AIM: – To introduce the modeling, simulation and implementation of digital circuits using
Xilinx's FPGA VIVADO HLx Editions design tools.
Equipment:- The Xilinx's FPGA VIVADO HLx Editions design tools are available in the
laboratory. These tools can also be downloaded from Xilinx's web site at www.xilinx.com. The
WebPack version of this tool that we use for the laboratory experiments are located under the
support download section at the related website
(https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloa dNav/vivado-
design-tools/2017-4.html). Please take note that the file download size exceeds 1 GB and also
during the installation process updates may have to be installed. It can take you up to a few hours
to download and install the software on your computer. The user does not need to have the
BASYS development board interface to the computer to design and simulate an FPGA.

ETU 07322 - Digital Electronic Lab Manual

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DAR ES SALAAM INSTITUTE OF TECHNOLOGY

DEPARTIMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING

DIGITAL ELECTRONICS LAB MANUAL

Digital Electronics Lab Manual

Digital Electronics Lab Manual

S/N NAME OF EXPERIMENT PAGE

Digital Electronics Lab Manual

Fig 1. The breadboard. The lines indicate connected holes.

Digital Electronics Lab Manual

Example Implementation of a Logic Circuit:

Quad 2 Input 7400 Hex 7404 Inverter

Digital Electronics Lab Manual

Table 1: Useful IC Pin details

Digital Electronics Lab Manual

7400-NAND Gate 7402-NOR Gate

7404-NOT Gate 7408-AND Gate

4‐i/p NAND Gate 3‐i/p AND Gate

Digital Electronics Lab Manual

Fig. 3 Logic gate IC pin details

SPECIFICATION OF APPARATIUS USED:

Digital Electronics Lab Manual

Fig. 4 Logic gate symbols

Digital Electronics Lab Manual

Digital Electronics Lab Manual

Example- SOP: 𝑌 = 𝐴𝐵 + 𝐴𝐶̅ + 𝐵𝐶

Fig. 5: SOP and POS circuit diagrams

SPECIFICATION OF APPARATUS USED:- Power Supply, Digital Trainer, IC’s

RESULT AND COMMENTS:-Implementation of SOP and POS form is obtained

Digital Electronics Lab Manual

EXPERIMENTAL SET UP:-

Fig. 6: Half Adder connection

SPECIFICATION OF APPARATUS USED:-

Digital Electronics Lab Manual

RESULT AND COMMENTS:- the observation data of half adder verified.

Digital Electronics Lab Manual

EXPERIMENTAL SET UP:-

SPECIFICATION OF APPARATUS USED:-

Digital Electronics Lab Manual

RESULT AND COMMENTS: - the observation data of full adder is verified.

Digital Electronics Lab Manual

EXPERIMENTAL SET UP: - Full Subtractor

Fig. 8 Realization of full Subtractor using basic and EXOR gates

SPECIFICATION OF APPARATUS USED:-

Digital Electronics Lab Manual

RESULT AND COMMENTS: - the observation data of full Subtractor is verified.

Digital Electronics Lab Manual

EXPERIMENTAL SET UP: - Comparator

Fig. 9: Magnitude comparator circuit

SPECIFICATION OF APPARATUS USED:-

RESULT AND COMMENTS:- The comparator is designed and verified

Digital Electronics Lab Manual

EXPERIMENTAL SET UP: -

Digital Electronics Lab Manual

RESULT AND COMMENTS::

Digital Electronics Lab Manual

DEMULTIPLEXER: Demultiplexer means generally one into many. A demultiplexer is a logic

EXPERIMENTAL SET UP: -

SPECIFICATION OF APPARATUS USED:-

Digital Electronics Lab Manual

RESULT AND COMMENTS:

Digital Electronics Lab Manual

EXPERIMENTAL SET UP: -