MECHATRONI

CS–UNI
T2
MI
CROPROCESSOR8085ANDMI
CRO–CONTROLLER8251

MI
CROPROCESSOR MI
CROCONTROLLER

Appli
cat
ions– PC,l aptopsf orgaming, Appl
icati
ons – Di
git
alcamer a,washing
photoediti
ng,vi
deo,document at
i f
ons(or machine,Microwave oven,remote car
taskswhicharenotpredef
ined). l
ocks(fordoi
ngpre-
definedt
asks)
Al
lmemoryelements,ser
iali
nterf
aces, Allelement
sar
eint
egr
atedonasi
ngl
e
I
/Opor
tsar
econnect
edseparat
ely. chip.

Cl
ockspeed–1GHzt
o4GHz Cl
ockspeed–1MHzt
o300MHz

RAM –512MBt
o32GB RAM -
2KBt
o256KB

ROM (
Har
dDi
sk)–128GBt
o2TB Fl
ash/
Progr
ammedMemor
y–32KBt
o2
MB.

ARCHI
TECTUREOF8085
Intel8085,an8bi tNMOSmi croprocessori
sf abri
cat
edonasi
ngl
eLSI(
Lar
ge
Scal
eIntegrat
ion)chipoper
ateson
 +5Vol tDC
 Clockspeed–3MHz
 Gener alpur
pose8bi tmi
croprocessor
 Capabl eofaddr
essingupto64Kby tesi
.e.2^16

Themainfuncti
onalcomponent
sof8085Ami
cropr
ocessorar
easgi
venbel
ow:
(i
)Regi
sterSect
ion
(i
i
)Arithmet i
candLogi cUni t
(i
i
i)TimingandCont rolSection
(i
v)InterruptControl
(v
)SerialInput/Out putCont rol
(i
)RegisterSection–8t ypes
The 8085 mi croprocessorcont ains ei
ghtaddressabl
e 8-bi
tr egi
ster
s namely–
Accumul ator,
Flagregister(Fli
pFlop),
and6gener
alpurposeregi
stersB,C,D,
E,H,L.

B,C,D,E,H andLgener alpurposeregist

erscanstore/copy8-bitdata.These
r
egi
stercanbeusedf or16bi
toperat
ionsbycombi nat
ionoftwoi .
e.B-
C, D-E,H-L.Mor e
t
hegeneralpurposer
egist
ermorewillt
heflexi
bil
it
yandeaseinpr ogr
ammi ng.Howev er
t
heywill
usemor espaceinsi
li
conchip.
CounterandSt
ackpoint
eralsocomesunderr egi
sterwhichare16bi tr
egister
s.

Accumul ator(A)–Theaccumulatorisan8-bitr
egist
ert
hatisapartofar
it
hmeti
c/l
ogic
uni
t( ALU).Thisregi
steri
susedtostore8-bi
tdataandtoperfor
m ar
it
hmeti
candlogi
cal
operati
ons.
Ther esultofanoper at
ionisstored i
nt heaccumulator
.Theaccumul at
ori
sal so
i
dentifedasr
i egist
erA.

FlagRegi ster–Toexecut ei nstruct ioni nt hemi cropr ocessor .Outof8bi tsintheflag,5

bitscont ainsst atusinformat i
onr egar dingset /resetaccor di
ngt ot hecondi ti
onoft he
resultinaccumul atorandot herr egi st ers.
a)Si gnFlag–Set s1i fther esul toft heoper ationi snegat iveandS=0i fitis
positive
b)Zer oFlag–Whent heoper ationoft hei nstruct i
oni szero,thisflagwi l
lset
.(i.
e.)
Z=1i ft her esul tiszer o,andZ=0i fther esul
ti snotzer o.
c)Car ryFlag-Thecar r
yf lagi ssett o1,i ft her eexistacar ry(orborrow)tot he
highestor derbi t( non-exi
st ent9t h positi
on)asa r esultoft he
executionofaddi ti
onorsubt ractioni nstructi
ons.
d)Par i
tyFl ag–P=1, ifther esul thasev ennumberof1s, andP=0, iftheresult
hasoddnumberof1s.
e)Auxi l
iaryFlag–Thi si sanewf lagin8085mi croprocessor .Thisfl
ag( AC)isset
to1,ifther eisanov erf
lowatbi t3oft heaccumul ator.
These f l
ags hav e crit
icali mpor tance i n the deci si
on-maki ng pr ocess of t he
mi croprocessor .Thecondi ti
ons( setorr eset)oft hef lagsar et est
ed throught he
sof t
war einstructions
Pr
ogr
am Count
er–16bi
tspeci
alpur
poser
egi
ster
Thepr ogram counterisa16bi tregist
er.Iti
susedt osend16bi taddresstof etchthe
i
nst r
ucti
onf rom thememor y.Itactsasapoi nterwhi chindicat
est headdr essoft he
nextinstructi
ont obef etchedandexecut ed.Thepr ogram counteri
supdat edaf teran
i
nst r
ucti
onhasbeenf etchedbyt heprocessor.Ifani nstr
ucti
onisoneby t
ei nstr
uction,
thenthepr ogram counterwillbeupdat edbyone( i
.e.PC=PC+1) .Si
mi l
arl
y,f
ort woand
threebyteinstruct
ions,thepr ogram counterwillbeupdat edbyt wo( i
.e.PC=PC+2)or
three(i
.e.PC=PC+3)l ocationsr espect
ively
.

StackPointer–16bi tspecialpurposeregi ster

Thest ackisanar ea/ partofRAM ( random accessmemor yorr ead/wr i
tememor y)in
whicht emporar
yi nformat i
oni sstored.ItisstoredonFi r
st-
In-
Last -
Out( FILO)basis.An
addressint heRAM ar eaisassignedt ot hestackpointerwheret hefir
sti nformati
oni s
storedasthef i
rststackent ry.Stackpoint ermaintai
nstheaddr essoft hel astbyt
et hat
i
sent eredintostack.Eacht i
mewhent hedat aisloadedintost ack,St
ackpoi nt
erget s
decremented.Conv erselyitisincrementedwhendat aisretr
iev
edf r
om stack.

(ii
)ALU–Ar ithmet icLogi calUnit
Thear i
thmeticandl ogicalunit(ALU)basicallyconsi
stsofaccumul ator(A),
flagregist
er(F)
andat empor aryr egister(whichi sinaccessiblebyt hepr ogrammeroruser )
.Thi suni t
carriesoutt hear it
hmet i
candl ogi
ccal culati
onsoft hedat ast oredi ngeneralpur pose
registersori n memor yl ocati
ons.The ar ithmeticoperati
onsar e ADD,SUB,compar e,
i
ncr ement s,decrement sandcompl ement setc.;whi
lelogi
caloper ati
onsar eAND,OR,XOR
andRot at
e.Ther esultoft heseoperati
onscoul dbepl acedintheaccumul at
ororel sewhere
throught hei nternalbus.Fort heseoperat i
ons,ALUr eceiv
est hecont r
olsignal
sf rom the
ti
mi ngandcont rolunit.

(i
i
i)Timi ngandCont rolUni
t– Ithassect
ions– a)I
nst
ruct
ionRegi
sterandDecoderb)
Controlsignal
s
a)Instr
uct i
onRegi
sterandDecoder

TheCPUfetchesani
nstr
ucti
onfrom t
hememor yfori
tsexecut
ion.Thisi
nstr
ucti
oncan
beof1-
3
byt
elong. Theinst
ruct
ionregi
sterrecei
vesopcodewhichisi nst
ruct
ion(nat
ureof
oper
ati
ontodo)andtr
ansfer
stothedecoder.

Thedecoderdecodest
heopcodeanddi
rect
sthecont
rol
uni
ttopr
oducet
henecessar
y
cont
rolsi
gnal
s

b)Cont
rol
Signal
-CPUwor
ksbyt
hecont
rol
signal

(
i)X1,
X2 -Twopi
nsX1andX2ar
epr
ovi
dedt
obeext
ernal
l
yconnect
edt
oaquar
tzcr
yst
al.

(i
i
)CLKOut–Theout putcl
ockf
requencyisgi
venbyCLKoutwhichisof3.072MHz,
butthi
s
i
shal ft
hefrequencyofthequart
zcrystal(
6.144MHz)usedi
nt heprocessor
.Theclock
peri
odis320ns.

(i
ii
)ALE(
Addr
essLat
chEnabl
e)-Thesear
e16bi
taddr
essbusdi
vi
dedi
nto–MSB–A7-A15
andLSB–AD0–AD7.
The16bi taddressbusi sbasi
callydivi
dedintotwosets.Themostsi gni
fi
cantbit
sA7-A15
oftheaddressbusar eusedseparatelyandtheleastsi
gnifi
cantbit
softheaddressAD0-
AD7ar eti
memul ti
plexedwit
ht hebitsofbidi
recti
onaldatabus(D0-D7).TheAD0-AD7bus
servesthedual pur
poseast heycanbeusedasl ow-orderaddressbusaswellas
Bidi
rect
ionaldatabusatdi f
ferentti
mes.

Theyactasbothaddr essbusduri
ngthe1sthalfcy
cleoft ockandbi
hecl -
dir
ecti
onaldata
busduri
ngthe2nd hal
fofthecl
ockcycle.Duri
ngthefir
stcl
ockcycl
eoft hemachinecycle
ALE i
shighwhichenabl esthelower8-bitoftheaddresstobelatchedeitherint
ot he
memoryorexter
nal l
atch.
(
iv)RD (
Read)Si
gnal
–Toenabl
einput
/out
putr
eadsi
gnal

(
v)RW (
Wri
te)Si
gnal
-si
gnal
isusedt
owr
it
etot
hememor
yori
nput/out
putdev
ices.

(v
i)IO/M (
InputOut
put/Memor y)-Thi
ssi
gnal
IO/
M di
sti
ngui
shest
hatt
headdr
essand
dataismeantforei
therI
/Odev
icesormemory.

Whent
hesignali
shigh(1)–mi cropr
ocessorwi
l
lcommunicat
etot
heI
/Odev
ices
Wheni
tisl
ow( 0)-micr
oprocessorwil
lcommunicat
etot
hememory

(
vii
)St
atusSignals(S0,S1)-Thestat
ussignal
s(S0,
S1)alongwi
thIO/M signali
ndi
catethe
t
ypeofmachinecy cl
einpr ogr
ess.Thetypeofmachinecycl
ear
eopcodef etchcy
cle,
memoryreadcycle,
memorywrit
ecy cl
e,I/OreadcycleorI/
Owr i
tecycl
e.
MachineCycle I
O/M S1 S0

Opcodef
etchCy
cle 0 1 1
Memor
yReadCy
cle 0 1 0
Memor
yWr
it
eCy
cle 0 0 1
I
/OReadCy
cle 1 1 0
I
/OWr
it
eCy
cle 1 0 1
I
NTRAcknowl
edge 1 1 1
Hal
t Hi
-Z 0 0

(v
ii)HOLDandHLDA–Hol dandHol dacknowledgeisusedforDMA(Di
rectMemory
Access)oper at
ions.Datat
ransferoccur
sbetweenI/Oandmemor ydevi
cesthr
ough
microprocessor.Asweknow, thedatatransf
ersbetweeni/
oandmemor ywi
thout
microprocessorinvol
vementi
sknownasDMA.Thi sisforl
imi
ti
ngthet
imeandto
processlargeamountofdata.

Whenevert
heHOLDsi
gnali
shigh,t
heCPUwaitsandDMAoperat
ionswi
l
lst
art
i
ndi
catedbyHLDA.Af
teri
tcomplet
esthei
nst
ruct
iont
heCPUresumes

(
vii
i
)READYsignal–Someperi
pheral
dev
iceswor
kssl
owerthant
hemicropr
ocessor
.
I
nordert
osynchroni
zet
hespeed,t
heCPUslowsdowntot
hespeedofperi
pher
al
devicebyusingREADYsignal
.IfREADYi
shi
gh,
theper
ipher
aldev
icei
sreadyandt
he
processorcomplet
ethedatatr
ansfer
.

(i
x)RESETOUT–CPUwil
lresett
heprogr
am count
er,
regi
sterandot
herci
rcui
ts.
RESETIN–Thedat
apr
ocessingwil
lbegi
nifi
tishi
ghandRESETOUTgoesl ow.

(iv)Interr
uptCont r
oll
er–I NTR,RST5. 5,
RST6. 5,RST7.5,andTRAP
Somet imesi ti
snecessar ytoi
nterrupttheexecutionofthemainprogram.Thi sinter
rupti
s
obt ai
nedbyt heI/Odev i
ces.Aft
erthewor koftheI/Odeviceiscompleteitret
urnstowhatit
wasdoi ngear l
ier
.
TRAP–Hi ghpr i
ori
tyinterr
uptsignal Non-maskabl e(Forprocessinginterr
upt
i
mmedi ately)
INTR( i
nterruptrequest)–Pr ocessort emporari
lystopswhatitwasdoi ngandattendsto
theI /Odev i
cebyr eceivi
ngINTRsi gnal
INTA–i sani nter
ruptacknowledgesi gnalwhichissentbythemi cr
oprocessorafterI
NTR
signal i
srecei v
ed.

TRAP( PinNo. 6) IPr iorit

y
RST7. 5( PinNo.7) I IPr iorit
y
RST6. 5( PinNo.8) I IIPr iori
ty
RST5. 5( PinNo.9) I VPr iori
ty
INTR ( Pi nNo.10) V Pr iori
ty
(v)Ser
ialI
nput/Out putControl l
er(SID/ SOD)–
SID–Thi sterminalwil
l r
eceivesser ialdat astr eam f rom aninputdev
ice,
thecontr
oluni
t
conver
tsser i
aldatastream int oparall
el databef or
ei ti
susedbyt hecomputer
.Af t
er
conver
sion,thi
s8bi tparall
el datastor edi naccumul ator
SOD–SODt erminaloutputst he8bi tpar all
el dat aav ail
abl
eintheaccumulat
orint
oseri
al
formtotheper i
pheraldeviceconnect edt ot hecomput er.

2.PINCONFI GURATI ON–( 40–PI NS)

64000=2^ 16–i taccess64KB
Multipl
exi
ngAD0- AD7–Ther earet hreetypesofbuses–Dat abus,Addr essbus
(memor ycanbeaccessed) ,
address-databuses
PIN1&2–X1andX2( TimingSignal)
TheseX1andX2pi nsar etobeconnect edtoanext ernalquar
tzcryst
al,L-CorR- C
networkwhi chdrivestheinternalclockgener ator
.Theclocksignalofappr opr
iate
fr
equencyi sdeterminedwhenaquar tzcrystalisconnectedtotheon-chiposci l
l
ator
shown.Theci rcuitproducestwocl ocksignalsΦ1( CLK)andΦ2( CLK)toderivetheint
ernal
ci
rcuitoft
hemi croprocessor.A6.25MHzQuar tzcr
ystali
susedtoprovide3.125MHz
i
nternalcl
ockfrequency .
PIN3–ThisisRESETOUTsignal
,whi
chi
ndicat
esthatCPUisbeingreset
.Wheni
tishi
gh,
syst
em i
sreset
.WhentheRESETOUTsignalgoesl
ow,theprocessi
ngofmicr
opr
ocessor
begi
ns.

PIN4, PIN5–Pi nNos.4and5i ndicat

eSOD( Seri
alOutData)andSID( Ser
ialI
nDat a)
terminal
sr especti
vel
y.Thesepinsareassoci
atedwithSeri
alInput
/Outputcontroluni
tfor
8085mi croprocessor.Asalr
eadydiscussedthesepi
nsareusedf ort
heser i
aldata
transmissi
on.TheSODout putpincandeli
veraseri
aldatastr
eam toaper i
pheraldevi
ce.
PIN6-11
Theinterr
uptcontr
ol unitofthemicr
opr
ocessorcont
ainsthesepi
ns.ThePins6to11ar
e
rest
artint
errupt
snamedas:
TRAP( PinNo.6)IPriori
ty
RST7.5( Pi
nNo.7)I IPr i
orit
y
RST6.5( Pi
nNo.8)I IIPriori
ty
RST5.5( Pi
nNo.9)I VPr iori
ty
I
NTR( PinNo.10)VPr iorit
y
TheTRAP( non-
maskabl e)hasthehi
ghestpr
ior
it
yandI NTRhasthelowestpri
ori
ty.

I
NTA(pi
n11)-I
sanInter
ruptAcknowl I
edge(NTA)si
gnal.Al
ow(l
ogic0)tothi
spini
ndi
cat
e
t
hatt
hemicr
opr
ocessorhasacknowledgedt
herequestf
rom t
heper
ipher
aldevi
ce.

TRAP,RST7.5,RST6.5andRST5. 5–Alsocall
edVectori
nter
rupts–becauseithasf i
xed
memorylocati
on.Assoonasanyoft hesepins6to10areacti
ve(high),
theint
ernalci
rcui
t
of8085stopsthenor
mal execut
ionofpr
ogram andt
heprogram control
istr
ansferr
edto
thecor
respondi
ngmemor ylocat
ion.

PIN12-19
AD0-
AD7–f orm bi-di
recti
onal
mult
ipl
exedAddress/Dat
aBus.Thel eastsi
gnif
icant8bi
tsof
thememoryaddr ess( orI
/OAddr
ess)appearonthebusduringthefir
stT-st
atesofa
machinecy
cle.I
tt henbecomesthedatabusduringthenextT-st
ates.

PI
NNO.20–Thegr
oundt
ermi
nal
.
 PINNOS.21to28
(A8-
A15)f
orm unidi
recti
onalmostsi
gni
fi
cant8bi
tsofmemor
yaddr
essor8bi
tsoft
heI/
O
addr
ess.I
tremainsinthehighi
mpedancestat
eduri
ngHOLD,
HALTandRESETmodes.

PINNOS.29to33
ThePinNos.29to33l
abel
edasS0andS1respect
ivel
yareknownasstat
ussignals.These
st
atussi
gnalsal
ongwi
thIO/M si
gnal
indi
cat
ethev ar
iousoper
ati
onsasi
ndicatedbelow.
Machi
necycl
e I
O/M St
atus Contr
olsignal
s
S1 S0

OpcodeFet
ch 0 1 1 RD=0

Memor
yRead 0 1 0 RD=0

Memor
yWr
it
e 0 0 1 WR=0

I
/ORead 1 1 0 RD=0

I
/OWr
it
e 1 0 1 WR=0

I
nter
ruptAck. 1 1 1 I
NTA=0

HALT HI
-Z 0 0
(
HighI
mpedancceSt
ate)

HOLD HI
-Z X X WR=Z
RD,

RESET HI
-Z X X I
NTA=1

X–Uns
( peci
fi
ed)

PINNO.30
ThePinNo.30i sknownasALE( Addr
essLatchEnabl
e)t
ermi
nalusedforenabl
eordi
sabl
e
theaddressbus.Whenthissi
gnali
shightheaddr
essbuswil
lbel
atched.WhenALEislow,
thedatainf
ormati
onwil
l becar
ri
edbyt hebus.

PI
NNOS.31, 32and34
31–WR(wri
tebar)–Whenl
owsi
gnal
WRgener
atedbymi
cropr
ocessorwr
it
esdat
aint
o
I
/Odev
icesormemory
32–RD(r
eadbar
)–WhenlowRDsi
gnal
gener
atedbymi
cropr
ocessorr
eads/
recei
ves
dat
afr
om I
/Oormemor
y.

34–IO/M si
gnali
soneofthest
atussi
gnal–Whenhi
ghi
tdenot
esI
/Ooper
ati
onsand
wheni
tisl
owi ti
ndicat
esmemoryoper
ati
ons

PIN35–READYsi gnal–Somet imestheI/Odevicewi llbeslowerthanthe

micropr
ocessor.READYsi gnalfor
cesthemicropr ocessortowaitti
llthedatabecome
avai
labl
efrom t
hememor yorinput/
outputdev
ices.Thi ssignalisusedt osynchr
onize
thespeedofmicroprocessorwithI
/Oormemor y.WhenREADY=1, thedatawil
lbe
avai
labl
einmicroprocessorandwhenREAD=0, t hedat ai
snotar r
ivedat
micropr
ocessor(waitstat
e).

PI
N36–RESETI N–t hi
sbuttonwil
lbeprovi
dedtotheoperatoras“r
eset”butt
on.
Wheni
tishi
gh,
itreset
stheprogr
am counter
,pr
ogram r
egistersandstopsall
inter
rupt
s.
Whenhi
gh,t
hedataprocessi
ngbegins.

PIN37-Thi
spincarr
iesCLKOUTsi
gnal
.Iti
sder
ivedf
rom t
heon-
chi
posci
l
lat
or,
whi
ch
goest
operi
pheral
stosynchr
oni
zet
hei
rti
mings.

PINNOS.38- 39–HOLDandHLDA( Hol

dAcknowledge)
.Thesesi gnalsusedi
nDMA
(Directmemoryaddress)operat
ions.Supposewhentherei
slot sofdatatobe
transfer
redf
rom I/
Odev i
cetomemor yweareusi
ngaspecial devi
ceDMA
(Por t
er/
cool
i
ef ormicr
oprocessor).Whenholdi
shigh,t
hemi croprocessorwi
l
lgot
o
wai
tst
ateandDMAt
ransf
ersdat
afr
om anyext
ernal
dev
icet
omemor
y.

HLDA–mi cr
oprocessorgi v
est hesignaltotheDMAt hatmicr
oprocessorgot
othewai
t
st
ateandnotdoi nganything.Att hi
sti
meDMAt akescontrol
overbusf r
om
micr
oprocessortotransferdatai.e.author
it
yofhandl i
ngbusisgiventoDMA.
AlowHOLDsi gnal wil
lreturnthecontrol
tot hemicropr
ocessor.

PINNO.40–Thepi
n40i
s+VCC,
whi
chi
stobeext
ernal
l
yconnect
edt
o+5v
oltd.
c.
suppl
y

ADDRESSIGMODESOF8085
Toperf
orm anyoper ati
on,wehavetogi
vethecor
respondingi
nst
ruct
ionst
othe
micr
oprocessor.
I
neachinstruct
ion,programmerhastospeci
fy3things:
1. Oper ati
ont obeper for
med.
2. Addr essofsour ceofdata.
3. Addr essofdest i
nationofr
esul
t.

Themet hodbywhicht
headdressofsour
ceofdataort
headdr
essofdest
inat
ionof
resul
tisgiv
enint
heinst
ruct
ioni edAddr
scal
l essi
ngModes.

Theter
m addressi
ngmodereferstot
hewayinwhi
chtheoperand(t
hev aluei
nwhich
wewillbedoi
ngoperat
ions,
E.g.Addi
ng2+3=5,2,
3,ar
eoperand)oftheinstr
uct
ioni
s
speci
fi
ed.

I
ntel
8085usest hefoll
owi ngaddr essi
ngmodes:
1.Dir
ectAddressingMode
2.Regist
erAddressi ngMode
3.Regist
erI
ndirectAddr essingMode(Def
err
edMode)
4.I
mmedi at
eAddr essingMode
5.I
mpl i
edAddressi ngMode

1.Di
rectAddr
essi
ngMode
I
nthi
smode,ther
egi
sterwi
l
lhol
dst
headdr
essofani
nst
ruct
ion.i
.e.t
her
egi
sterhol
ds
t
headdr
ess.

LDA2500H–Loadthecontentofmemor yl
ocat
ion2500Hi
naccumul
ator
.
 LDAistheoperati
on.
 2500Histheaddressofsource.
 Accumulat
oristhedest
inat
ion.

*
**Ot
herExampl
es-MVIB,
25H,
LXIB,
2000H,
LDA2100H,
OUT03H

2.Regist
erAddressi
ngMode
Dataisalr
eadyavail
abl
eint
heCPU,i
.e.t
heCPUneednotsearchel
sewhere.I
tsav
es
theti
met osear
chi not
hermemor
ylocat
ions.Ther
egi
stermustpl
acetheaddr
essto
getthedata.

MOVA,B–Movethecontentofr
egi
sterBt
oA
 MOVist
heoperati
on.
 Bist
hesour
ceofdata.
 Aist
hedest
inat
ion.

*
**Ot
herexampl
es-SUBB&ADDC,

3.Regi st
erIndirectAddr essi
ngMode( Defer
redMode)
Registerholdsaddr essofanaddr essofadat a.i.e.theregisterhol
dsaddressofadat
a
i
ndirectly
.
MOVA, M –Mov ethedat afrom memor ylocati
onspeci fi
edbyH- Lpai
r t o
accumul ator.
 MOVi st heoperat i
on.
 Mi st hememor ylocationspecif
iedbyH- Lr egist
erpai r
.
 Ai sthedest i
nation.
OtherExampl es-LXIH, 7500
Registerplacest headdress1000andgeti ntoitselfthecont entoft
helocati
on1000
whichi s1010.Onceagai ntheregist
erplacestheaddr ess1010i nbusandgetthedat
a
i
n1010l ocation.Soitwi ll
takemor eti
me

Oftheabove3modes,ef
fect
iveaddr
essi
nginvol
vedasmoreandmore
cal
culat
ioni
nvol
ved.I
tal
lconsumestimeforeff
ect
iveaddr
essi
ngt
ogett
hedat
a.

4.I
mmediateAddr
essingMode
I
nthismode,t
heoperandi
sspeci
fi
edwi
thi
nthei
nst
ruct
ioni
tsel
f.
MVIA,05H–Mov e05Hi nAccumulat
or
 MVIistheoperat
ion.
 05Hi sthei
mmedi at
edata(sour
ce).
 Aisthedesti
nati
on.
*
**OtherExamples-ADI63H,SUI08H,ADI63H,
MVIB09H.

5.Impl
iedAddressi
ngMode
I
faddressofsour
ceofdataaswel
lasaddr
essofdesti
nati
onofr
esul
tis
fi
xed,t
henthereisnoneedtogiveanyoper
andal
ongwit
hthei
nstruct
ion.

CMA–Compl
ementAccumulator
 CMAi st
heoperati
on.
 Aisthesour
ce.
 Aisthedest
inat
ion.

*
**Ot
herExampl
es–STAXB,
LDAXB

I
NSTRUCTI
ONSET

Eachi
nst
ruct
ionhast
wopar
ts–OpcodeandOper
and

Opcode(
oper
ati
oncode)
-Thef
ir
stpar
tist
het
askoroper
ati
ont
obeper
for
med.

Operand-Thesecondpar ti
st hedat at obeoper atedon.Dat acanbegiveni
nv ari
ous
form.
 Itcanspeci fyinv ariousway s: mayi nclude8bi t
/16bi
tdata,aninternal
r
egister
,memor ylocat i
onor8bi t/16bi taddress.
 Ani nstr
uctionisassembl edi nbi nar yform( 0,
1)knownasmachi necodeor
opcode.Duet odi f
ferentway sofspeci f
yingdat aoroperandthemachinecode
arenotsamef oral lthei nst r
uct i
on
 Thesi zeofani nstructi
onsi gnifieshowmuchmemor yspaceisrequi
redt oload
an
i
nst r
ucti
oninthememor y
.8085i nstruct i
onsar eoff oll
owingsizes:
One-byt
eoronewor dInst ructions: opcodeandoper andin8bits
onlyi.
e.oneby t
e.Oper and(s)ar ei nternalregisterandar ecodedintotheinstr
uction.
e.g.MOV, ADD,ANA, SUB, ORAet c.

Two-byt
einstr
ucti
ons:f
ir
stbytei
sopcodei
n8bi
tsandsecondby
tei
soper
and
ei
ther8bitdat
aor8bitaddress.
e.
g.MVI
,ADI,
ANI ,
ORI,XRIet
c.

Three-
by t
einst
ructi
ons: f
ir
stbytei
sopcodein8bit
sandsecondandt
hir
dby
te
areoperandeit
her16bi tdataor16bi
taddress.
Operand1=l ower8bi tdata/address
Operand2=Hi gher8bitdata/address
opcode+dat aby te+databy te
e.
g.LXI ,
LDA,STA, LHLD,SHLDet c.
 (
A)DataTransf
eroper at
ion
 Theseoperati
onssi mplyCOPYt hedat afr
om thesour cetothedest
inat
ion.
 Theytransfer:
 Dat abetweenr egi
sters.
 Dat aBy t
etoar egi
sterormemor ylocati
on.
 Dat abetweenamemor ylocati
onandar egist
er.
 Dat abetweenanI /ODev i
ceandt heaccumul ator
.
 Thedat ainthesourceisnotchanged.
 Datatransferi
nstruct
ionsnev eraff
ecttheflagbits.

S.
NO MNEMONICS EXAMPLES OPERATI ON
1 MVIR,
**8bit MVIB,4FH Loadthe8bi tdat ainaregi
ster
2 MOVRd,Rs*
* MOVB,A Copydatafr
om sour ceregisterRsint
odestinati
onregi
ster
MOVC,B Rd
3 LDA16bit LDA2050H Copythedataby t
eintoAf rom t hememor yspeci
fi
edby
16bitaddr ess
4 STA16bit STA2070H Copyt
hedataby t
efrom Ai ntomemor yspecifi
edby16bi t
address

(
B)Ar
it
hmeti
cOper at
ion–
 Theseinstr
uctionperf
orm addi
ti
on,subt
ract
ionandcompareoper
ations.
 Theseoperationsarealwaysper
formedwithaccumulat
orasoneofthe
operands.
 Thestatusoft her
esultcanbeveri
fi
edbythecontent
softhefl
agregist
er.

Addit
ion:Any8- bi
tnumber ,ort
hecontent
sofaregist
erort
hecontent
sofa
memor ylocati
oncanbeaddedt othecontent
softheaccumulat
orandthesum i
s
st
oredint heaccumulator.Theinst
ruct
ionDADisanexcepti
on;i
tadds16-bi
tdat
a
di
rectl
yinr egi
sterpai
rs.ExADD, ADI

Subtr
acti
on-Any8- bitnumber,orthecontent
sofar egi
ster,ort
hecontent
sofa
memor ylocati
oncanbesubt ract
edfrom thecontent
soft heaccumulat
orandthe
resul
tsstoredintheaccumulator
.Subtract
ionisdoneby2’ scompli
mentmethodand
setcarr
yf l
agtoindicat
eborr
ow.SUB.SBI

I
ncrement
/Decrement-The8-
bitcont
entsofaregi
steroramemor
ylocati
oncanbe
i
ncrement
edordecrementby1.Simil
arl
y,t
he16-bi
tcontent
sofar
egi
sterpai
r(suchas
BC)canbeincr
ementedordecr
ementby1.I NR,DCR.

S.
NO MNEMONI
CS EXAMPLES OPERATION
1 ADDR ADDB Addcont
entoft
heregi
stert
othecont
ent
sofA
2 SUBR SUBC Subt
ractt
hecont
ent
sofar
egi
sterf
rom t
he
 cont
entsofA
3 INR I
NRD I
ncr
easet
hecontentoft
heregister
4 DCR DCRE Decr
easet
hecontent
softheregister

(C)LogicalOper ation
 Per form 8- bit basi cl ogical oper ations wi th t he cont ent of
theaccumul ator
 Logi cal inst r
uct i
onsal somodi fyt hef lagbi ts.
 Op- codesf orlogi cali
nst ructionsi ncl udeANA, ANI,ORA, ORI ,XRA,XRI ,CMA,
CMC, RAL, RLC, RAR, RRC, CMP, CPIet c.
AND, ORExcl usiv e-OR-Any8- bitnumber ,ort hecont entsofar egist er,orofamemor y
l
ocat i
oncanbel ogi callyAND, Or ,
orExcl usiv e-ORwi ththecont ent soft heaccumul ator.
Ther esultsarest oredi ntheaccumul ator.
Rotate-Eachbi tint heaccumul atorcanbeshi f
tedei therleftorr i
ghtt ot henext
positi
on.
Compar e-Any8- bitnumber ,
ort hecont ent sofar egi st
er,oramemor yl ocat i
oncanbe
compar edf orequal it
y, greaterthan, orlesst han, withthecont ent soft heaccumul at or.
Compl ement-Thecont ent soft heaccumul atorcanbecompl ement ed.
S.
NO MNEMONI CS EXAMPLES OPERATI ON
1 ANAR ANAB Logi callyANDt hecont entsofar egi sterwiththecont ent
s
ofA
2 ORAB ORAE Logi callyORt hecont entofar egi sterwi ththecont entof
A
3 XRAR XRAB Exclusi ve–ORt hecont entofar egi sterwi t
ht hecont ent
ofA
4 CMPR CMPB Compar ethecont entofr egist erwi ththecont ent sofA,
forlesst han,equal t
o( or )gr eaterthan

(
D)BranchOper ation
Theseinst r
uctionsar eusedt otransf ert heprogram control
:
 Toj umpf rom onememor yl ocationt oanyot hermemor yl
ocati
onwithina
program
 Fr om onepr ogram t oanot herpr ogr am call
edasasubr outi
ne.
 Al terst he sequence of pr ogram executi
on ei t
herconditi
onal
ly
oruncondi ti
onally
 Uncondi ti
onal branchi nstructions-Tr ansfertheprogram tothespeci
fiedl
abelor
addressJMPuncondi t
ionall
yi .
e.wi t
houtsat isfyi
nganycondi ti
on.
UnconditionalPr ogram control i
nst ructionsar e
 Cal l&RET
Conditi
onal branchi nstructi
ons- Tr ansfert heprogram tothespecifi
edlabelor
addresswhencer t
aincondi ti
oni ssat isfied.
 JNC, JC,JNZ, JZ, JP, JM, JPE, JPO
 CNC, CC, CNZ, CZ, CP, CM, CPE, CPO
 RNC, RC,RNZ, RZ, RP, RM, RPE, RPO

S.
NO MNEMONI
CS EXAMPLES OPERATI
ON
1 JMP16bi t JMP2050H Changetheprogram sequencet ot hespecifi
ed16bi
t
addr
ess address
2 JC16bitaddr
ess JC2025H Changetheprogram sequencet ot hespecifi
ed16bi
t
addressift hecarr
yflagisset
3 CALL16bit CALL2075 Changetheprogram sequencet othelocati
onofa
addr
ess subrouti
ne
4 RET RET Retur
ntothecal l
i
ngpr ogr
am aftercompl et
ingt
he
subrout i
nesequence

(E)Machi
neCont r
ol Oper
ation
Theseinstr
ucti
onsi ncl
udespeci al i
nst
ruct
ionssuchast
ransf
er,
per
for
m
machinerel
atedoperati
on
 HLT–Tohal ttheCPU
 NOP–Toper form nooper at
ion
 EI – EnableInterr
upt
 DI – DisableInter
rupt

Pr
ogr
am t
oAdd2nos

BLOCK1 MVIA,
32H Loadr
egi
sterAwi
th32H
(
CopyOper
ati
on) MVIB,
48H Loadr
egi
sterBwi
th48H
Bl
ock2(
ari
thmet
icoper
ati
on) ADDB Add2by
tesandsav
ethesum i
nA
Bl
ock3 OUT01H Displ
ayaccumul
atorcont
ent
satpor
t
01H
Bl
ock4(Machi
neCont
rol HALT HALT
Oper
ati
on)

TI
MINGDI
AGRAM FOR8085

Itrepr esentstheexecut i
ont i
met akenbyeachi nstruct
ioninagraphi
calfor
mat.
Itist hegraphicalrepresentationofi nit
iat
ionofr ead/writ
eandtransf
erofdata
oper at
ionsundert hecont rolof3- st
atussi gnal
sI O/M ,S1,andS0.Allt
he
oper at
ioni sperformedwi thr especttoCLKsi gnal.
 Thecombi nati
onoft hese3- statussignalsi denti
fyreadorwrit
eoperati
onand
remai nval
idforthedur ationoft hecy cle.
  T-St
ate:
 Onesubdi
vi
sionofanoper
ati
onper
for
medi
nonecl
ockper
iod.
 EachTst
atesi
spr
eci
sel
yequal
toonecl
ockper
iod.
 Aninst
ruct
ion’
sexecut
ionl
engt
hisusual
l
ymeasur
edi
nanumberofT-
st
ates.
Machi
neCy
cle-Thet
imer
equi
redt
ocompl
eteoneacknowl
edgi
nganext
ernal
request
.
Thi
scy
clemayconsi
stof3t
o6T-
stat
es.
Var
iousmachi
necy
clei
n8085i
s
 Opcodef etch
 Memor yread/
writ
e
 Inputr ead/wri
te
 Intereuptacknowledge
 Hal t
/hol d
 Reset
I
nst
ruct
ionCy cl
e:
 Thetimerequi
redtocompl
etetheexecut
ionofani
nstr
uct
ion.I
nthe8085,
aninstr
uct
ioncycl
emayconsistof1to6machinecycl
es
Pr
ocessCy
cle
 Thef
unct
ionofthemi
cropr
ocessori
sdi
vi
dedi
ntot
wocy
cleoft
hei
nst
ruct
ion
 Fetch
 Execute
  Numberofi nstr
uctionsarest
oredinthememor yinsequence.
 Inthenor mal pr
ocessofoperation,t
hemicroprocessorfetches(r
ecei
vesor
r
eads)andexecut esoneinst
ructi
onatatimei nthesequenceunt i
li
texecut
es
t
hehal t(HLT)instruct
ion.
 Thus, aninstr
uctioncyclei
sdefinedastheti
mer equi
redtof et
chandexecut
ean
i
nstr
uct i
on.
I
nst
ruct
ionCy cle(I
C)=Fet chcycle(
FC)+ExecuteCy cle(EC)

The8085mi
cropr
ocessorhas7basi
cmachi
necy
cles.Theyar
e
1.Opcodefet
chcy cl
e(4T)
2.Memoryreadcy cl
eoroperandfet
ch(3T)
3.Memorywritecycl
e( 3T)
4.I
/Oreadcycle(3T)
5.I
/Owr i
tecy
cle(3T) ,
6.Int
err
uptAcknowl
edge,
7.BusI
dlecy
cle
1.OPCODEFETCHCYCLE( 4TStates)
•TheOpcodefet
chcy cle,
fet
chestheinst
ruct
ionsf
rom memor
yanddel
i
ver
sitt
othe
i
nstr
uct
ionregi
sterofthemicropr
ocessor
•Opcodef
etchmachi
necy
cleconsi
stsof4T-
stat
es.

T1St
ate:
Dur
ingtheT1st at
e,thecont
entsoftheprogram counterar
epl
acedonthe16bi
t
addressbus.Thehigherorder8bi
tsaretransf
err
edtoaddr essbus(
A8-A15)andl
ower
order8bit
saretransfer
redtomulti
plexedA/D(AD0-AD7)bus.
ALE(addr
esslat
chenabl
e)signalgoeshigh.AssoonasALEgoeshi
gh,
thememor
y
l
atchest
heAD0-AD7bus.Atthemi ddl
eoftheTst at
etheALEgoesl
ow
T2St
ate:
Duringthebegi
nni
ngofthi
sst
ate,
theRD’si
gnal
goeslowtoenabl
ememory.I
tis
dur
ingt hi
sstat
e,t
hesel
ect
edmemor yl
ocat
ioni
splacedonD0-
D7oftheAddr
ess/Dat
a
multi
plexedbus.
T3St
ate:
Intheprev
iousst
atet
heOpcodei
spl
acedinD0-
D7oftheA/Dbus.Inthi
sstateoft
he
cycle,
theOpcodeoft
heA/Dbusi
str
ansf
erredt
othei
nstr
uct
ionregi
sterofthe
micr
opr
ocessor
.Nowt
heRD’
goeshi
ghaf
tert
hisact
ionandt
husdi
sabl
est
hememor
y
f
rom A/
Dbus.
T4St
ate:
I
nthi
sst
atet
heOpcodewhi
chwasf
etchedf
rom t
hememor
yisdecoded.

2.Memor
yreadcy
cle(
3T)
•Thesemachi
necy
cleshav
e3T-
stat
es.
T1st
ate:
Thehigherorderaddressbus(A8-A15)andl
owerorderaddressanddatamul
ti
plexed
(AD0-
AD7)bus.ALEgoeshi ghsothatt
hememorylatchesthe(AD0-AD7)sot
hat
complet
e16-bitaddressareavai
labl
e.

Theμpi
dent
if
iest
hememor
yreadmachi
necy
clef
rom t
hest
atussi
gnal
sIO/
M’=0,
S1=1,

S0=0.Thi
scondi
ti
oni
ndi
cat
est
hememor
yreadcy
cle.T2st
ate:
•Sel
ectedmemoryl
ocat
ioni
spl
acedont
he(
D0-
D7)oft
heA/
Dmul
ti
plexedbus.RD’
goesLOW T3St
ate:
•Thedatawhichwasloadedontheprevi
ousstat
eistransf
err
edtothemicr
oprocessor
.
I
nthemi ddl
eoftheT3stateRD’goeshi
ghanddisablesthememoryreadoper
ation.
Thedatawhichwasobtainedf
rom thememoryisthendecoded.
3.Memor
ywr
it
ecy
cle(
3T)
•Thesemachi
necy
cleshav
e3T-
stat
es.
T1st
ate:
•Thehigheror
deraddressbus(A8-A15)andl
oweror
deraddressanddat
amulti
plexed
(AD0-
AD7)bus.ALEgoeshi ghsothatthememoryl
atchest
he( AD0-
AD7)sot
hat
complete16-
bitaddr
essareavai
lable.
Thempidenti
fi
esthememoryreadmachi
necy
clefrom t
hest at
ussignal
sIO/
M’=0,
S1=0,
S0=1.Thiscondi
ti
oni
ndi
catest
hememoryreadcycle.T2stat
e:

•Sel
ect
edmemorylocat
ioni
spl
acedont
he(
D0-
D7)oft
heA/
Dmul
ti
plexedbus.WR’
goesLOW T3St
ate:
•I
nthemiddl
eoftheT3stat
eWR’goeshi
ghanddi
sabl
esthememor
ywr
it
eoper
ati
on.
Thedat
awhichwasobtai
nedfr
om t
hememoryist
hendecoded.

4.I
nput
/Out
putReadMachi
neCy
cle
 Microprocessorexecutest
hiscycletor
eadcont
entofI
/Opor
tort
oread8bi
t
datapresentonani nputpor
tsthroughdat
abus.
 TheI
/Or
eadmachi
necy
clei
sexact
lyt
hesameast
hememor
yreadexcept
:
 I
O/M=1(
I/Ooper
ati
on)
,
 s0=0ands1=1.(r
ead)
 WR=1&RD=0
 I
tonl
yhas3T-
stat
es
 Thisi
nstr
uct
ionreadst
hedat
afr
om ani
nputdev
iceandpl
acest
hedat
aby
tei
n
theaccumul
ator
.
 I
tacceptt
hedat
afr
om i
nputdev
icebyusi
ngI
/Or
eadsi
gnal
(IOR)
.
5.I
nput
/out
putwr
it
eMachi
neCy
cle
 Micropr
ocessorexecut
est
hiscycl
etowr
it
e adat
aint
oanI
/O por
tort
owr
it
e
8bitdatapr
esentonanoutputpor
ts.
 TheI
/Owr
it
emachi
necy
clei
sexact
lyt
hesameast
hememor
ywr
it
eexcept
:
 I
O/M=1(
I/Ooper
ati
on)
,
 s1=1ands0=0.(wr
it
e)
 WR=0&RD=1
 I
tonl
yhas3T-
stat
es
 Thi
sinst
ruct
ionpl
acest
hecont
entoft
heaccumul
atoront
hedat
abus.
 I
ttr
ansmi
tthedat
atoout
putdev
icebyusi
ngI
/Owr
it
esi
gnal
(I
OW)
.
Exampl
e–STAi
nst
ruct
ionex:STA526A
I
trequi
re4m/
ccy
cles&13Tst
ates
1.Opcodef
etch(
4T)
,2.Memor
yread(
3T)
,3.Memor
yread(
3T)
,4.Memor
ywr
it
e(3T)
8051-Mi
crocont
rol
l
er-Ref
erbook