DLD Lab#07

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DIGITAL LOGIC DESIGN

LAB REPORT # 07
Submitted to: Engineer Sadaf Sardar
Submitted by: ZAIN ULLAH
Registration Number: 20PWMCT0761
Lab Report Rubrics:

Excellent (4) Proficient (3) Basic (2) Below Basic (1) Student’s
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as per the disorganized and
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are ordered well most of the
guidelines clearly organized in as per the
but requires guidelines are
a logical order. guidelines
minor missing
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discusses the The report is
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experiment/lab discusses the experiment/lab totally
To discuss the actual work but have
work in own words required irrelevant to the
experiment/task irrelevant experiment/lab
with some relevant experiment/lab work
additional information work
information

Calculations
and data analysis
Calculations and Most data and
were performed
data analyses were observations
performed clearly, accurately, but were recorded Calculations
To perform calculations concisely, and minor errors were adequately, but and data
accurately, with made both in with several analyses of lab
and data analysis
calculations and in significant errors were missing
correct units.
applying correct units or omissions.

ZAIN ULLAH 20PWMCT0761


Graphs, if
necessary, were Graphs, if Graphs, if Major
drawn accurately necessary, were necessary, components
To present results in the and neatly and
form of graphs drawn were drawn of lab were
were clearly adequately but missing
labelled. inadequately.

LAB TITLE:
LOGIC SIPLIFICATION USING KARNAUGH MAP

 OBJECTIVES
 To get the expression using karnaugh map.
 To simplify logic expressions using K-maps.
 To simply the expression experimentally.
 Implementing the circuit and get the truth table.

 APPARATUS USED
 AND gate IC 7408
 NOT gate IC 7404
 OR gate 7432
 NAND gate IC 7486
 Bread board
 Jumper wires(male to male and male to female)
 Different LEDs
 9 volts battery  5V regulator

 THEORY KARNAUGH MAPS {1}

A Karnaugh map (K-map) is a pictorial method used to minimize Boolean expressions


without having to use Boolean algebra theorems and equation manipulations. A K-map can
be thought of as a special version of a truth table.

Karnaugh Map is a two-dimensional graphical representation of the input and output


conditions which can minimize the Boolean expression involving 2, 3, 4 and 5 variables. In
other words, it is used to remove redundant operations in a Boolean function.
SIMPLIFICATION OF BOOLEAN EXPRESSION
USING K-MAP (KARNAUGH MAP) [2]
Simplification of Boolean expression using K- Map requires grouping of 1’s. Grouping of 1’s
should follow certain rules:

• Groups should have 2, 4, 8 one’s (1’s).


• Identification of Minterms or Maxterms is necessary.
• Grouping is done horizontally, vertically but never diagonally.  Multiple groups using
repeated 1’s can be done.

This can be better explained with an example using 3 variables as shown below,

The variables that are remaining are OR’ed (Logical Addition) to obtain the reduced Boolean
expression.

 APPLICATIONS OF KARNAUGH MAP


(KMAP)
The applications include:

 They are used in design and implementation of Digital Circuits


 K- Maps are used in the simplification of Half- Adder and Full- Adder circuits

 ADVANTAGES OF K-MAP
The advantages include:

 The most economical and simplified circuit can be built using K-Maps.
 Using K-Maps, logical operation is fast.
 Deriving at the simplest expression helps in reduction of instructions in software applications.
 It is more efficient than any other simplification techniques of Boolean algebra.

 IN LAB EXPERIMENTATIONS

TASK 1
TO SIMPLFY THE EXPRESSION USING MIN-TERMS

EXPRESSION= F(x, y, z) = A’B’ + AC + ABD

F (A,B,C,D)= Σm(0,1,2,3,10,11,12,13,14,15)

MIN-TERMS
MIN TERMS=A’B’C’D’+ A’B’C’D+ A’B’C D’+ A’B’CD+AB’CD’+ AB’CD+

AB C’D’+ABC’D+ABCD’+ABCD

EXPRESSION= F(x, y, z) = A’B’ + AC + ABD


PROCEDURE
I. First we take AND gate IC and OR and NOT GATE Ic a 9V battery and breadboard.
II. Then we setup the circuit according to the circuit diagram.
III. Then we give the power to the circuit.
Then we note the truth table according to the results

CIRCUIT DIAGRAM

TRUTH TABLE
A B C D F

0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

EXPERIMENT DIAGRAM

Figure 1 EXPERIMENT PICTURE IN OFF STATE

Figure 2 EXPERIMENT PICTURE IN ON STATE

===========================================================================

TASK 2
TO SIMPLFY THE EXPRESSION USING MIN-TERMS

EXPRESSION= F(x, y, z) = A’C + ABC + AB’

F (A, B, C, D) = Σm (0, 1, 2, 3, 4) PROCEDURE


I. First we take NAND gate IC a 9V battery and breadboard.
II. Then we setup the circuit according to the circuit diagram.
III. Then we give the power to the circuit.
IV. Then we note the truth table according to the results
CIRCUIT DIAGRAM

A’

A F
B
C

A
B’

TRUTH TABLE

A B C F
0 0 0 1
0 0 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
EXPERIMENTAL PICTURE

Figure 3 IN OFF STATE

Figure 4 IN OFF STATE

CONCLUSION
 We discuss the min and max terms in karnaugh maps of the logic expression.
 Then we prove it experimentally by implementing it on circuit.
 Then we check the result with truth tables.

REFERENCES
1. https://www.techtarget.com
2. https://electricalfundablog.com/

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