Jose Rizal University

80 Shaw Boulevard Mandaluyong City

College of Computer Studies and Engineering

EXPERIMENT NO. 8
CPE C301-301G LOGIC CIRCUITS AND DESIGN

DATE SUBMITTED:
DECEMBER 1, 2022

GROUP 2 MEMBERS:
CANTO, PAULINE

CELOCIA, CELINE

CRISTOBAL, JUSTINE

MASIRAG, ANGELENE

SAMAS, ZARETH

PROFESSOR:
ENGR. BARBRA IANNE EMBILE

S.Y 2022-2023
 EXPERIMENT NO. 8
MOORE MODEL: MODULO 10 BINARY UP/DOWN COUNTER

OBJECTIVES:

• To apply the theories and method of designing modulo counters.

• To design and construct a modulo 10 synchronous up/down counter using JK Flip – flops.

BACKGROUND INFORMATION:

The number of input pulses that causes a counter to reset to initial count is called the modulus of the counter.
Thus, the modulus equals the total number of distinct states (counts), including zero, that a counter can store. For
example, a three – FF counter modulo 8 because it resets to 000 after eighth clock pulse, and it has the eight states 000
to 111. A binary counter with n stages is a mod-2n counter. Note that the largest count of the mod-N counter can
achieve is N-1; that is, a mod-N counter never reaches the binary number equal to its modulus.

In some applications, it is necessary to use a counter whose modulus is a number that cannot be express as 2 n.
For example, in the experiment we wish to divide the clock frequency by 10, we must use a modulo 10 counter.

The purpose of this experiment is to introduce a systematic procedure that can be use to design a synchronous
counter that will count in a prescribed sequence. The logic circuitry used to control the ways in which FF change states
in response to clock pulses.

MATERIALS:

Online Class: Digital Circuit Simulation (IOS and Android Application)

National Instrument Multisim Live (Web Application)

Digital Trainer
Connecting wires
Components:
- 555 timer
- 2 pcs 7476 JK FF IC
- 4 pcs LED
- Logic Gates: (the number of gates needed depends on your design)
7408 Quad Input AND gate
7432 Quad Input OR gate
7404 NOT gate

PROCEDURE:

1. MODULO 10 Binary Up/Down Counter

1.1. Based on the state diagram (Figure 6.1) below, derive the excitation table, construct the K – Map and
design the logic diagram of a Modulo 10 Synchronous Up/Down Binary Counter that uses JK FF.
1.2. Mount all the IC needed on the breadboard, connect the power and ground terminals of all the ICs and
clock.
1.3. Connect the circuit according to your design.
1.4. Connect each FF outputs (Q3, Q2, Q1, Q0) to a LED.
1.5. Observe the sequence of the outputs at the LEDs.

Note: For Online Class, provide the screenshot of your digital circuit simulation.
STATE DIAGRAM:

Figure 9.1. State Diagram for Synchronous Up/Down Modulo 10 Counter Design.

DATA AND RESULTS:

JK FF Excitation Table

Present Next FF Input

State State J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

T = 0 (UP Counter)
T = 1 (DOWN Counter)
 Table 9.1. Excitation Table for Synchronous Up/Down Modulo 10 Counter Design.

Present State Next State Excitation Table

Q4 Q3 Q2 Q1 Q4 Q3 Q2 Q1 J4 K4 J3 K3 J2 K2 J1 K1
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1
1 0 1 0 0 0 0 1 X 0 0 X 0 X X 1
1 0 1 1 0 0 1 0 X 1 1 X 1 X 1 X
1 1 0 0 0 0 1 1 0 X X 0 X 0 X 1
1 1 0 1 0 1 0 0 0 X X 0 X 1 1 X
1 1 1 0 0 1 0 1 0 X X 0 0 X X 1
1 1 1 1 0 1 1 0 0 X X 1 1 X 1 X

KARNAUGH MAPPING:
00 01 11 10 00 01 11 10
000 0 0 0 0 000 X X X X
001 0 0 1 0 001 X X X X
011 X X X X 011 X X X X
101 X X X X 101 0 1 X X
100 1 0 0 0 100 X X X X
101 0 0 0 0 101 X X X X
111 X X X X 111 X X X X
110 X X X X 110 1 0 X X

J4 = T’Q3Q2Q1 + TQ3’Q2’Q1’ K4 = T’Q1 + TQ1’

00 01 11 10 00 01 11 10
000 0 0 1 0 000 X X X X
001 X X X X 001 0 0 1 0
011 X X X X 011 X X X X
101 0 0 X X 101 X X X X
100 0 0 0 0 100 X X X X
101 X X X X 101 1 0 0 0
111 X X X X 111 X X X X
110 1 0 X X 110 X X X X

J3 = T’Q2Q1 + TQ4Q1’ K3 = T’Q2Q1+TQ2’Q1’

 00 01 11 10 00 01 11 10
000 0 1 X X 000 X X 1 0
001 0 1 X X 001 X X 1 0
011 X X X X 011 X X X X
101 0 0 X X 101 X X X X
100 0 0 X X 100 X X 0 1
101 1 0 X X 101 X X 0 1
111 X X X X 111 X X X X
110 1 0 X X 110 X X X X

J2 = T’Q4’Q1 + TQ3Q1’ + TQ4Q1’ K2 = T’Q1 + TQ1’

00 01 11 10 00 01 11 10
000 1 X X 1 000 X 1 1 X
001 1 X X 1 001 X 1 1 X
011 X X X X 011 X X X X
101 1 X X X 101 X 1 X X
100 1 X X 1 100 X 1 1 X
101 1 X X 1 101 X 1 1 X
111 X X X X 111 X X X X
110 1 X X X 110 X 1 X X

J1 = 1 K1 = 1

LOGIC DIAGRAM:
RESPONSE DIAGRAM:
DISCUSSION AND ANALYSIS OF RESULTS:

In this laboratory experiment, we were able to apply the theories and method of designing modulo
counters. We were also able to design and construct a modulo 10 synchronous up/down counter using JK Flip
– flops. In accomplishing, we have come up with an analysis that a modulo 10 counter is a counter that counts
from 0 to 9 and then resets to 0. It is commonly used in digital circuits and is created using JK flip-flops, which
are two-state devices with two inputs (J and K) and one output (Q). The four JK flip-flops are connected in
series, with the output of the first flip-flop connected to the input of the second, and so on. This arrangement
of flip-flops is known as a counter chain. The clock pulse is applied at the input of the first flip-flop. When the
clock pulse is applied, all the flip-flops in the chain are triggered and their outputs change state. The output of
the fourth flip-flop is connected to the input of the first flip-flop to form a loop. This loop continues as long
as the clock pulses are applied and the counter counts from 0 to 9. As for the response diagram, it shows the
signals for the modulo 10 counter design at each clock cycle. The clock signal (CLK) is used to trigger the
counter to increment or decrement its value. Each time the clock rises, the current count is compared with the
preset value (PRE) to determine whether the counter should increment or decrement. If the current count is
less than the preset value, the counter will increment; if it is equal or greater, the counter will decrement. It also
shows the outputs for the modulo 10 counter at each clock cycle. The Q output gives the current count, which
is incremented or decremented according to the comparison with PRE. The output also includes a carry (CY)
signal, which indicates when the counter has reached its maximum value (9).

SUMMARY AND CONCLUSIONS:

To summarize everything, we have learned in accomplishing this activity that a modulo 10 counter is
a type of digital logic circuit that counts up in a sequence and then resets itself after reaching the number 10.
This type of counter is commonly used in digital systems such as computers, calculators, and other digital
devices. A modulo 10 counter is a combinational logic circuit that contains a set of flip-flops and logic gates.
The circuit is designed to increment the count each time it receives an input from an external clock source.
Each time the count reaches 10, the circuit resets itself and begins counting up again.
QUESTIONS AND PROBLEMS:

1. Create a State Diagram, State Table and Logic Diagram of a MODULE – 6 UP/DOWN Counter.

STATE DIAGRAM:

000

101 001

100 010

011

T = 0 (UP Counter)

T = 1 (DOWN Counter)

STATE TABLE:

Present State Next State Excitation Table

Pos T
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 0 1 0 1 0 0 X 1 X X 1
2 0 0 1 0 0 1 1 0 X X 0 1 X
3 0 0 1 1 1 0 0 1 X X 1 X 1
4 0 1 0 0 1 0 1 X 0 0 X 1 X
5 0 1 0 1 0 0 0 X 1 0 X X 1
13 1 1 0 1 1 0 0 X 0 0 X X 1
12 1 1 0 0 0 1 1 X 1 1 X 1 X
11 1 0 1 1 0 1 0 0 X X 0 X 1
10 1 0 1 0 0 0 1 0 X X 1 1 X
9 1 0 0 1 0 0 0 0 X 0 X X 1
8 1 0 0 0 1 0 1 1 X 0 X 1 X
 KARNAUGH MAP:

00 01 11 10 00 01 11 10

00 1 X X 1 00 X 1 1 X

01 1 X X X 01 X 1 X X

11 1 X X X 11 X 1 X X

10 1 X X 1 10 X 1 1 X

J1 = 1 K1 = 1

00 01 11 10 00 01 11 10

00 0 1 X X 00 X X 1 0

01 0 0 X 01 X X X X

11 1 0 X X 11 1 X X X

10 0 0 X X 10 X X 0 1

J2 = T’Q3’Q1 + TQ3Q1’ K2 = T’Q1 + TQ1’

00 01 11 10 00 01 11 10

00 0 0 1 0 00 X X X X

01 X X X X 01 0 1 X X

11 X X X X 11 1 0 X X

10 1 0 0 0 10 X X X X

J3 = T’Q2Q1 + TQ2’Q1’ K3 = T’Q1 + TQ1’

LOGIC DIAGRAM: