Tukwila Itanium processor Tukwila is the code-name for the generation of Intel's Itanium processor family following Itanium

2 and Montecito. It was released on 8 February 2010 as the Itanium 9300 Series. While its features have not been publicly disclosed in detail, it utilizes both multiple processor cores (multi-core) and SMT techniques. The engineers said to be working on this project are from the Alpha project, specifically those who worked on the Alpha 21464 (EV8), which was focused on SMT.

Named for the city of Tukwila, Washington,[1] Tukwila was previously code-named Tanglewood. However the name coincides with the Tanglewood music festival, and Intel renamed the project in late 2003. The processor has two to four cores per die and up to 24 MB L3 of ondie cache. They are the first batch of processors to contain more than 2 billion transistors on a single die.,[2][3]which is added up from [4]: core logic 430 million.  System interface 157 million  L3 cache 1,420 million  I/O logic 39 million  Chip total 2.046 billion Features


Tukwila is a quad-core update to the Itanium processor, which has had a less-than-promising run since the original version was announced back in 2001. The chip's architecture--based on explicit instruction-level parallelism--is a radical departure from the x86 design used in PCs today. It was believed at one time that Itanium would replace x86 chips in many Intel-based computers.

So, what's delaying it this time? Intel has "made some engineering enhancements to the Tukwila platform," according to a statement Thursday from Intel. As one enhancement, Tukwila and its follow-on processors on the Itanium roadmap, Poulson and Kittson, will be socket compatible. Intel is also introducing a technology called "scalable buffered memory" to Tukwila platforms. Scalable buffered memory enables higher memory capacities and uses newer DDR3 (Double Data Rate, third generation) memory. The number of CPU pins that can be dedicated to a memory interface is limited. Scalable buffered memory acts as a memory expander by connecting to multiple DDR3 RDIMMs (Registered Dual In-line Memory Modules) for each CPU memory interface, thus increasing the total memory capacity compared to natively attached memory configurations, according to an explanation provided by Intel.

Additional Information: - Quad-Core processing, EPIC architecture, and Hyper-Threading Technology to support eight threads per processor -Intel Virtualization Technology for enhanced virtualization -Intel Cache Safe Technology -Increased RAS -More than 2 billion transistors -30 MB on-die L3 cache -Enhanced Machine Check Architecture -Increased security features -Demand-Based Switching -Intel QuickPath Interconnect -More than 2X Performance of Previous Generation -Improved Soft Error Rate (SER) Immunity -Voltage Frequency Management -DDR3 Memory The next-generation Itanium processor will build on its predecessor, the Intel Itanium processor 9100. Based on the 90nm process, the Dual-Core

Intel Itanium processor 9100 series has an energy efficient clock speed of up to 1.66GHz and includes new notable features such as core-level lockstep (a mainframe-class RAS feature), demand-based switching for improved energy efficiency and front-side bus performance by up to 667MHz. The Intel Itanium processor 9100 series also boasts 24MB ondie cache and other features such as Enhanced Machine Check Architecture (another mainframe-class RAS feature) and increased security features.