IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 6, NO.

3, SEPTEMBER 2018 1021

A Comprehensive AC-Side Single-Line-to-Ground

Fault Ride Through Strategy of an
MMC-Based HVDC System
Shenghui Cui , Student Member, IEEE, Hak-Jun Lee, Member, IEEE, Jae-Jung Jung, Member, IEEE,
Younggi Lee, Student Member, IEEE, and Seung-Ki Sul, Fellow, IEEE

Abstract— When a single-line-to-ground (SLG) fault occurs on

the ac side of the modular multilevel converter (MMC) in an high-
voltage direct-current transmission (HVDC) system, it results in
the ac-side voltage sag and leads to an instantaneous reduction
of the MMC power capacity. Thus, it calls for the fault ride
through (FRT) strategy to coordinate two MMC stations in the
HVDC system to protect the MMCs against the submodule (SM)
capacitor overvoltage in case of the SLG fault. In the meantime,
the HVDC system is expected to track the prefault active power
as much as possible during the FRT to secure the power
system stability. In this paper, a comprehensive FRT strategy
is proposed, which is free of interstation communication. The
proposed FRT strategy presents fast dynamic response, and it
can prevent effectively the MMC SM-capacitor overvoltage and
HVDC transmission line overvoltage. Moreover, the second-order
voltage and current fluctuations in the HVDC transmission line
caused by the grid unbalance are inherently avoided. Validity of
the proposed strategy and its superiority over existing methods
are demonstrated by simulation of a 200-kV, 400-MW cable-based
HVDC system.
Index Terms— Communication, fault ride through (FRT),
high-voltage direct-current transmission (HVDC), maximum
power transmission, modular multilevel converter (MMC), single
line to ground fault.
I. I NTRODUCTION
V OLTAGE-SOURCE converter-based high-voltage direct-
current transmission (VSC-HVDC) is a promising solu-
tion for various applications, e.g., grid integration of offshore
wind farms and interconnection of asynchronous grids.
Manuscript received August 23, 2017; revised November 13, 2017; accepted
January 18, 2018. Date of publication January 25, 2018; date of current
version August 6, 2018. This work has been partially presented at the IEEE
Energy Conversion Congress and Exposition 2015 held in Montreal, Canada
on September 20–24, 2015 with title “A comprehensive AC side single line to
ground fault ride through strategy of a modular multilevel converter for HVDC
system.” Recommended for publication by Associate Editor Qiang Song.
(Corresponding author: Shenghui Cui.)
S. Cui is with the Institute for Power Generation and Storage
Systems, RWTH Aachen University, 52062 Aachen, Germany (e-mail:
scui@eonerc.rwth-aachen.de).
H.-J. Lee is with the LS Industrial Systems, Anyang 14119, South Korea
(e-mail: hjleea@lsis.com).
J.-J. Jung is with the Mechatronics Research and Development Center,
Samsung Electronics, Hwaseong 18449, South Korea (e-mail: jaejung.jung@
eepel.snu.ac.kr).
Y. Lee and S.-K. Sul are with the Department of Electrical and Computer
Engineering, Seoul National University, Seoul 08826, South Korea (e-mail:
younglee@eepel.snu.ac.kr; sulsk@plaza.snu.ac.kr).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JESTPE.2018.2797934
2168-6777 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Fig. 1. Conceptual configuration of a VSC-HVDC transmission system.
For VSC-HVDC, compared to the conventional two-level
converters (TLCs), a modular multilevel converter (MMC),
which consists of numerous submodules (SMs), is a compet-
itive candidate and is attracting worldwide attention. MMC
presents many advantages such as very low harmonics,
low dv/dt, modularity and simple voltage scaling, high reli-
ability and low switching loss, no necessity of series con-
nection of power semiconductors, and the dc-link capacitor
elimination [1]–[3], [36]–[38].
The conceptual configuration of a VSC-HVDC transmission
system is shown in Fig. 1. It consists of two VSCs, and
each VSC can be either a TLC or an MMC. Typically,
one converter (VSC-A) operates as the voltage regulat-
ing station (VRS) to regulate the HVDC transmission line
voltage v dcA (as well as v dcB ), and the other one (VSC-B)
operates as the power dispatching station (PDS) to regulate
the active power pacB (as well as pdcB ) that flows through the
HVDC transmission system [4].
The single-line-to-ground (SLG) fault is one of the most
frequent faults in ac power system. For power system sta-
bility enhancement, the VSC-HVDC transmission system is
supposed to operate and transmit power even if an SLG fault
occurs in the connected ac grid (either Grid-A or Grid-B).
When an SLG fault occurs in the connected grid, it brings two
challenges to the VSC-HVDC transmission system as follows.
The first challenge is that a second-order oscillation is
imposed on the converter dc-link voltage in unbalanced grid
conditions, e.g., an SLG fault. The second-order voltage
oscillation is not only delivered to the other station resulting
in additional voltage stress on semiconductor devices but
also would lead to malfunction of the protection system [5].
Several dc-link voltage oscillation suppressing controllers had
been proposed for the MMC-based HVDC system to address
this issue [5], [6]. The control scheme in [5] requires real-
time measuring of the output voltages of six arms, which is
challenging in engineering implementation point of view and
might lead to extra investments. The control scheme in [6] calls

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1022 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 6, NO. 3, SEPTEMBER 2018

Fig. 2. Schematic of the VSC dc-side model. (a) TLC. (b) MMC.

for no extra investment on hardware; however, it takes certain Fig. 3. Voltage–current characteristics of two converters in LCC-HVDC.
time to fully suppress the second-order voltage oscillation
during dynamic process.
The second challenge is that the SLG fault results in grid
voltage sag and it consequently leads to an instantaneous
power capacity reduction of the corresponding converter. If the
SLG fault occurs in the grid on the PDS side, namely, Grid-B,
then the grid positive-sequence voltage reduces to around two
third of the rated value, and the instantaneous power capacity
of VSC-B decreases from its rated value PcapB,N to pcapB,F .
Consequently, the dc-side power pdcB decreases to pcapB,F
if the prefault power is larger than pcapB,F , and the system
moves into a new equilibrium point. However, if the SLG fault
occurs in the grid on the VRS side, namely, Grid-A, the dc-side
power pdcA keeps unchanged despite that the converter power
capacity decreases from PcapA,N to pcapA,F . The conceptual
configuration of VSC-A is shown in Fig. 2 [7].
If the prefault power is larger than pcapA,F and the power
flows from PDS to VRS, then the dc-link capacitor of VSC-A
is continuously charged, and it leads to not only the semicon-
ductor device breakdown but also the HVDC transmission line
overvoltage. Several different concepts had been proposed to Fig. 4. Voltage–power characteristics of two converters in VSC-HVDC.
address this issue as follows: (a) Voltage margin control. (b) Power limiting control.
1) installing a full-scale dc chopper breaker on the dc link
of VSC-A [8], [9]; was actually developed from the current margin control [18]
2) direct communication between two stations by either commonly used in the line-commutated converter-based
optical fiber or wireless communication [10], [11]; HVDC (LCC-HVDC) transmission. The principle of the cur-
3) coordination between two stations by utilizing the rent margin control in the LCC-HVDC is shown in Fig. 3.
HVDC transmission line voltage as a reference In the LCC-HVDC, the inverter regulates the HVDC trans-
signal [12]–[17]. mission line voltage and the rectifier regulates the line current.
The first and second proposals may be effective but with While a voltage sag occurs in the grid on the rectifier side,
conspicuous drawbacks. The first concept calls for a con- the rectifier lose the controllability of the line current and
siderable extra investment on hardware. The second con- the inverter takes over the responsibility of the line current
cept needs direct communication. The direct communication regulation.
used in today’s wind parks has a communication delay in As a dual to the current margin control in LCC-HVDC,
an order of tens of milliseconds [35]. Since the capacitor the voltage margin control for VSC-HVDC was proposed
time constant of the MMC is typically among 25–30 ms in in [12]. The principle of the voltage margin control is shown
industrial projects, a partial-scale dc chopper breaker is still in Fig. 4(a). While the voltage sag occurs in the grid on the
required on the dc link of VSC-A to prevent overvoltage [10]. VRS side due to, e.g., an SLG fault, the instantaneous power
In addition, it should be kept in mind that the chopper breaker capacity of the VRS reduces abruptly and the VRS would
is only valid for wind energy integration where the power is lose the controllability of the HVDC transmission line voltage.
unidirectional and always flows from PDS to VRS. In the case When the line voltage increases over the voltage margin, then
of bidirectional power flow applications, e.g., interconnection PDS transits from the power dispatching mode to the voltage
of asynchronous grids, the chopper breaker cannot prevent regulating mode and takes over the responsibility of line
under-voltage (in the case the power flows from VRS to voltage regulation. Consequently, the HVDC system moves
PDS at the prefault) and the over-modulation would occur. into a new equilibrium point temporarily during FRT. Different
Moreover, the direct communication may have the potential approaches to implementation of voltage margin control in
risk of communication failure. The philosophy of the third the offshore wind farm had been discussed and developed
concept was first proposed for VSC-HVDC in [12], which in [13] and [14]. Another derivative control method was

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CUI et al.: COMPREHENSIVE AC-SIDE SLG FRT STRATEGY OF MMC-BASED HVDC SYSTEM
Fig. 5. Simplified schematic of the MMC converter in HVDC applications.
proposed in [15], which was called as power limiting control,
and its principle is depicted in Fig. 4(b). When the HVDC
transmission line voltage increases, then the PDS decreases
the power pacB (consequently as well as pdcB ) linearly with
respect to the transmission line voltage variation. Afterward,
the HVDC system settles down at a new equilibrium point
temporarily during FRT. The common advantage of both the
voltage margin control and the power limiting control is
that, the system can track the prefault power as much as
possible during FRT since | pdcA| = | pcapA,F | at the new
equilibrium point. However, both of them present following
drawbacks.
1) The HVDC transmission line voltage may exceed the
rated voltage during FRT.
2) The dynamic response is sluggish since the control
scheme acts only after the converter dc link capacitor
voltage as well as the HVDC transmission line voltage
get to exceed the voltage margin.
When the VSC-HVDC system is based on the MMC instead
of the TLC, a more advanced FRT strategy would be possi-
ble to manage the SLG fault since the converter capacitor
voltage and the dc-link voltage of the MMC can be fully
decoupled [19], [20]. In this paper, a novel SLG FRT strategy
for the VSC-HVDC transmission system based on MMC is
proposed. By the proposed method, second-order voltage and
current fluctuations in the transmission line are inherently
avoided. The transmission system can track the prefault power
as much as possible automatically and the HVDC transmission
line voltage does not exceed the rated voltage during FRT
regardless of the direction of the prefault power. Moreover,
the proposed method presents faster dynamic performance
compared to the existing voltage margin control and power
limiting control.
II. D ECOUPLED C ONTROL OF MMC
The simplified schematic of the MMC converter in the
VSC-HVDC system is shown in Fig. 5. Typically, the MMC
is grounded by a star reactor grounding device at trans-
former secondary side in HVDC applications [21]. Con-
trol methods of the MMC are generally classified into the
indirect modulation-based control and the direct modulation-
based control [22], [23]. The direct modulation-based control
is one of the most popular techniques in HVDC applica-
tions [24]–[26] due to its simple structure of controllers
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1023
and the self-balancing capability of the arm SM-capacitor
voltages [27]. The major drawback of the direct modulation-
based control is the presence of considerable second-order
harmonic circulating current due to the fluctuation of the
SM-capacitor voltage. Typically, the circulating current is
suppressed by increasing inductance of the arm inductor or by
employing an additional circulating current suppression con-
troller [28]. When the direct modulation-based control is
employed, the SM-capacitor voltage is imposed on the MMC
dc-link voltage and the dc-side presents the same charac-
teristics of that of the TLC, as shown in Fig. 2. Then the
FRT strategies introduced in Section I, which are originally
developed for the TLC-based HVDC system, can be directly
utilized. However, the drawbacks of the existing FRT strategies
are still remained.
When the indirect modulation-based control is employed,
the second-order harmonic circulating current is inherently
avoided, whereas balancing of the arm SM-capacitor voltages
is marginally stable and an additional closed-loop controller
should be employed to stabilize SM-capacitor voltages of
six arms of the MMC [23]. By employing the indirect
modulation-based control, it is able to fully decouple the
ac-side current, the dc-side current, and the circulating current
of the MMC [19], [20]. A temporary circulating-current injec-
tion can be employed to balance the SM-capacitor voltages of
the six arms. A dc circulating current is injected to balance
the SM-capacitor voltages of three phases, and a fundamental-
frequency ac circulating current is injected to balance the
SM-capacitor voltages of the upper- and lower arms in each
phase.
Compared to the other control methods in [32]–[34], which
are based on the decoupled MMC model, the decoupled
control method presented in [19] has various advantages. The
control method presented in [32] can decouple the circulating
current control from the ac- and dc-side currents. However,
it requires extra full-bridge SMs. In [33], the arm capacitor
voltage balancing is realized by injecting additional voltage
references into the arm voltage references. The main drawback
of this method is that the additional reference voltage injection
distorts the arm output voltages, and consequently the currents
are distorted and could not be fully decoupled from each
other. In addition, it is impossible to balance arm capacitor
voltages effectively while there is no apparent power. In [34],
the arm capacitor voltage balancing is realized by both current
and voltage reference injections. The main drawback of this
method is that a dc component is injected into the ac-side
current to balance upper and lower arm SM-capacitor voltages,
which can lead to the transformer core saturation in reality.
Moreover, SM-capacitor voltages of upper three arms and
lower three arms could not be effectively balanced while there
is no dc-side current, namely, in no active-power situation.
On the contrary, the decoupled control method proposed
in [19] can fully decouple the ac-side current, the dc-side
current, and the circulating current without any extra hardware.
Moreover, the arm capacitor voltage balancing is realized only
by the injection of the circulating current and it does not affect
either the ac side or the dc side, and it is generally valid
in overall operation situations. Thus, the decoupled control
1024 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 6, NO. 3, SEPTEMBER 2018
Fig. 6. Terminal behavioral model of the MMC under decoupled control.
Fig. 7. Modeling of the MMC-HVDC transmission system based on the
MMC-decoupled control.
method proposed in [19] has been employed as the basis of
the work in this paper.
The terminal behavioral model of the MMC can be drawn,
as shown in Fig. 6, if the MMC is controlled by the indirect
modulation-based control method in [19]. The ac-side of the
MMC is equal to a three-phase controlled voltage source
behind a three-phase equivalent inductor, and the dc side
of the MMC is equal to a controlled voltage source behind
an equivalent inductor. Different from the case of the direct
modulation-based control method, the SM-capacitor voltage is
not imposed on the dc-link voltage v dc any more, and the volt-
age of the controlled voltage source v dc ∗ can track its reference
in every sampling period of the digital controller (typically
around 100 μs). This important characteristic provides the
degree of freedom to manipulate the dc-link voltage actively.
Thus, an advanced FRT strategy can be developed, which is
impossible to utilize in the TLC-based HVDC system.
The SM capacitors of the MMC play a role of the capacitive
energy buffer between the ac-side three-phase voltage source
and the dc-side voltage source. The dynamics of the total
energy stored in all the SM capacitors can be described by (1)
neglecting the conversion losses
d ∗
 ∗ ∗ ∗
 component of the grid voltage. In this paper, the voltage vector
E total = v dc i dc − v us i us + v vs i vs + v ws i ws . (1)
dt
III. S YSTEM C ONTROL IN N ORMAL O PERATION
Based on the decoupled control of the MMC, a
MMC-HVDC system control strategy in normal operation
was discussed in [29]. The modeling of the MMC-HVDC
transmission system is shown in Fig. 7 when the decoupled
control of MMC is employed. Since the dc-link voltage of
the MMC is fully decoupled from the SM-capacitor voltages
and the MMC can manipulate the dc-link voltage actively,
then MMC-A (namely, the VRS side converter) generates a
constant voltage at a magnitude of the rated transmission line
voltage Vdc,N , and MMC-B (namely, the PDS side converter)
regulates the transmission line current, as shown in Fig. 8.
By this means, the transmission line voltage can be stabilized
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Fig. 8. Block diagram of the transmission line current controller.
Fig. 9. Block diagram of the SOGI-based PLL to separate positive and
negative sequence components of grid voltage and current.
Fig. 10. Block diagram of the power flow controller installed in MMC-B.
regardless of SM-capacitor voltage fluctuations in dynamic
process. Moreover, since the manipulated dc-link voltages
of both MMC-A and MMC-B are fully decoupled from the
SM-capacitor voltage, the second-order voltage and current
fluctuations are inherently avoided even if an SLG fault
occurs either on the VRS side or the PDS side. MMC-B can
∗
estimate v dcA by (2), hence, MMC-A can communicate
with MMC-B at a fast speed by actively manipulating its
dc-link voltage
∗ ∗
v dcA = v dcB + Rdc i dcB . (2)
To deal with the unbalanced grid condition, the second-order
generalized integrator (SOGI)-based phase locked loop (PLL)
system [30] shown in Fig. 9 is employed to separate positive
and negative sequence components of both grid voltage and
current, and to detect the phase angle of the positive sequence
of the ac grid is oriented to the q-axis of the synchronous
rotating reference frame. The ac-side proportional-resonance
current controller constructed in the stationary αβ–reference
frame is employed in the MMC to improve the dynamic
performance [29]. The negative-sequence current is always
managed as null.
The power flow of the transmission system is controlled
by MMC-B. The power flow controller installed in MMC-B is
shown in Fig. 10. The power flow is manipulated by regulating
the power that flows from MMC-B into the coupled ac grid in
a closed-loop manner, namely, pacB . The SM-capacitor energy
of MMC-B, i.e., E totalB is controlled by manipulating the trans-
mission line current i dcB , and consequently pdcB tracks pacB
in steady state neglecting the conversion losses. The block
diagram of the capacitor energy controller of MMC-B and the
plant of the capacitor energy are shown in Fig. 11.
CUI et al.: COMPREHENSIVE AC-SIDE SLG FRT STRATEGY OF MMC-BASED HVDC SYSTEM 1025

Fig. 11. Capacitor energy control of MMC-B. (a) Block diagram of the Fig. 13. Block diagram of the modified leg capacitor energy balancing
controller. (b) Block diagram of the plant. controller.

However, it takes quite long time to compensate the abrupt

active power unbalance and leads to poor dynamic perfor-
mance. In this paper, a modified leg capacitor energy balancing
controller is proposed to improve leg capacitor energy balanc-
ing dynamics in case of the abrupt power unbalance. The block
diagram of the modified controller is shown in Fig. 13.
The instantaneous power that flows out from the SM capaci-
tors of “x” phase to the ac grid can be predicted by the product
of the reference phase voltage v xs ∗ and the measured phase

current i xs shown in Fig. 6. Then the predicted power can

Fig. 12. Capacitor energy control of MMC-A. (a) Block diagram of the be utilized as a feed-forward term to improve the dynamic
controller. (b) Block diagram of the plant. performance of leg capacitor energy balancing. Since there
is a considerable second-order ripple in ac side instantaneous
The block diagram of the capacitor energy controller of power of each phase, notch filters are employed to cut off
MMC-A and the plant of the capacitor energy are shown the ripple components. With this additional feed-forward term,
in Fig. 12. The total capacitor energy stored in the SMs the dynamic performance can be conspicuously improved.
of MMC-A is regulated by drawing the active power pacA
from the coupled ac grid. The power drawn by the HVDC
B. SLG Fault on the PDS Side
transmission line pdcA is utilized as a feed-forward term to
improve the dynamic performance. The power capacity of MMC-B decreases temporarily from
PcapB,N to pcapB,F in case of the grid voltage sag. In case of
IV. P ROPOSED SLG FAULT R IDE T HROUGH S TRATEGY the SLG fault, pcapB,F is around two third of PcapB,N . When
A. Interleg Capacitor Energy Balancing a SLG fault occurs in Grid-B, the active current of MMC-B
increases automatically to sustain the prefault power, and the
In the decoupled control of the MMC, the leg capacitor
magnitude of the active current is limited by the saturation
energies (namely, the energy stored in the SM capacitors of
block shown in Fig. 10.
each phase) are balanced by injecting a dc circulating current
If the prefault power is smaller than pcapB,F , then the
into the converter [19], [20]. Dynamics of the leg capacitor
magnitude of active current increases automatically to keep the
energy of “x” phase E x are described by (3). While the
power flow due to the presence of the power flow controller
ac grid is balanced, the active powers that flow from each
in Fig. 10. On the contrary, if the prefault power is larger
leg into the ac grid are identical. Then, in steady state, there
than pcapB,F , the magnitude of active current increases up
is no circulating current inside the MMC
⎧   to IlimB to track the prefault power as much as possi-
⎪
⎪
d Eu
= v ∗ +
i dc ∗i
− v us
ble. However, the transmitted power during FRT (which is
⎪
⎪ i ucir us
actually pcapB,F ) is smaller than the prefault power and
⎪
⎪ dt dc
 3
⎨  consequently the dc-link current decreases during FRT.
d Ev ∗ i dc ∗i
= v dc i vcir + − v vs vs (3)
⎪
⎪ dt 3
⎪
⎪ 
⎪
⎪ d E i dc C. SLG Fault on VRS Side
⎩ w = v dc ∗ i wcir + ∗ i .
− v ws ws
dt 3 As discussed in Section III, MMC-A can actively manip-
An abrupt active power unbalance occurs in case of the ulate the dc-link voltage to communicate with MMC-B.
SLG fault due to the abrupt grid voltage unbalance. Then MMC-A can vary dc-link voltage to inform MMC-B when
as shown by (3), a dc circulating current should be injected it is lack of instantaneous power capacity. Block diagram
inside the converter continuously during the FRT to keep the of the proposed FRT controller is shown in Fig. 14. In the
leg capacitor energy balanced. The conventional leg capac- proposed FRT strategy, the difference between the active cur-
itor energy balancing controller would inject the required rent references before and after the saturation block (namely,
+∗ +∗
dc circulating current automatically to sustain the balance. i qsA,o and i qsA ) is exploited as a feedback signal to vary

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1026 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 6, NO. 3, SEPTEMBER 2018

Fig. 15. Voltage–power characteristics of two converters when the proposed

FRT control scheme is employed.

consequently a slow dynamic response. Hence, compared to

Fig. 14. Block diagram of the proposed FRT control scheme.
the dc-link voltage v dcA ∗ to inform MMC-B. If the prefault
power is smaller than or equal to the instantaneous power
capacity pcapA,F during FRT, then MMC-A has sufficient
power capacity to sustain the prefault power and i qsA +∗
is equal
+∗
to i qsA,o . Hence, the FRT scheme acts only when the prefault
power is larger than pcapA,F . In such case, the power limiting
coordinator in MMC-A codes the information of the difference
between the required ac-side power and the instantaneous
∗ then i qsA in Fig. 14 increases due to the presence of the
power capacity pcapA,F , namely, pfb to v dcA as given in
the conventional method, dynamic performance of the pro-
posed method can be significantly improved. Principle of the
proposed method is depicted in Fig. 15. Different from the
conventional one, the transmission line voltage never exceeds
the rated voltage regardless of the direction of the prefault
power flow.
One might argue that the conduction loss of the trans-
mission line has not been taken into consideration in the
proposed FRT control method [16]. Hence, if the pre-
fault power flows from MMC-A to MMC-B, it results in
SM-capacitor discharge in case of the long duration of the grid
voltage sag. Actually if the instantaneous power capacity of
MMC-A is not sufficient to regulate the SM-capacitor voltage,
+∗
integrator in the MMC-A total SM-capacitor energy controller.

pfb =
pdcA + ptotalA
∗
− | pcapA,F | Afterward, the dc-link voltage v dcA decreases and MMC-B

3 + +∗

3 +
decreases the power pacB as well as pdcB correspondingly
=

v qgA i qsA,o

v qgA IlimA

. (4) during FRT. Consequently, the system moves into a new

2 2
equilibrium point. Hence, the phenomena concerned in [16]
∗
While v dcA decreases, MMC-B receives the information would not occur. The significant advantage of the proposed
sent from MMC-A in accordance with (2) and (4). Afterward, method compared to the one in [16] is that the proposed
the power limiting coordinator in MMC-B decodes the infor- method does not need to distinguish by precalculation whether
mation to limit the dispatched power command in Fig. 10. the instantaneous power capacity pcapA,F is larger or lower
Dynamics of the dc-link voltage of MMC-A are deduced than the prefault power pdcA. This is especially critical to
as (5) if the conventional power limiting control or the voltage the HVDC system interconnecting two weak grids, because
margin control is employed. Dynamics of the dc-link voltage the transformer secondary-side voltage consequently as well
of MMC-A are deduced as (6) if the proposed FRT control is as pcapA,F vary in a quite large range with respect to the drawn
employed power. By the proposed method, the transmission system
moves automatically into the optimum equilibrium point in
|Vdc,N − v dcA |
 terms of tracking the prefault power during FRT.
1
= (| pdcA| − | pcapA,F |)dt In summary, the proposed control strategy presents the
Ceq Vdc,N following characteristics.
 




1
3 + +∗

3 +

=



1) The integrator in the MMC-A capacitor energy con-
Ceq Vdc,N
2 v qgAi qsA,o
−
2 v qgA IlimA
dt (5) troller assures successful SM-capacitor voltage regula-
Vdc,N − v dcA tion during FRT.





= kpv
pdcA + ptotalA
∗
−
pcapA,F
2) Since the power limiting coordinator in MMC-A utilizes




the active-current reference difference i qgA +∗
, the

3 + +∗

3 +

= k pv
v qgAi qsA,o
−
v qgA IlimA

.
(6) FRT scheme only acts if the instantaneous power capac-
2 2
The difference between the conventional method and the
proposed method is clearly shown by (5) and (6). In the
proposed method the MMC-A dc-link voltage variation is
proportional to the difference between the instantaneous power
capacity and the dc-link power. However, in the conventional
method the dc-link voltage variation is proportional to the
integral of the difference, which would lead to a delay and
ity is not enough to sustain the prefault power.
3) If the prefault power is larger than the instantaneous
power capacity, the active-current reference reaches its
limit IlimA and the HVDC system transmits its available
maximum power automatically in the new equilibrium
point during FRT.
4) Second-order oscillations in the transmission line volt-
age and current are inherently avoided.

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CUI et al.: COMPREHENSIVE AC-SIDE SLG FRT STRATEGY OF MMC-BASED HVDC SYSTEM 1027

TABLE I
PARAMETERS OF THE S IMULATED S YSTEM

Fig. 16. Schematic of the simulated MMC-based VSC-HVDC transmission

system.

D. Discussion on Applicability in Different Applications

In each comprehensive communication-free FRT strategy
based on interstation coordination, it always includes two
layers.
1) The first layer is on interstation coordination for instan-
taneous reduction of power reference by utilizing the
HVDC transmission line voltage as a reference signal.
2) The second layer is on the implementation means of the
power reduction.
The proposed FRT method, the voltage margin control method,
and the power limiting control method are all in the frame of
the first layer. There are several different means in the frame of
the second layer as well. If the HVDC transmission system is
for interconnection of two ac grids, then the power reduction
can be implemented by reducing the grid-side active current.
If the HVDC transmission system is for integration of offshore
wind farms, then the power reduction can be implemented by
frequency modulation [13] or the voltage dip modulation [14].
For a certain application, a control method in the first
layer and a control method in the seconder layer should be
combined to implement a comprehensive FRT strategy. For
example, the FRT strategy in [13] employs the voltage margin
control in the first layer and the frequency modulation means
in the second layer. Thus, the proposed FRT control method
can also be applied to other applications, e.g., offshore wind
farm integration by employing a proper means in the second
layer. The proposed control method is not limited to point-
to-point power transmission and can also be generalized and
applied to multiterminal dc grid system.
Fig. 17. Simulation results of the MMC-B side SLG FRT when the
conventional control scheme is employed.
V. S IMULATION R ESULTS
To verify the proposed FRT strategy, ±200-kV, 400-MW,
is 400 MW, namely, pdcA = 400 MW. At first, the per-
70-km cable-based MMC-HVDC transmission system shown
formance of the conventional direct-modulation-based control
in Fig. 16 is simulated by using PSIM. The Thevenin equiv-
is presented in Fig. 17. The second-order circulating current
alent method is employed to reduce simulation time without
suppressing controller in [28] is employed to suppress the
sacrificing accuracy [31], and -section model including ten
circulating current, and the dc-link voltage second-order oscil-
sections is used for simulation of transmission cable. As a
lation suppressing controller in [6] is employed to suppress
normal engineering design in practical applications to limit
the transmission voltage oscillation caused by the grid voltage
dc-side short-circuit current, smoothing reactors are installed
unbalance. After the SLG fault occurs, the ac-side current of
on the dc-side of the MMC. The detailed parameters of
MMC increases up to IlimB to transmit maximum possible
the system are listed in Table I. The ac-side current limit
power, and the transmission line current i dcB decreases due to
of MMC-A IlimA is set as 1900 A and the ac-side current
the active-power reduction. The dc-link voltage fluctuates dur-
limit for MMC-B IlimB set as 1820 A.
ing the transient process since the dc-link voltage is coupled
with the SM-capacitor voltages. The dc-link voltage second-
A. SLG Fault on the PDS Side order oscillation suppressing controller proposed in [6] can
FRT performance during the SLG fault F2 in Grid-B on the successfully suppress the oscillation; however, it takes around
PDS side is investigated. An SLG fault occurs at t = 1.5 s 100 ms to fully suppress the oscillation. The SM-capacitor
in Grid-B and is cleared 0.15 s later. The prefault power voltages of three phases deviate from each other due to the

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1028 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 6, NO. 3, SEPTEMBER 2018

Fig. 18. Simulation results of the MMC-B side SLG FRT when the proposed Fig. 19. Simulation results of the MMC-A side SLG FRT when the
control scheme is employed. conventional voltage margin control scheme is employed.

abrupt power unbalance, and they are not well balanced even
until the fault is cleared.
The performance of the proposed indirect modulation-based
control is presented in Fig. 18. The dc-link voltage second-
order oscillation caused by the grid voltage unbalance is
inherently absent and the dc-link voltage does not fluctuate
during the transient process thanks to the decoupled control.
It is shown in Fig. 18 that the performance of SM-capacitor
voltage balancing is conspicuously improved in spite of the
abrupt power unbalance. It is because the modified leg capac-
itor energy balancing controller presented in Section IV is
employed, and it can compensate the power unbalance in a
feed-forward manner.

B. SLG Fault on the VRS Side

FRT performance during the SLG fault F1 in Grid-A on the
VRS side is investigated. An SLG fault occurs at t = 2.5 s
in Grid-A and is cleared 0.1 s later. The prefault power
is −400 MW, namely, pdcA = −400 MW. At first, the per-
formances of the conventional voltage margin control and
the power limiting control are presented in Figs. 19 and 20.
The second-order circulating current suppressing controller
in [28] is employed to suppress the circulating current inside
the MMC; however, the dc-link voltage second-order oscil-
lation suppressing controller is deactivated to exclude its
effects on the FRT performance. By employing both control
schemes, MMC-B decreases the power and the HVDC system
can find the new equilibrium point during FRT. However,
the transmission line voltage stays above the rated voltage
during FRT since the prefault power flows from MMC-B to
MMC-A. MMC-B starts decreasing power almost 20 ms later
after the fault occurs by both control schemes.
The performance of the proposed FRT control is presented
in Fig. 21. Different from the conventional control schemes,
Fig. 20. Simulation results of the MMC-A side SLG FRT when the
conventional power limiting control scheme is employed.
MMC-B decreases power as soon as the fault occurs and the
dynamic response of the proposed control is much faster than
that of the conventional control schemes. It is because, there
is no delay introduced by the integral in the proposed method
as discussed in Section IV. Moreover, the transmission line
voltage does not exceed the rated voltage despite the fact that
the prefault power flows from MMC-A to MMC-B.
To illustrate the superior performance of the proposed FRT
method compared to the conventional voltage margin control
and the power limiting control intuitively, simulation results of
the MMC-A side SLG FRT with three different FRT methods

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CUI et al.: COMPREHENSIVE AC-SIDE SLG FRT STRATEGY OF MMC-BASED HVDC SYSTEM
Fig. 21. Simulation results of the MMC-A side SLG FRT when the proposed
control scheme is employed.
Fig. 22. Simulation results of the MMC-A side SLG FRT with the proposed
FRT strategy (in black), the voltage margin control strategy (in red), and the
power limiting control strategy (in blue), respectively.
are summarized in Fig. 22. At first, the HVDC transmission
line experiences temporary overvoltage under the conven-
tional control schemes. However, the HVDC transmission line
voltage does not experience any overvoltage regardless of
the direction of the prefault power if the proposed control
scheme is employed. Second, the capacitor of SM experiences
temporary overvoltage under the conventional control schemes
since the SM-capacitor voltage is coupled with the MMC
dc-link voltage. On the contrary, the capacitor voltage is
well regulated at its rated value with the proposed control
method even during FRT since it is based on the decoupled
control of the MMC. Moreover, the performance of the voltage
balancing of the capacitors is conspicuously improved in spite
of the abrupt power unbalance, as shown in Figs. 19–21.
Third, the dynamic response of the power reduction during
FRT is much faster with the proposed control scheme. It is
because, in the conventional control schemes (both the voltage
margin control and the power limiting control) there is a delay
introduced by the integral term as shown in (5) while such a
delay does not exist in the proposed control scheme as shown
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1029
Fig. 23. Simulation results of FRT in the steady state (a) when the cable
resistance is the nominal value and (b) when the cable resistance increases to
three times of the nominal value.
in (6). The proposed FRT strategy also presents faster power
recovery after the fault clearance due to the aforementioned
reasons.
C. Robustness Against Cable Resistance Variation
Long duration SLG fault is applied in Grid-A to evaluate the
robustness of the proposed control scheme against the cable
resistance variation (due to, e.g., temperature variation). Sim-
ulation results in the steady state are shown in Fig. 23. When
the cable resistance is exactly the nominal value and a long
duration SLG fault is applied, the proposed control scheme can
secure the MMC-AN SM-capacitor voltage control, as shown
in Fig. 23(a) in the steady state. When the cable resistance
increases to three times of the nominal value, the proposed
control scheme can still successfully secure the MMC-AN
SM-capacitor voltage control, as shown in Fig. 23(b). It is
shown in Fig. 23 that the dc-link power of MMC-A, namely,
pdcA is identical in the steady state in both cases. It verifies that
with the proposed FRT control scheme the HVDC system can
automatically move to the optimal equilibrium point during
FRT even if the cable resistance varies in such a wide range.
Thus, the concern mentioned in [16] would not be an issue in
the proposed FRT method.
VI. C ONCLUSION
A communication-free SLG FRT strategy of the
MMC-based HVDC system has been proposed in this
paper. The proposed method guarantees the maximum
available power transmission during FRT. By the proposed
method, the SM-capacitor voltages of six arms of the MMC
are balanced and regulated to the rated value with fast enough
dynamic response after the fault occurs. The second-order
oscillation in the transmission line voltage during SLG fault is
inherently avoided. The transmission line voltage never goes
1030 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 6, NO. 3, SEPTEMBER 2018
above the rated value during FRT regardless of the prefault
power flow direction. Validity of the proposed method is
verified by simulation of a cable-based MMC-HVDC system
employing 216 SMs per arm.
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Shenghui Cui (S’13) received the B.S. degree
in electrical engineering from Tsinghua University,
Beijing, China, and the M.S. degree in electrical
engineering from Seoul National University, Seoul,
South Korea, in 2012 and 2014, respectively. His
master’s dissertation focused on the modeling and
control of modular-multilevel voltage-source con-
verters for high-voltage dc applications.
Since 2015, he has been with the Institute
for Power Generation and Storage System, E.ON
Energy Research Center, RWTH Aachen University,
Aachen, Germany, as a Research Associate. His current research interests
include high-power converters for medium- and high-voltage applications.
CUI et al.: COMPREHENSIVE AC-SIDE SLG FRT STRATEGY OF MMC-BASED HVDC SYSTEM
Hak-Jun Lee (S’11–M’14) was born in Cheongju,
South Korea in 1980. He received the B.S., M.S., and
Ph.D. degrees in electrical engineering from Seoul
National University, Seoul, South Korea, in 2007,
2009, and 2013, respectively.
He has been with the Research and Development
Center, LSIS Company, Ltd., Anyang, South Korea,
since 2013, focusing on electric machine drive sys-
tems. His current research interests include electric
machine drive systems, high-power converters, and
multilevel converters.
Jae-Jung Jung (S’13–M’17) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering
and computer science from Seoul National Univer-
sity, Seoul, South Korea, in 2011, 2013, and 2017,
respectively.
Since 2017, he has been a Researcher with Sam-
sung Electronics Company, Ltd., Hwaseong, South
Korea. He has studied modular multilevel converters
for medium-voltage motor drive applications and
high voltage dc transmission systems, and flexible ac
transmission systems. His current research interests
include power electronics, control of electric machines, and power converter
circuits.
Younggi Lee (S’14) was born in Seoul, South Korea
in 1990. He received the B.S. degree in electrical
engineering from Seoul National University, Seoul,
in 2013, where he is currently pursuing the Ph.D.
degree in electrical engineering.
His current research interests include power elec-
tronics, control of electric machines and converters,
electric/hybrid vehicles, and sensorless drive.
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1031
Seung-Ki Sul (S’78–M’87–SM’98–F’00) received
the B.S., M.S., and Ph.D. degrees in electrical
engineering from Seoul National University, Seoul,
South Korea, in 1980, 1983, and 1986, respectively.
From 1986 to 1988, he was an Associate
Researcher with the Department of Electrical and
Computer Engineering, University of Wisconsin-
Madison, Madison, WI, USA. From 1988 to 1990,
he was a Principal Research Engineer with LG
Industrial Systems Company, Seoul. Since 1991,
he has been a member of faculty of the School of
the Electrical and Computer Engineering, Seoul National University, where
he is currently a Professor. He has authored or co-authored over 150 IEEE
journal papers and a total of more than 340 international conference papers
in the area of power electronics. He holds 14 U.S patents, seven Japanese
patents, 11 Korean patents, and supervised 43 Ph.D students. His current
research interests include power electronic control of electrical machines,
electric/hybrid vehicles and ship drives, high-voltage dc transmission based
on modular multilevel converter, and power-converters circuits for renewal
energy sources.
Dr. Sul was appointed a fellow of IEEE with the contribution to PWM
technology. He was the program chair of IEEE PESC’06 and general chair of
IEEE ECCE-Asia, ICPE, 2011. In 2015, he was the president of KIPE. He
was a recipient of the 2015 IEEE Transaction first and second paper awards
on Industrial Application, simultaneously, the 2016 Outstanding Achievement
Award of IEEE Industrial Application Society, and the 2017 Newell Award
of IEEE PELS.