DIRECT CONVERSION RECEIVER FOR

ACTIVE INTEGRATED ANTENNA

MOHD HAIZAL BIN JAMALUDDIN

UNIVERSITI TEKNOLOGI MALAYSIA

 PSZ 19 :16 (Pind. 1/97)
UNIVERSITI TEKNOLOGI MALAYSIA

BORANG PENGESAHAN STATUS TESIS***

JUDUL: DIRECT CONVERSION RECEIVER FOR ACTIVE
INTEGRATED ANTENNA

SESI PENGAJIAN : 2005/2006

Saya MOHD HAIZAL BIN JAMALUDDIN______________

(HURUF BESAR)

mengaku membenarkan tesis (PSM/Sarjana/Doktor Falsafah)* ini disimpan di Perpustakaan Universiti

Teknologi Malaysia dengan syarat-syarat kegunaannya seperti berikut:

1. Tesis adalah hak milik Universiti Teknologi Malaysia.

2. Perpustakaan Universiti Teknologi Malaysia dibenarkan membuat salinan untuk tujuan pengajian
sahaja.
3. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi

* * Sila tandakan ( X )
pengajian tinggi.
4.

(Mengandungi maklumat yang berdarjah keselamatan

SULIT atau kepentingan Malaysia seperti yang termaktub di
dalam AKTA RAHSIA RASMI 1972)

(Mengandungi maklumat terhad yang telah ditentukan

TERHAD oleh organisasi / badan di mana penyelidikan dijalankan)

X TIDAK TERHAD

Disahkan oleh

________________________________ ______________________________
(TANDATANGAN PENULIS) (TANDATANGAN PENYELIA)

23, JALAN PALAS 14 DR MOHAMAD KAMAL

TAMAN TERATAI BIN ABD RAHIM
81110 SKUDAI, Nama penyelia
JOHOR

Tarikh : 28 NOVEMBER 2005 Tarikh : 28 NOVEMBER 2005

CATATAN : * Potong yang tidak berkenaan

** Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak
berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh
tesis ini perlu dikelaskan sebagai SULIT atau TERHAD.
*** Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah dan Sarjana secara
penyelidikan, atau disertai bagi pengajian secara kerja kursus atau
penyelidikan, atau Laporan Projek Sarjana Muda (PSM).
 “I hereby declare that I have read this thesis and in my opinion this thesis is
sufficient in terms of scope and quality for the award of the degree of
Master of Engineering (Electrical-Electronic & Telecommunication)”

Signature : ....................................................

Name of Supervisor : DR. MOHAMAD KAMAL BIN ABD RAHIM

Date : 28 NOVEMBER 2005

DIRECT CONVERSION RECEIVER FOR
ACTIVE INTEGRATED ANTENNA

MOHD HAIZAL BIN JAMALUDDIN

A thesis submitted in fulfillment

of the requirements for the award of the
degree of Master of Engineering
(Electrical-Electronic & Telecommunication)

Fakulti Kejuruteraan Elektrik

Universiti Teknologi Malaysia

NOVEMBER, 2005
I declare that this thesis entitled “Direct Conversion Receiver for Active
Integrated Antenna” is the result of my own research except as cited in the
references. The thesis has not been accepted for any degree and is not concurrently
submitted in candidature of any other degree.

Signature : _______________________________

Name : MOHD HAIZAL BIN JAMALUDDIN.

Date : 28 NOVEMBER 2005

 iii

To my parents and family, for their guidance, support, love and enthusiasm. Without
these things this thesis could not have been possible.
 iv

ACKNOWLEDGEMENT

Praise is to Allah who has given me the strength, physically and mentally in
order for me to complete this thesis.

I extend my sincere gratitude and appreciation to many people who made this
master’s project possible. Special thanks to my supervisor Dr. Mohamad Kamal Abd
Rahim for their invaluable guidance, suggestions and full support in all aspects
during the whole process of the project. The thank goes also to my lecturer Assoc.
Prof. Dr Jafri Din that was indirectly involved in this project.

Many thanks go to Mr. Mohamad Zoinol Abidin and Mr. Azhari Asrokin
from the Wireless Communication Centre for their suggestions and help in
fabricating the final device.

Finally, I would also like to thanks my entire friend and whoever involved for
their valuable help during my project and for providing me with useful information.
 v

ABSTRACT

This thesis describes the design of a compact miniature and low cost
microstrip dipole antenna integrated with 900 hybrid coupler, oscillator and diodes
for direct conversion, or zero IF receiver. The frequency chosen is at 2.4 GHz, which
is of particular interest for RFID application. In this receiver design, Agilent’s ADS
software using momentum simulation and circuit simulation is employed to analyze
the entire structure. In the fabrication process, the proposed receiver element is
printed on a FR4 substrate with a dielectric constant of 4.7, a thickness of 1.6 mm
and a conductor loss of 0.019. Microstrip dipole antenna that is presented here has a
wide bandwidth up to 24% bandwidth. The 900 hybrid coupler can act as a phase
shifter to provide the necessary 900 characteristics to operate with I/Q signal for
direct conversions. Two schottky diodes (HSMS 8101) are mounted onto each of two
coupler’s output port to act as a mixer. One kHz sinusoidal signal act as a baseband
have been generated and modulated using signal generator. The demodulated signal
is detected using direct conversion receiver circuit and the baseband signal at the
output ports should be detected using oscilloscope.
 vi

ABSTRAK

Tesis ini menerangkan mengenai rekaan padat antena mikrostrip dipole

digabungkan bersama 900 hybrid coupler, oscillator dan diod untuk penerima Direct
.Conversion atau Zero-IF. Frekuensi yang digunakan adalah pada 2.4 GHz dimana ia
banyak digunakan untuk aplikasi RF ID. Di dalam rekaan penerima ini, perisian
Agilent ADS menggunakan simulasi momentum dan litar telah digunakan untuk
menganalisa seluruh struktur litar. Antena microstrip dipole ini mempunyai
lebarjalur sehingga 24 %. 900 hybrid coupler pula akan bertindak sebagai penganjak
fasa, supaya mencapai ciri 900 untuk operasi bersama isyarat I/Q. Dua diod Schottky
(HSMS 8101) dilekapkan bersama setiap pasangan port keluaran untuk bertindak
sebagai pengadun. Satu pin daripada diod itu disambungkan pada hujung port
keluaran dan satu pin lagi dibumikan di atas satah bumi. Satu kilohertz isyarat sinus
bertindak sebagai isyarat baseband telah dijana dan dimodulat menggunakan penjana
isyarat. Isyarat yang telah termodulat kemudian dikesan menggunakan litar penerima
Direct Conversion dan isyarat baseband kemudiannya berjaya dikesan pada port
keluaran menggunakan osiloskop.
 vii

TABLE OF CONTENTS

CHAPTER TITLE PAGE

DECLARATION
DEDICATION iii
ACKNOWLEDGEMENT iv
ABSTRACT v
ABSTRAK vi
TABLE OF CONTENTS vii
LIST OF FIGURES xi
LIST OF ABBREVIATIONS xiii
LIST OF APPENDICES xiv

1 INTRODUCTION 1

1.1 Introduction 1
1.2 Objective 2
1.3 Project Background 2
1.4 Scope Of Project 4
1.5 Thesis Structure 4
1.6 Summary 5
 viii

2 RECEIVER ARCHITECTURE 6

2.1 Introduction 6
2.2 Types Of Receiver 6
2.2.1 The Superheterodyne Receiver 7
2.2.2 Image Reject- Receivers 10
2.3.3 Low IF Single Conversion
Receiver 11
2.2.4 Wideband IF with Double
Conversion 12
2.2.5 Direct Conversion Receiver 13
2.3 Direct Conversion Receiver concept 14
2.3.1 DCR Architecture 15
2.3.2 DCR Design Consideration 17
2.3.3 DC Offset 18
2.3.4 I/Q Mismatch 19
2.3.5 Even Order Distortion 21
2.3.6 LO Leakage 23
2.4 Active Integrated Antenna (AIA) 23
2.4.1 Definition of AIA 24
2.4.2 Previous research on AIA 24
2.5 Summary 27

3 DESIGN AND SIMULATION OF DCR 28

3.1 Introduction 28
3.2 Design Flow Chart 28
3.3 Design and Selection of DCR
Components 29
 ix

3.3.1 Microstrip Dipole Antenna 30

0
3.3.2 Quadrature 90 Hybrid Coupler 33
3.3.3 Voltage Tuned Oscillator (VTO) 38
3.3.4 Diode Mixer 39
3.4 Simulation of DCR Circuit 40
3.5 Fabrication 43
3.6 Summary 45

4 RESULTS AND DISCUSSION 46

4.1 Introduction 46
4.2 DCR Components Simulation
& Measurement Results 46
4.2.1 Microstrip Dipole Antenna 47
4.2.2 900 Hybrid Coupler 47
4.3 AIA DCR Simulation Results 51
4.4 AIA DCR Measurement Results 53
4.5 Summary 56

5 CONCLUSION 57

5.1 Future Works 58

5.2 Summary 58

REFERENCES 59

Appendices A-B 62-75

 x

LIST OF FIGURES

NO. OF FIGURES TITLE PAGE

Figure 2.1 The Superheterodyne Receiver 8

Figure 2.2 Image Rejection and selectivity in
a Superheterodyne receiver (high-side LO injection) 9
Figure 2.3 The Hartley image-reject architecture 11
Figure 2.4 The Weaver image-reject architecture 11
Figure 2.5 Low IF single conversion receiver 12
Figure 2.6 Wideband IF with double conversion 13
Figure 2.7 Direct Conversion Architecture 16
Figure 2.8 Spectrum before and after direct-conversion 17
Figure 2.9 Self-mixing of (a) LO. (b) Interferers 19
Figure 2.10 Quadrature generation in a) RF path and b) LO path 20
Figure 2.11 Effect of I=Q mismatch. Constellation
(a) with gain error.; (b) with phase error. Time-domain
waveforms (c) with gain error; (d) with phase error. 21
Figure 2.12 Single Balanced Mixer 22
Figure 2.13 Downconversion of signal harmonics. 22
Figure 2.14 Two-element active antenna configuration 25
Figure 2.15 Direct Conversion Receiver 25
Figure 2.16 Circuit architecture of the integrated antenna
with direct conversion circuitry 26
 xi

Figure 2.17 Ring AIA construction 27

Figure 3.1 Design Flow Chart 29
Figure 3.2 Microstrip Dipole Antenna Layout 30
Figure 3.3 Layout Environment of Microstrip Dipole Antenna
using Method of Moment (MOM) simulation 32
Figure 3.4 Fabricated Microstrip Dipole. 33
Figure 3.5 Geometry of Branch-line coupler 34
Figure 3.6 Calculation of width and length for Zo = 50 Ω. 35
Figure 3.7 Calculation of width and length for Zo = 50 /√2 Ω. 35
Figure 3.8 Line Calculator of width and length for Zo=50
and Zo=50 /√2Ω 36
Figure 3.9 Layout Environment of Quadrature 900 Hybrid
Coupler using Method of Moment (MOM) simulation 37
Figure 3.10 Fabricated 90 degree hybrid coupler 37
Figure 3.11 VTO–8150 Power Output, Frequency and
Modulation Sensitivity vs. Tuning Voltage. 38
Figure 3.12 VTO-8150 38
Figure 3.13 Typical Forward Current vs. Forward Voltage at
Three Temperatures. 39
Figure 3.14 Fabricated diode mixer with microstrip line 40
Figure 3.15 Circuit Simulation Design of DCR 41
Figure 3.16 Modulated Signal Generations 42
Figure 3.17 AIA Direct Conversion Receiver Circuit 42
Figure 3.18 The flow chart of fabrication process 43
Figure 3.19 The Layout generated in ADS layout environment 44
Figure 4.1 Input Return Loss for Microstrip Dipole Antenna. 47
Figure 4.2 Hybrid Coupler S parameter results
a) Simulation b) Measurement 49
 xii

Figure 4.3 Output phase different at port 2 and port 3 for

a) Simulation b) Measurement 50
Figure 4.4 Comparison of original baseband signal from
modulator and detected baseband signal at I/Q output 52
Figure 4.5 Detected demodulated spectrum at output port 52
Figure 4.6 Fabricated Direct Conversion Receiver 53
Figure 4.7 Experimental setup of DCR circuit 54
Figure 4.8 Detected baseband signal at I & Q Output Port 55
Figure 4.9 Comparison of transmitted sinusoidal wave and
detected baseband signal 55
 xiii

LIST OF ABBREVIATIONS

ADS - Advanced Design System

AIA - Active Integrated Antenna
BW - Bandwidth
CAD - Computer Aided Design
dB - Decibel
DCR - Direct Conversion Receiver
G - Gap
GHz - Giga Hertz
IF - Intermediate Frequency
kHz - Kilo Hertz
L - Length
LAN - Local Area Network
LO - Local Oscillator
MHz - Mega Hertz
Mm - Milimeter
o
C - Celcius
o
K - Kelvin
RF - Radio Frequency
VTO - Voltage Tuned Oscillator
W - Width
WCC - Wireless Communication Centre
Zo - Characteristic Impedance
εr - Material substrate
Λ - Wavelength
Ω - Ohm
 xiv

LIST OF APPENDICES

APPENDIX TITLE PAGE

A Varactor Tuned Oscillator 61

B Surface Mount Microwave

Schottky Mixer Diodes 69

 CHAPTER I

INTRODUCTION

1.1 Introduction

The wireless industry has experienced a significant growth in the past several
years. In order to have smaller products with more features, lower power
consumption, and shorter design cycles, the size and complexity of the RF section of
the product must be reduced. To explain this impact on the RF section one must
briefly examine radio receiver architecture [1].

There are several types of receiver architecture that have been implemented
in the wireless industry. However, in this thesis, five types of receiver will be
discussed in the next chapter. The these are Superheterodyne Receiver, Image-Reject
Receiver, Low IF Single Conversion receiver, Wideband IF with Double Conversion
and Direct Conversion Receiver.

Superheterodyne receiver is the most widely used reception technique.

However, it has several disadvantages that will be discussed later in the next chapter.
The second type of receiver is Image Reject Receiver, which proposed is to remove
image without the need of any post-LNA image-reject filtering. The third type of
receiver is Low IF Single Conversion Receiver purpose is to protect the receiver
from all the DC-related problems that pertain to DCR, while retaining the DCR's
benefit of elimination of high Q IF filters. The fourth type of receiver is Wideband IF
 2

with Double Conversion is very similar to the superheterodyne configuration. The

last type of receiver which is particularly topic of interest in this project is Direct
Conversion Receiver (DCR) or Zero IF Receiver. This DCR is implemented to
overcome the problem that occurred in superheterodyne receiver such as problem of
image and complex circuitry.

Direct Conversion Receiver (DCR) can be implemented with Active

Integrated Antenna (AIA). AIA is Active Integrated Antenna is used to classify a
combined antenna and front end where the antenna and active device interact to
produce the overall circuit’s response. The implementation of DCR and AIA gives
advantages such as simple circuitry, compact size and lower manufacturing cost.
These make the DCR technique popular choice for implementation in majority of
wireless products [2].

1.2 Objective

The objective of this project is to design and fabricate a compact and low cost
Direct Conversion Receiver (DCR) at frequency 2.4 GHz.

1.3 Project Background

Most of radio receivers adopt superheterodyne technique, which can provide

high selectivity and sensitivity. Superheterodyne receiver contains RF, IF and
baseband stages. The system has many advantages such as good stability, high gain,
low noise and flexibility for channel selection. However, superheterodyne receiver
 3

has some disadvantages such as high power consumption, complex circuitry and the
existence of an image frequency signal. To overcome this problem, direct
conversion or zero-IF detection has been proposed as alternative receiver architecture
[2-4]. Zero IF or direct conversion detection is a kind of coherent detection method.
A modulated signal is mixed with the unmodulated carrier to produce zero IF signal.

The output signal contains the baseband signal’s amplitude and phase
information [4]. This kind of receiver can eliminate the IF stage and the band pass
and band reject filters, thereby reducing the circuit complexity.

A compact miniature direct conversion receiver constructed with microstrip

dipole antenna, a local oscillator (LO), diodes mixer and hybrid coupler has been
designed for this research. This design can be realized in an active integration
antenna (AIA) [6-9]. AIA can be regarded as an active microwave circuit in which
the output or input port is free space instead of a conventional 50Ω interface [10]. In
this case, the antenna can provide certain circuit functions such as resonating,
filtering, and duplexing, in addition to its original role as a radiating element. On the
other hand, from an antenna designer’s point-of-view, the AIA is an antenna that
possesses built-in signal- and wave-processing capabilities such as mixing and
amplification.

Miniature size, low cost and simple circuitry is the main advantages to
implement this AIA design using direct conversion technique. 2.4 GHz frequency is
chosen since it is within the license free frequency bands, Industrial, Scientific and
Medical (ISM) bands [10]. In this thesis simulation and measurement results of
DCR components and DCR itself will be discussed in this thesis.
 4

1.4 Scope Of Project

The scope of this project describes the design of a compact miniature

microstrip dipole antenna integrated with 900 hybrid coupler, oscillator and diodes
for direct conversion, or zero IF receiver. The frequency chosen is at 2.4 GHz,
which is of particular interest for RFID application. In this receiver design, Agilent’s
ADS software using momentum simulation and circuit simulation is employed to
analyze the entire structure. DCR components which are dipole antenna and 900
hybrid coupler are needed to be design part by part. A suitable oscillator and mixer
diodes selection should be done for DCR at 2.4 GHz. All of the DCR components
are then being assembled and tested. This DCR should be able to detect baseband
signal that has been transmitted throughout signal generator. A compact DCR are
then fabricated in one board and again will be tested using signal generator.

1.5 Thesis Structure

The thesis is divided into five chapters and covers the research works that
have been through for Direct Conversion Receiver design.

Chapter II reports the literature review of the basic concept of Direct

Conversion Receiver and implementation with Active Integrated Antenna. Chapter
III describes the design, simulation and fabrication process. Using Advanced Design
System (ADS) software will do this process. The simulation and measurement
results are reported in Chapter IV. This chapter also includes discussion from
simulation and measurement results. Chapter V concludes the research work and
gives suggestion for future development of the research project.
 5

1.6 Summary

This chapter is an introduction for objective and research scope of the project.
The research background and importance of the project also be explained. Besides,
the thesis structure is highlighted. The research work performed will be reported in
the following chapter.
 CHAPTER 2

RECEIVER ARCHITECTURE

2.1 Introduction

This chapter will discuss on several types of receiver. There are five type of
receiver described in this chapter. However the main focus of interest is on Direct
Conversion Receiver. Some definition and background research on Active Integrated
Antenna (AIA) also will be discussed in this chapter. Besides that, some DCR
components theory that will be used in this project also will be discussed in this
chapter.

2.2 Types Of Receiver

Superheterodyne receiver counterpart was first established and introduced in

1918 by Armstrong [11]. The origins of the direct conversion receiver (DCR) date
back to the first half of last century when a single down-conversion receiver was first
described by F.M. Colebrook in 1924 [12], and the term homodyne was applied.
Additional developments in 1947 led to the publication of an article by D.G. Tucker,
[13] which first coined the term synchrodyne, for a receiver which was designed as a
precision demodulator for measurement equipment rather than a radio. Another
paper by Tucker in 1954 [14] reports the various single down-conversion receivers
 7

published at the time and clarifies the difference between the homodyne (sometimes
referred to as coherent detector) and the synchrodyne receivers. The homodyne
receiver obtains the LO directly (from the transmitter, for example), whereas the
synchrodyne receiver synchronizes a free-running LO to the incoming carrier.

Over the last decade or so, the drive of the wireless market and enabling
monolithic integration technology have triggered research activities on direct
conversion receivers, which integrated with the remaining analog and digital sections
of the transceiver, have the potential to reach the "one-chip radio" goal. Besides, it
favors multi-mode, multi-standard applications and thereby constitutes another step
towards software radio.

The present section refers to several recent publications [1-2] which provide a
thorough survey and insight, and display renewed interest in direct conversion
receivers. Overcoming some of the problems associated with the traditional
superheterodyne and being more prone to integration, DCR has nevertheless an array
of inherent challenges. After a brief description of alternative and well-established
receiver architectures, this article presents the direct conversion reception technique
and highlights some of the system level issues associated with DCR.

2.2.1 The Superheterodyne Receiver

The superheterodyne or heterodyne receiver is the most widely used

reception technique and finds numerous applications from personal communication
devices to radio and TV tuners. It has been used extensively and is well understood.
It comes in a variety of combinations, [2,15-16] but essentially relies on the same
principle. The RF signal is first amplified in a frequency selective low noise stage,
then translated to a lower intermediate frequency (IF) with significant amplification
 8

and additional filtering, and finally down-converted to baseband with either a phase
discriminator or straight mixer, depending on the modulation format. This technique
is illustrated in the schematic of Figure 2.1.

Figure 2.1: The Superheterodyne Receiver

The use of a superheterodyne technique entails several trade-offs. Image

rejection is a prevailing concern in this architecture. During the first down-
conversion to IF, any unwanted activity at a frequency spaced at fIF offset from the
LO frequency (fLO ) on the opposite side of fLO from the desired RF channel, will
produce a mixing product falling right into the down-converted channel at fIF . In
practice, a RF bandpass filter, usually a surface acoustic wave (SAW) device, is
utilized to perform band selection ahead of the low noise amplifier (LNA), while a
second filter follows the LNA to perform image rejection. If these filters are identical
they share the burden of the two functions. But some amount of image rejection
must follow the LNA, for without it, the LNA's noise figure will effectively double
due to the mixing of amplified image noise into the IF channel. Instead of the RF
SAW filter, other passive filtering technologies such as dielectric or ceramic
resonators can also be featured. The higher the IF, the more relaxed the requirements
on the cut-off frequency of the image reject filter. Once at the IF, the presence of an
interfering signal in the vicinity of the channel mandates sharp filtering around the
channel; this filtering is performed after the first mixer by the channel select filter,
which is also often an IF SAW filter. Figure 2.2 shows this filtering process.
 9

Essentially, the exercise is that of a carefully engineered balance among

several variables, including the rejection provided by the various filters, frequency
planning and linearity of the active stages. Dual IFs provide additional room to
maneuver with filter selectivity, but somewhat complicate the frequency planning.

Figure 2.2: Image Rejection and selectivity in a Superheterodyne receiver (high-

side LO injection)

The selectivity required of the two aforementioned filters (in terms of

fractional bandwidth) makes them unsuitable candidates in the foreseeable future for
integration, due to the low Qs of current silicon processes, and have to be
implemented by bulky off-chip components. The IF channel filter in particular
requires high Q resonators for its implementation the higher the IF, the lesser the
filter's fractional bandwidth (that is, its ratio of bandwidth to center frequency),
necessitating ever-higher Q. This high Q requirement is most commonly met by the
use of piezoelectric SAW and crystal filters.

This introduces additional constraints, as those filters often require

inconvenient terminating impedances, and matching may impinge on such issues as
noise, gain, linearity and power dissipation of the adjoining active stages. The
narrower the fractional bandwidth, the more likely the filter's passband shape will
exhibit an extreme sensitivity to variations in matching element values.
Additionally, the specificity of the IF filter to the bandwidth of the signal and hence
the standard used makes superheterodyne receivers unsuitable for multi-standard
 10

operation. Nonetheless, superheterodyne is known for its high selectivity and

sensitivity.

2.2.2 Image Reject- Receivers

Alternatively, by smart use of trigonometric identities, the image can be

removed without the need of any post-LNA image-reject filtering. This is the
principle of image-reject receivers [2, 17], the first of which is the Hartley
architecture, introduced in 1928 [18]. It makes use of two mixers with their local
oscillators in a quadrature phase relationship; this separates the IF signal into in-
phase (I) and quadrature (Q) components. It then shifts the Q component by 90°
before recombining the two paths, where the desired signal, present in both paths
with identical polarities, is reinforced, while the image, present in both paths with
opposite polarities, is cancelled out. The dual of the Hartley architecture, known as
the Weaver image-reject receiver [19], achieves the relative phase shift of one path
by 90° by the use of a second LO enroute to another IF or to baseband. The same
result is achieved. However, the reliability of these receivers heavily depends on the
accuracy of the I/Q paths, that is, the gain and phase imbalance between the two
branches. Figures 2.3 and 2.4 show diagrams of the Hartley and Weaver image-
reject architectures, respectively (high frequency mixing products are removed by
low-pass filtering not shown on figures).
 11

Figure 2.3: The Hartley image-reject architecture

Figure 2.4: The Weaver image-reject architecture

2.2.3 Low IF Single Conversion Receiver

Low IF single conversion, shown in Figure 2.5, is an offspring of the DCR.

Its main purpose is to protect the receiver from all the DC-related problems that
pertain to DCR, while retaining the DCR's benefit of elimination of high Q IF filters.
As its name indicates, instead of directly converting the signal to baseband, the LO is
slightly offset from the RF carrier, typically one to two channels. The low IF means
that the fractional bandwidth of the IF bandpass filtering is large, making it possible
to implement it with low Q components. The IF SAW or crystal filter needed in the
 12

high IF case can be replaced with an active RC filter or other filter suitable for low
frequency operation, that is also conducive to silicon integration. The low IF signal
may be translated to baseband through another mixer, or preferably, in the digital
domain following analog-to-digital (A/D) conversion. Of course, this comes at the
expense of faster and higher resolution A/D converters. If the IF frequency is equal
to only one or two channel widths, then it is not possible to provide image rejection
at RF, as the RF filter must be wide enough to pass all channels of the system. In
this case, all image rejection must come from the quadrature down-conversion to the
low IF, which itself resembles the Hartley architecture, once the baseband conversion
is added.

Figure 2.5: Low IF single conversion receiver

2.2.4 Wideband IF with Double Conversion

This architecture, shown in Figure 2.6, is very similar to the superheterodyne

configuration. In this case, the first mixer utilizes an LO that is at a fixed frequency,
and all channels in the RF band are translated to IF, retaining their positions relative
to one another. The second mixer utilizes a tunable LO, thus selecting the desired
channel to be translated to baseband. A subsequent lowpass filter suppresses adjacent
channels.
 13

Figure 2.6: Wideband IF with double conversion

2.2.5 Direct Conversion Receiver

Direct conversion reception is also referred to as homodyne, or zero-IF, is the

most natural solution to receiving information transmitted by a carrier. However, it
has only been over the past decade or so that this type of reception has found
applications other than pagers. Direct conversion reception has several qualities
which make it very suitable for integration as well as multi-band, multi-standard
operation, but there are severe inherent obstacles that have for a long time kept it in
the shadow of the superheterodyne technique. The next section will described more
details on DCR concept and some design consideration of implementing DCR
 14

2.3 Direct Conversion Receiver Concept

The wireless industry has experienced a significant growth in the past several
years [20]. In order to have smaller products with more features, lower power
consumption, and shorter design cycles, the size and complexity of the RF section of
the product must be reduced. To explain this impact on the RF section one must
briefly examine radio receiver architecture [1].

A radio receives signals at RF containing useful voice or data information. In

order to extract this information the RF signal must be down converted by a mixing
process. A traditional method is to mix the RF signal with a signal generated by a
local oscillator (LO) to produce a signal at an intermediate frequency (IF), which
still contains the useful information. This IF signal can be amplified and filtered
with moderate quality components and then demodulated to extract the useful
information. A receiver utilizing this method is known as a superheterodyne re-
ceiver. Although the superheterodyne system was patented in 1917 by Edwin
Armstrong, it is still considered state-of-the-art in mobile communications.

However, this architecture requires two frequency synthesizers to generate

the LO signals required for the frequency conversion from RF to IF and then from
IF to baseband. As well, image-reject and IF filters are required, which have typically
been implemented with off-chip surface acoustic wave (SAW) filters.

The image-reject filter, located before the mixer, eliminates the signal at the
frequency that is twice the IF away from the RF, which would also be mixed to the IF.
The IF filter allows channel selection. The requirement of these filters increases the
cost of the receiver because of: a) the filter cost, b) higher packaging costs (a
package with 2 more pins is required because the signal must be routed off the chip to
the filter and then back onto the chip), and c) the additional space required on the
printed circuit board.
 15

Recently, two approaches have been used to overcome this. Image filtering
has been successfully implemented on-chip. A second approach is a direct down-
conversion architecture in which the radio frequency (RF) signal is mixed with a LO
signal at the radio frequency with the result that the RF signal is downconverted
directly to the baseband without an IF step and this is call direct conversion receiver
technique.

Direct conversion was invented many decades ago, has been tried many
times, and has failed almost every time. Nevertheless, this architecture has recently
become the topic of active research again, perhaps to a much greater extent than
before. Several reasons account for this renaissance [2]: 1) DCR, in principle, lends
itself to monolithic integration much more easily than do heterodyne receivers; 2)
DCR suffers much less from mismatch-induced effects than do image-reject
architectures; 3) DCR past failures arose primarily from effects that could not be
removed in discrete implementations, but may be controlled and suppressed in
integrated circuits. In other words, DCR is one of few reception techniques whose
drawbacks can be remedied through the use of only more transistors.

2.3.1 DCR Architecture

Direct conversion, also called zero-IF or homodyne conversion, is the

natural approach to downconverting a signal from RF to baseband [6]. A DCR
translates the band of interest directly to zero frequency and employs low-pass
filtering to suppress nearby interferers, as shown in Figure 2.7. The quadrature I and
Q channels are necessary in typical phase and frequency-modulated signals because
the two sidebands of the RF spectrum contain different information and result in
irreversible corruption if they overlap each other without being separated into two
phases.
 16

Figure 2.7: Direct Conversion Architecture

Suppose that the IF in a superheterodyne is reduced to zero. The LO will

then translate the center of the desired channel to 0 Hz, and the portion of the
channel translated to the negative frequency half-axis becomes the image to the
other half of the same channel translated to the positive frequency half-axis (Figure
2.8). The downconverted signal must be reconstituted by a phasing method of the
type described above, otherwise the negative-frequency half-channel will fold over
and superpose on to the positive-frequency half-channel. Zero-IF, therefore, mandates
quadrature downconversion into two arms and a vector-detection scheme.

However, this scheme does not suffer from the strong-image problem when
the image-reject downconverter is used in a nonzero IF heterodyne receiver, and the
typical gain mismatches and phase errors in the two branches cause only a small
loss in detected SNR. A lowpass filter, which is in effect a bandpass centered at
dc when the negative frequency axis is included, may be used to select the desired
channel and to reject all adjacent channels.

Therefore, RF preselection may in principle be eliminated because there is

no image channel. In practice, it is still required to suppress strong out-of-band
signals that may create large intermodulation distortion in the front-end prior to
baseband channel selection and to avoid harmonic downconversion. There is also the
advantage that if a high-order active filter is used for channel selection, it will
dissipate lower power and occupy a smaller chip area at a given dynamic range than an
 17

active bandpass filter with the same selectivity centered at a high IF. All
amplification past the front-end is also at baseband, and therefore consumes a small
power. This zero-IF scheme is also called direct-conversion. When the local
oscillator is synchronized in phase with the incoming carrier frequency, the receiver is
called a homodyne.

As early as 1924, radio pioneers had considered use of homodyne

architectures for single vacuum-tube receivers, but it was a homodyne-measuring
instrument for carrier-based telephony built in 1947 that first employed a high-
order low pass filter for channel-selection [4]. Thereafter, the concept lay dormant,
until it was revived in 1980 in the radio-paging receiver, the first miniature digital
wireless device for personal communication to attain widespread consumer use.

Figure 2.8: Spectrum before and after direct-conversion

2.3.2 DCR Design Consideration

There are a few design issues that are needed to be considered when
designing direct conversion receiver. This section will discuss about a few issues
that involved with DCR [2, 5-8].
 18

2.3.3 DC Offset

Since in a DCR architecture the downconverted band extends to zero

frequency, extraneous offset voltages can corrupt the signal and, more importantly,
saturate the following stages. To understand the origin and impact of offsets,
consider the receiver shown in figure 2.9, where the LPF is followed by an amplifier
and an analog-to-digital converter (ADC). Let us make two observations.

First, the isolation between the LO port and the inputs of the mixer and the
LNA is not perfect, i.e., a finite amount of feed through exists from the LO
port to points A and B [Figure 2.9(a)]. Called "LO leakage," this effect arises from
capacitive and substrate coupling and, if the LO signal is provided externally, bond
wire coupling. The leakage signal appearing at the inputs of the LNA and the mixer
is now mixed with the LO signal, thus producing a dc component at point C. This
phenomenon is called "self-mixing." A similar effect occurs if a large interferer leaks
from the LNA or mixer input to the LO port and is multiplied by itself [figure
2.9(b)].

Second, the total gain from the antenna to point X is typically around 100
dB so as to amplify the microvolt input signal to a level that can be digitized by a low
cost, low power ADC. Of this gain, typically 25 to 30 dB is contributed by the
LNA/mixer combination.

The problem of offset is exacerbated if self-mixing varies with time. This

occurs when the LO signal leaks to the antenna and is radiated and subsequently
reflected from moving objects back to the receiver. For example, when a car moves
at a high speed, the reflections may change rapidly.
 19

From the above discussion, we infer that DCR's require some means of
offset removal or cancellation. AC Coupling and Offset Cancellation are among
the technique proposed to overcome the problem in DC Offset. This is further
discussed in [2].

Figure 2.9: Self-mixing of (a) LO. (b) Interferers

2.3.4 I/Q Mismatch

As shown in Figure 2.1, for most phase and frequency modulation schemes, a
DCR must incorporate quadrature downcon-version. This requires shifting either the
RF signal or the LO output by 90° (Figure 2.10. Since shifting the RF signal
generally entails severe noise-power-gain tradeoffs, it is desirable to use the
topology in figure 2.10 (b). In either case, the errors in the nominally 90° phase
shift and mismatches between the amplitudes of the / and Q signals corrupt the
downconverted signal constellation, thereby raising the bit error rate. Note that all
sections of the circuit in the I and Q paths contribute gain and phase error.
 20

Figure 2.11(a) and (b) shows the resulting signal constellation with finite e or
θ. This effect can be better seen by examining the downconverted signals in the time
domain [Figure 2.11(c) and (d)]. Gain error simply appears as a nonunity scale factor
in the amplitude. Phase imbalance, on the other hand, corrupts one channel with a
fraction of the data pulses in the other channel; in essence degrading the signal-to-
noise ratio if the I and Q data streams are uncorrelated.

The problem of I/Q mismatch has been a major obstacle in discrete designs,
but it tends to decrease with higher levels of integration. The key point, however,
is that I/Q mismatch is much less troublesome in DCR's than in image-reject
architectures. A 5° phase imbalance degrades the SNR by roughly 1 dB in the
former while yielding an image rejection of only 27 dB in the latter.

Figure 2.10: Quadrature generation in a) RF path and b) LO path

 21

Figure 2.11: Effect of I=Q mismatch. Constellation (a) with gain error.; (b) with
phase error. Time-domain waveforms (c) with gain error; (d) with phase error.

2.3.5 Even Order Distortion

Typical RF receivers are susceptible to only odd-order intermodulation

effects. In direct conversion, on the other hand, even-order distortion also becomes
problematic. Suppose, as illustrated in figure 2.11, two strong interferers close to the
channel of interest experience a nonlinearity such as y(t) = a1x(t) + a2x2{t) in the
LNA. If x{t) = A1 cos ωt + A2 cos ω2t, then y(t) contains a term: a2A1A2 cos (ω1 -
ω2)t, indicating that two high-frequency interferers generate a low-frequency beat
in the presence of even-order distortion.

Upon multiplication by cos ωLo in an ideal mixer, such a term is translated

to high frequencies and hence becomes unimportant. In reality, however, mixers
exhibit a finite direct feedthrough from the RF input to the IF output. For example,
in the single-balanced mixer of Figure 2.12, mismatches between M2 and M3 and
 22

the deviation of the LO duty cycle from 50% create asymmetry in the circuit, thereby
producing an output signal such as vRF(t)(a + AcosωLo). Thus, a fraction of VRF(t)
on the order of 1% in IC technologies—appears at the output with no frequency
translation.

Another manifestation of second-order nonlinearity is the second harmonic of

the desired RF signal, which is downconverted to the baseband if mixed with the
second harmonic of the LO output (Figure 2.13). This effect arises for higher
harmonics as well, but it is negligible in differential mixers because the magnitude of
the harmonics of both the RF signal and the LO is inversely proportional to the
frequency.

Figure 2.12: Single Balanced Mixer

Figure 2.13: Downconversion of signal harmonics.

 23

2.3.6 LO Leakage

In addition to introducing dc offsets, leakage of the LO signal to the antenna

and radiation therefrom creates interference in the band of other receivers [3]. Each
wireless standard and the regulations of the Federal Communications Commission
(FCC) impose upper bounds on the amount of in-band LO radiation, typically
between -50 and -80 dBm. The issue is less severe in heterodyne and image-
reject mixers because their LO frequency usually falls out of the reception band.

The problem of LO leakage becomes less serious as more sections of RF

transceivers are fabricated on the same chip. With differential local oscillators, the
net coupling to the antenna can approach acceptably low levels.

2.4 Active Integrated Antenna (AIA)

The role of antennas is increasing and diversifying as the wireless

applications proliferated. Active integrated antennas are new technology that
integrates planar antennas with active solid state devices so that a number of
interesting functions can be accomplished [21]. This section will introduce some
basic concept of AIA and some previous research on AIA with direct conversion
technique.
 24

2.4.1 Definition of AIA

The term Active Integrated Antenna (AIA) is used to classify a combined

antenna and front end where the antenna and active device interact to produce the
overall circuits response. Viewed from the antenna point of view the AIA is a device
that possesses built-in signal and wave processing capabilities such as mixing,
amplification and detection. From a microwave circuit viewpoint the AIA is an
active circuit where some I/O ports are fiee-space rather than conventional 50 ohm
interfaces. A typical AIA would consist of active devices such as:-IMPATT or Gunn
diodes; Schottky diodes; MESFET, pHEMT, HBT and other 3 terminal devices.
These would be linked (using microstrip or coplanar transmission lines) to a range of
planar antennas such as:- dipoles; slots; patches; bow-ties; slot-rings etc [22]. The
significant difference between these antennas and traditional antennas connected to
active fiont-ends is the dependence of the antennas electromagnetic performance on:-
the properties of the detector/source; on the way it is mounted in the planar circuit;
and on how this circuit is matched to the planar antenna

2.4.2 Previous research on AIA

There are several research have implemented AIA with direct conversion
detection. Several papers that have been referred for implementation of this AIA are
on [5-8]. In [5-6], two active integrated antennas are implemented to act as direct-
conversion receivers. This is shown in figure 2.14. These active antennas can be
applied for Doppler frequency detection, I&Q demodulation and direction finding.
They used direct conversion detection principle which direct-conversion receiver or
I&Q demodulator, is shown in figure 2.15. It is assumed that a modulated signal,
I(t)~coso,t+Q(t)~sinw,t, is received at the input port. The local oscillator (LO)
frequency is exactly tuned to the carrier frequency and is divided into two branches
with a 90" phase difference. When a small voltage is biased on mixer, for example
 25

Schottky diode, the output of diode is dominated by a square term. For verification,
baseband signal have been generated and detected at both the in phase and
quadrature branches of the modulation signal. This 1 MHz sinusoidal wave, can be
detected at the oscilloscope

Figure 2.14: Two-element active antenna configuration

Figure 2.15: Direct Conversion Receiver

 26

In [7], using EHMs based on a pair of APDPs, the direct conversion circuitry
is realized to provide both I/Q phase channels. The direct conversion circuitry is
integrated with a 40-GHz planar patch antenna with impedance matched to 50Ω.
With two such front-ends, a communication link including a transmitter and receiver
is built. The circuit architecture is shown in figure 2.16. The proposed approach has
a threefold advantage. First, directly integrating the antenna with the front-end RF
circuits realizes a compact millimeter-wave front-end and reduces the
interconnection loss between the antenna and circuits, which is an important issue at
millimeter-wave frequencies. Secondly, the circuit provides the direct conversion
capability for digitally modulated signals, which eliminates the need of items such as
an IF mixer, image rejection filters, and saves printed circuit board space]. More
importantly, the existence of I/Q channels for direct conversion is suited for various
frequency- and phase-modulation systems such as binary phase-shift keying (BPSK),
QPSK, QAM, frequency-shift keying (FSK), etc. Furthermore, I/Q channels can
naturally

Figure 2.16: Circuit architecture of the integrated antenna with direct conversion
circuitry
 27

In [8], a compact active ring antenna integrated with diodes for direct
conversion, or zero-IF detection, is implemented. The circular aperture ring antenna
exhibits a wide bandwidth and a high gain performance. The ring can act as a phase
shifter to provide the necessary 90 degrees characteristics to operate with I/Q signals
for direct conversions. Two Schottky diodes can be connected to the ring structure
and are used as a mixer. The frequency focus is at 2.44GHz, which is of particular
interest for home networking communication systems. The construction of this AIA
ring antenna/phase is shown in figure 2.17.

Figure 2.17: Ring AIA construction

2.5 Summary

In this chapter, the basic concept of several kinds of receiver has been
reviewed. The focused of the reviewed are mainly on Direct Conversion Receiver
(DCR). DCR architecture and design consideration of DCR is presented in this
review. In addition of DCR, active integration antenna (AIA) concept is also being
discussed here. Some previous research is also presented in this chapter.
 CHAPTER 3

DESIGN AND SIMULATION OF DCR

3.1 Introduction

This chapter will discuss the design, simulation and fabrication of two types
of DCR components which are microstrip dipole antenna and 90 degree hybrid
coupler. Besides that, selection of another two components of DCR which are
Voltage Tuned Oscillator (VTO) and diode mixer will be discussed here. Simulation
of DCR using ADS software is also presented here.

The design process begins with calculation and followed by simulation and
fabrication. Computer Aided Design (CAD) tools such as Advanced Design System
(ADS) software, MathCAD and AutoCAD is required to fulfill the design task.

3.2 Design Flow Chart

The design flowchart is shown in figure 3.1. The process is beginning with
calculation for the formula in microstrip dipole antenna and hybrid coupler. Next, is
to do some simulation using ADS software. After simulation is successfully
implemented, these two components of DCR are tested for their own performance.
Suitable selection of VTO and diode mixer is also needed before we can integrate it
to perform DCR.
 29

Simulation of DCR circuit is also implemented in ADS software. It is tested

to detect baseband signal transmitted from I and Q modulator. Part by part
integration to perform DCR circuit is then tested to detect baseband signal. After this
process has successfully detected baseband signal, all of this DCR components are
then integrated on one circuit board (FR-4 Board). DCR circuit implementation is
complete, when its successfully detected baseband signal from signal generator.

Design of Microstrip Dipole Integr Selection of VTO

Antenna & Hybrid Coupler ation &
Mixer Diode

Simulation
Simulation
NO
NO OK
YES
OK Fabrication
YES
Measureme
Fabrication t

Tested
OK?
Tested
OK?

DCR Circuit
Successful

Figure 3.1: Design Flow Chart

3.3 Design and Selection of DCR Components

This section will discuss on the design and selection of all four DCR
components.
 30

3.3.1 Microstrip Dipole Antenna

The approach proposed in this part is to design microstrip dipole resonance at

2.4 GHz frequency band. Figure 3.2 shows the structure of a microstrip dipole of
length L, width W and gap G that were used in simulation. The proposed antenna
element is printed on a FR4 substrate with a dielectric constant of 4.7, a thickness of
1.6 mm and a conductor loss of 0.019. The two hatched rectangular pieces in Figure
3.2 are copper on the top of the substrate. Each of it is connected with the microstrip
bend. The gap between the two pieces is G and the microstrip dipole is fed at the
middle of the gap. One piece of the hatched is fed with connector and another one is
connected to the ground.

Figure 3.2: Microstrip Dipole Antenna Layout

Microstrip dipole of rectangular hatched or rectangular geometry as shown in

figure 3.2 can be designed for the lowest resonant frequency using transmission line
model. The formula to calculate the value of λ, L2 and W can be found through
formulation as follows [23]:

The effective dielectric constant (εe) constant of a microstrip line:

(3.1)
 31

Where εr = Dieletric Constant

d = substrate thickness
W= width of microstrip line
(Approximation is made for the simulation)
The length (L1 and L2) of microstrip line using formula:

λ=
c
f ε eff
(3.2)

where λ= wavelength
C= velocity of light
f = frequency

Thus
L1= L2 = λ/4 (3.3)

The simulation process is done using Metod of Moment ( MoM). The

environment of MoM using ADS software is shown in figure 3.3. Optimization has
been done by varying the calculated parameters and to get a better result of S11
parameter.
 32

Figure 3.3: Layout Environment of Microstrip Dipole Antenna using Method of

Moment (MOM) simulation

The length of each hatched rectangular is about quarter-wavelength. In this

case the length of rectangular hatched, L1=L2= λ/4=16.52 mm and the gap between
the two pieces, G = 0.9mm. At the designed frequency, approximation of the width
W is made and it is equal to 2.90 mm. Overall, the length of the dipole is about, L =
47mm. In addition the microstrip bend is added between the two rectangular hatched
which has length and width is equal to 7 mm. The photograph of the fabricated
microstrip dipole prototype can be shown in figure 3.4
 33

Figure 3.4: Fabricated Microstrip Dipole.

The design procedure of microstrip dipole antenna design can be carried out
in a few steps as follows:
• The resonance frequency is chosen and for this case resonance frequency at
2.4GHz is chosen.
• Calculate the correct dipole dimension (L1, L2 and W) by using microstrip
transmission line formula.
• Connect the rectangular hatched with microstrip bend and chooses the suitable
gap G between the two hatched pieces on the substrate.
• The gap between the two traces is G and the microstrip dipole is fed at the middle
of the gap.

3.3.2 Quadrature 900 Hybrid Coupler

Quadrature hybrids are 3 dB directional couplers with a 90° phase

difference in the outputs of the through and coupled arms. This type of hybrid is
often made in microstrip or stripline form as shown in figure 3.5, and is also
known as a branch-line hybrid. Other 3 dB couplers, such as coupled line couplers
or Lange couplers, can also be used as quadrature couplers [24].
 34

With reference to Figure 3.5 the basic operation of the branch-line coupler
is as follows. With all ports matched, power-entering port 1 is evenly divided
between ports 2 and 3, with a 90° phase shift between these outputs. No power is
coupled to port 4 (the isolated port).

Figure 3.5: Geometry of Branch-line coupler

The same material specification is used to design this hybrid coupler. Again,
the important parameters that are needed for the design are width (W) and length (L).
There are two calculation value are needed for Zo = 50 Ω and Zo = 50 /√2 Ω. The
calculation value is shown in MathCAD Professional in figure 3.6 and 3.7. The
value of width (W1) = 2.91 mm and (W2) = 5mm while the value of length (L1) and
(L2) = 16.65mm.

ADS software also has a built in Microstrip line calculator. This is shown in
figure 3.8. The value of width and length will be dependent on the formula utilized
and as a whole will be estimation. What’s important to note is, that the value of λg
will not vary much with the change in width from the respective formula. From the
line calculator, we get the value of width (W1) = 2.91 mm and (W2) =16.52 mm
while the value of length (L1) = 16.52 mm and (L2) = 16.08 mm. This is shown in
figure 4.8 and this parameters are inserted for the design of hybrid coupler.
 35

Figure 3.6: Calculation of width and length for Zo = 50 Ω.

Figure 3.7: Calculation of width and length for Zo = 50 /√2 Ω.

 36

Figure 3.8: Line Calculator of width and length for Zo=50 and Zo=50 /√2Ω

The simulation process is done using Metod of Moment ( MoM). The

environment of MoM using ADS software is shown in figure 3.9. Optimization has
been done by varying the calculated parameters and to get a better result of S
parameter. The photograph of the fabricated hybrid coupler prototype can be shown
in figure 3.10
 37

Figure 3.9: Layout Environment of Quadrature 900 Hybrid Coupler using Method
of Moment (MOM) simulation

Figure 3.10: Fabricated 90 degree hybrid coupler

 38

3.3.3 Voltage Tuned Oscillator (VTO)

A suitable VTO must be selected before it can be integrated to perform DCR

circuit. Frequency of interest here is at 2.4 GHz, which mean suitable VTO must be
selected within that range. Oscillator that is used in this project is Agilent’s Model
VTO-8150. The voltage can be tuned up to 2.5 GHz frequency. The Tuning Voltage
is shown in figure 3.11. From, the graph is shown that the tuning voltage is about 34
Volt at 2.4 GHz and power output is about 13 dBm. The picture of VTO is shown in
figure 3.12. Overall specification is shown in Appendix A.

Figure 3.11: VTO–8150 Power Output, Frequency and Modulation Sensitivity vs.
Tuning Voltage.

Figure 3.12: VTO-8150

 39

3.3.4 Diode Mixer.

Mixer circuits may be used whenever there is a need to translate signals

between frequency bands. When two signals of differing frequencies are fed into
a non-linear element such as a diode, numerous intermodulation products are
produced, including the sum and difference frequencies of the signals. Mixer
circuits are often configured in the form of balanced mixers with two mixer
diodes connected to two mutually isolated ports of a 3dB hybrid network [22].
Hybrids that are used in this connection are invariably one of two types: the 90° or
quadrature hybrid and the 180° hybrid.

For this project, diode mixer that has been chosen to be connected with 90°
hybrid coupler is schottky diodes Model HSMS-8101. The diode is biased at 0.15
as shown in figure 3.13. The photograph of the diodes that has been fabricated
with microstrip line is shown in figure 3.14 and the overall specification can be
found in Appendix B.

Figure 3.13: Typical Forward Current vs. Forward Voltage at Three Temperatures.
 40

Figure 3.14: Fabricated diode mixer with microstrip line

3.4 Simulation of DCR Circuit

All of DCR components are then integrated to perform DCR circuit. This is
done by using circuit simulation environment as shown in figure 3.15. This design is
divided into 2 sections. One section is for modulating part and the other section is
for the receiving section of AIA DCR circuit.

For the modulating section, I & Q modulator is used to transmit signal. I & Q
signal are generated in bits. The signals are then mixed with oscillator and
modulated through MOD module. More details figure of modulating section is
shown in figure 3.16.

At the receiving part, the signals from modulating part are then propagate
through AIA DCR circuit. Its then demodulated and mixed with oscillator at the
mixer diodes. The baseband signal will be detected at the two output port. I signal
will be detected at the I output port and Q signal will be detected at Q output port.
Details figure of demodulating part is shown in figure 3.17
Figure 3.15:

MO DULATED SIG NAL G ENERATION

P_1Tone
LO_ref1 R Fin
N um=1
Z=50 Ohm
P=dbmtow (0) Qdua
IQ_ModTuned
Freq=2.4 GH z
Circuit Simulation Design of DCR

Idua
MOD1 V tB itS eq MLIN
Fnom=2.4 GHz Qs atuS RC3 AIA DIRECT CONVERSION RECEIVER
TL9
V tB itS eq Is atu Rout=50 Ohm V low=-.005 V
S RC1 LP F_RaisedCos
LP F_RaisedCos V high=.005 V
Subs t="MSub1" O UTPUT1
V low=-.005 V LP F1 LP F3 Rate=S ymRate W =2.910190 mm
V high=.005 V A lpha=0.35
A lpha=0.35 Rise=1 nsec L=20 mm
t MSOBN D _MD S
Rate=S ymRate t S ymbolRate=S ymRate ymRate
S ymbolRate=S Fall=1 nsec
Rise=1 nsec DelayS ymbols=0
DelayS ymbols=0 B itS eq="0101" Bend1
Fall=1 nsec E xponent=0.5
E xponent=0.5 Subs t="MSub1"
B itS eq="1010" DutyCycle=1000
DutyCycle=1000
Iout
RF
W =2.910190 mm
S incE =no
S incE =no
MLIN MLIN
MLIN
TL1 TL7 Term
TL5 MTEE_AD S MTEE_AD S
Subs t="MSub1" Subs t="MSub1" Iout
Subs t="MSub1" Tee1 Tee4 Num=3
W =5.000860 mm W =2.910190 mm
W =2.910190 mm Subs t="MSub1" L=13.17211 mm Subs t="MSub1" L=10 mm Z=50 Ohm
L=10 mm W 1=2.910190 mm W 1=5.000860 mm
W 2=5.000860 mm W 2=2.910190 mm
W 3=2.910190 mm W 3=2.910190 mm di_hp_H SMS8101_20000301
D4
VARIABLE PARAMETER
MLIN MLIN
M eas
Meas Eqn TL4 TL3
Eq n
Meas 1 Subs t="MSub1" Subs t="MSub1"
R Fin_Fund=R Fin[1] W =2.910189 mm W =2.91019 mm
I_Fund1=Is atu[0] L=16.62 mm L=16.62 mm
I_Fund2=Idua[0] ENVELOPE
Q_Fund2=Qdua[0]
Q_Fund1=Qs atu[0] E nvelope
E nv1
Iout_BB=real(Iout[0]) Freq[1]=2.4 GHz LOCAL OSCILLATO R (LO )
Iout_BB1=Iout[1] Order[1]=5
Qout_BB=real(Qout[0]) FundOversample=1
OUTPUT2
Qout_BB1=Qout[1] S top=S topTime
S tep=TimeS tep Qout
LO Term
MSub Qout
P_1Tone MLIN MTEE_AD S MLIN MTEE_AD S MLIN
Num=4
MSU B Va r VAR
POR T2 TL6 Tee2 TL2 Tee3 TL8 Z=50 Ohm
MSub1
Eq n
V A R1
N um=2 Subs t="MSub1" Subs t="MSub1" Subs t="MSub1" Subs t="MSub1" Subs t="MSub1"
H =1.6 mm S ymRate=10 MHz Z=50 Ohm W =2.910190 mm W 1=5.000860 mm W =5.000860 mm W 1=2.910190 mmW =2.910190 mm
Er=4.7 TimeS tep=1/(10* S ymRate) P=dbmtow (8) L=15 mm W 2=2.910190 mm L=13.17211 mm W 2=5.000860 mmL=10 mm
S topTime=1000* TimeS tep Freq=2.4 GH z W 3=2.910190 mm W 3=2.910190 mm
Mur=1
C ond=1.0E+50 di_hp_H SMS8101_20000301
H u=3.9e+034 mil D5
T=0 mil
TanD =0.019
R ough=0 mil

41
 42

MODULATED SIGNAL GENERATION

P_1Tone
LO_ref1
Num=1
Z=50 Ohm
P=dbmtow(0) Qdua
IQ_ModTuned
Freq=2.4 GHz Idua
MOD1 VtBitSeq
Fnom=2.4 GHz QsatuSRC3
VtBitSeq Isatu Rout=50 Ohm Vlow=-.005 V
SRC1 LPF_RaisedCos
LPF_RaisedCos Vhigh=.005 V
Vlow=-.005 V LPF1 LPF3 Rate=SymRate
Vhigh=.005 V Alpha=0.35
Alpha=0.35 Rise=1 nsec
t
Rate=SymRate t SymbolRate=SymRate
SymbolRate=SymRate Fall=1 nsec
Rise=1 nsec DelaySymbols=0
DelaySymbols=0 BitSeq="0101"
Fall=1 nsec Exponent=0.5
Exponent=0.5
BitSeq="1010" DutyCycle=1000
DutyCycle=1000
SincE=no
SincE=no

Figure 3.16: Modulated Signal Generations

MLIN
TL9 AIA DIRECT CONVERSION RECEIVER
Subst="MSub1" OUTPUT1
W=2.910190 mm
L=20 mm
MSOBND_MDS
Bend1
Subst="MSub1" Iout
W=2.910190 mm
RF
MLIN MLIN
MLIN
T L1 T L7 Term
T L5 MT EE_ADS MT EE_ADS
Subst="MSub1" Subst="MSub1" Iout
Subst="MSub1" T ee1 W=5.000860 mm T ee4 W=2.910190 mm Num=3
W=2.910190 mm Subst="MSub1" L=13.17211 mm Subst="MSub1" L=10 mm Z=50 Ohm
L=10 mm W1=2.910190 mm W1=5.000860 mm
W2=5.000860 mm W2=2.910190 mm
W3=2.910190 mm W3=2.910190 mm di_hp_HSMS8101_20000301
D4

MLIN MLIN
T L4 T L3
Subst="MSub1" Subst="MSub1"
W=2.910189 mm W=2.91019 mm
L=16.62 mm L=16.62 mm

LOCAL OSCILLATOR (LO)

OUTPUT2
Qout
LO Term
P_1T one MLIN MT EE_ADS MLIN MT EE_ADS MLIN Qout
PORT 2 T ee2 T ee3 Num=4
T L6 T L2 T L8 Z=50 Ohm
Num=2 Subst="MSub1" Subst="MSub1" Subst="MSub1" Subst="MSub1" Subst="MSub1"
Z=50 Ohm W=2.910190 mm W1=5.000860 mm W=5.000860 mm W1=2.910190 mm W=2.910190 mm
P=dbmtow(8) L=15 mm W2=2.910190 mm L=13.17211 mm W2=5.000860 mm L=10 mm
Freq=2.4 GHz W3=2.910190 mm W3=2.910190 mm
di_hp_HSMS8101_20000301
D5

Figure 3.17: AIA Direct Conversion Receiver Circuit

 43

3.5 Fabrication

This section will discuss in general about the fabrication process of DCR circuit.
Although the fabrication process involved with fabrication of DCR components part
by part, this section will discuss the fabrication of final DCR circuit.

The fabrication processes are done manually using an etching technique. FR4
microstrip board with 1.6 mm thickness is used. Figure 3.18 show the flow chart of
the fabrication process.

Layout Prepared

Ultraviolet Process

Film Remove Process

Etching Process

Soldering Process

Figure 3.18: The flow chart of fabrication process

 44

Designed layout is generated from ADS layout tools. This is shown in figure
3.19. Small pad is included to connect it with VTO pin. All microstrip line used in
this layout is made of double-sided FR4 material.

Figure 3.19: The Layout generated in ADS layout environment

The layout in figure 3.19 is exported to DXF file format for printing. Using
AutoCAD, the DXF (drawing enhancement file) will be printed on transparency in
actual size. Modification is needed to ensure the layout is very clear on the
transparency.

The upper side of FR4 microstrip board is exposed to ultraviolet for 135
seconds using layout from transparency. This ultraviolet (UV) process is done in a
 45

dark room to avoid the film layer exposed to light; instead Red Bulb is used for
lighting purpose. After the UV process is completed, the microstrip board is put into
a small square container, which contained a universal developer liquid solution (50 g
universal developer for 1 liter water). Then, the container is sieve to remove the
exposed film layer for about 2 minutes. The sieved microstrip board is put into
another small square container, which contains a stain remover liquid. Ferric
Chloride chemical substance is selected as the stain remover agent (100g Ferric
Chloride for 200 ml water). Again, the container is sieved to remove the uncovered
copper layer. The sieved process took about 30 minutes to 1 hour to complete.
Lastly, the soldering process commenced on the work piece.

3.5 Summary

This chapter is about DCR circuit design process at 2.4 GHz frequency. DCR
circuit is built from part by part design of four types of DCR components which are
microstrip dipole antenna, 90 degree hybrid coupler, VTO and mixer diode. This
four type of DCR components are then integrated to perform DCR circuit. The
designed process begins with calculation then followed by simulation. The designed
DCR is then fabricated. Brief description of ADS in performing circuit
development, simulation setup and data analysis is covered.
 CHAPTER 4

RESULTS AND DISCUSSION

4.1 Introduction

This chapter discusses the result obtain from the research works. The
discussion covers the results of S parameter of microstrip dipole antenna and hybrid
coupler. Both simulation and measurement results will be compared and analyzed.
Finally, the results of simulation and measurement of DCR circuit will be analyzed.

4.2 DCR Components Simulation & Measurement Results

This section will discuss on the results of microstrip dipole antenna and 90
degree hybrid coupler.
 47

4.2.1 Microstrip Dipole Antenna Results

The result of microstrip dipole antenna has been discussed in term of

bandwidth response and return loss of the antenna. The simulation and measurement
results of the antenna return loss is shown in figure 4.1. The resonance of the
antenna can be seen by observing the dip in the return loss. The dip of antenna can
be seen at 2.4 GHz frequency. The bandwidth from simulation result is 13.4% and
for measurement is about 23.85 %. The experimental result shows the frequency has
been shifted down by 100 MHz. From the graph, it is shown that the bandwidth of
measurement result is much higher than the simulation result.

Simulation and Measurement of

Microstrip DipoleAntenna

0
-2 Measurement
-4
MAgnitude (dB)

Simulation
-6
-8
-10
-12
-14
-16
-18
2 2,2 2,4 2,6 2,8 3
Frequency (GHz)

Figure 4.1: Input Return Loss for Microstrip Dipole Antenna.

 48

4.2.2 Quadrature 900 Hybrid Coupler Results

In this section the results of measurement of hybrid coupler has been

discussed in term of S parameter and output phase at the two output port.

S parameter measurement of the hybrid coupler is shown in figure 4.2 and the
output phase between port 2 and port 3 is shown in figure 4.3. From figure 4.2 a,
measurement return loss, S11 = -40.1 dB and the isolation between port 1 and port 4,
S14 = -24.3 dB. The gain at the output port 2, S12 = -4.59 dB and the gain at the
output port 3, S13 = -4.4 dB. While for simulation results in figure 4.2b it shown that
simulated return loss, S11 = -32.809 dB and the isolation between port 1 and port 4,
S14 = -41.775 dB. The gain at the output port 2, S12 = -3.322 dB and the gain at the
output port 3, S13 = -3.838 dB.

Figure 4.3 shows a 900 phase different between port 2 and port 3. Overall the
measurement results of S parameters follow the simulation results. This proof that
the hybrid coupler can be integrated with dipole antenna and is suitable for I and Q
signals that keep 900 phase different.
 49

S-PARAMETER
0
m4
m3
-5

-10

-15
m4
freq=2.400GHz
Mag. [dB]

-20
dB(S(1,2))=-3.322
m3
-25 freq=2.400GHz
dB(S(1,3))=-3.838
m2
-30 freq=2.400GHz
m2
dB(S(1,1))=-32.809
-35 m1
freq=2.400GHz
dB(S(1,4))=-41.775
-40 m1

-45
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2
Frequency (GHz)

a) Simulation Result

S-Parameter of Hybrid Coupler

0
-5
-10
M a g n itu d e (d B )

-15
-20
-25 s11
-30 s12
-35 s13
s14
-40
-45
2 2,1 2,2 2,3 2,4 2,5 2,6 2,7 2,8 2,9 3 3,1 3,2
Frequency (GHz)

b) Measurement

Figure 4.2: Hybrid Coupler S parameter results a) Simulation b) Measurement

 50

Output phase
150
m5
100 m5 freq=2.400GHz
phase(S(1,2))=80.561
50 m6
Phase [deg]

freq=2.400GHz
m6 phase(S(1,3))=-8.708
0

-50

-100

-150
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2
Frequency (GHz)

a) Phase different for simulation

Output phase (Measurement)

250
200
150
Phase (S31)
Phase (Degree)

100
Phase (S21)
50
0
-50
-100
-150
-200
-250
2,39 2,4 2,41 2,42 2,43 2,44 2,45
Frequency (GHz)

a) Phase different for Measurement

Figure 4.3: Output phase different at port 2 and port 3 for
a) Simulation b) Measurement
 51

4.3 AIA DCR Simulation Results

The modulated source data is generated using I and Q modulator. I and Q

modulator have three input ports. One is connected to the carrier and the other two
go to the in-phase and quadrature branches. The modulated signal is then
demodulated through the coupler and mix out with LO at the schottky diodes. The
baseband signal is then detected at the two end of the output port as what has been
described in previous chapter.

The simulation of the schematic is base on circuit envelope simulation. The

baseband signal detected at the port 1 and port 2 follows the sinusoidal wave that
generated at the I and Q modulation source. It shown that this schematic design is
suitable for I and Q demodulation. The baseband signals that have been detected is
shown in figure 4.4. The upper part of the graph had shown the original I & Q signal
and the lower part shown the detected. It’s also shown that the detected signal
follows the original sinusoidal wave but the amplitude is attenuated. Figure 4.5
shows the demodulated spectrum that has been detected throughout the receiver. The
carrier and sidebands of the spectrum can be clearly observed.
 52

-0.014

c i rc u i t_ Ii n
-0.016

-0.018

-0.020

-0.034696

-0.034698
c i rc u i t_ Io u t

-0.034700

-0.034702

-0.034704

-0.078
c i rc u i t_ Qi n

-0.080

-0.082

-0.084

-0.034695
c i rc u i t_ Qo u t

-0.034700

-0.034705
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.5

time, usec

Figure 4.4: Comparison of original baseband signal from modulator and detected
baseband signal at I/Q output

D emodulated S pectrum
10 m6
0
m6
fre q = 0 .0 0 0 0 Hz
-1 0
d B m (sp e ctru m )= 3 .3 6 8

-2 0 m7
fre q = -5 .0 0 0 M H z
-3 0 d B m (sp e ctru m )= -5 2 .8 9 3
-4 0
m8
m7 m8 fre q = 5 .0 0 0 M H z
dBm(spectrum)

-5 0
d B m (sp e ctru m )= -5 2 .9 0 3
-6 0

-7 0

-8 0

-9 0

-1 0 0

-1 1 0

-1 2 0

-1 3 0

-1 4 0
-5 0 -4 5 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50

f req , MH z

Figure 4.5: Detected demodulated spectrum at output port

 53

4.4 AIA DCR Measurement Results

The fabricated of Direct Conversion Receiver circuit is shown in figure 4.6.

All of the DCR components are integrated on one FR-4 Board. The experimental
setup is shown in figure 4.7. Synthesizer Signal Generator is used to transmit the
baseband signal. The baseband signal is than radiated from monopole antenna. The
DCR circuit is placed in front of the transmitting antenna with 1 meter separation.
When the diodes are forward biased by a voltage 0.1 -0.25 V, the LO signal will be
mixed with the RF signals received by microstrip dipole antenna. The down
conversion components of the mixer include all the baseband signals information.

Figure 4.6: Fabricated Direct Conversion Receiver

1 kHz sinusoidal baseband signal have been generated and detected at DCR
circuit. The baseband signal can be detected using oscilloscope. The baseband
signal at the output port 1 and port 2 of the circuit can be seen as figure 4.8. Since the
transmitting side does not use I/Q modulator, the signal detected at output port 1 and
2 are the same.
 54

Figure 4.7: Experimental setup of DCR circuit

From figure 4.8, it can be observed that the sinusoidal wave that detected at
the two output ports have the same voltage peak to peak which is 4 Volt. From the
figure, it also shown that the output ports have the same sinusoidal wave. Figure 4.9
shows the comparison of original transmitted signal with the detected baseband
signal. It is shown that the original sin wave signal is measured on channel 1 of the
oscilloscope, while the other channel is measured for DCR circuit output port. The
original signal Vpp is equal to 0.75 V while the detected baseband signal Vpp is
equal to 0.75 mV. It is shown that the sin wave signal is attenuated from the original
signal. As conclusion, this designated DCR circuit has successfully implemented
when it successfully detected baseband signal using oscilloscope. The objective of
this thesis has been achieved.
 55

Freq : 1 kHz
I output : Vpp= 4 mVolt
Q output : Vpp = 4 mVolt

Figure 4.8: Detected baseband signal at I & Q Output Port

Freq : 1 kHz
Output channel 1 : Vpp= 0.75 Volt
Output channel 2: Vpp = 0.75m Volt

Figure 4.9: Comparison of transmitted sinusoidal wave and detected baseband

signal
 56

4.5 Summary

A low cost and compact integrated receiver at 2.4 GHz band for direct
conversion has been proposed. The proposed microstrip dipole antenna with a
narrow width is easy to implement. The hybrid coupler provides the required 900
characteristics to operate with the I and Q signal for direct conversion. Overall, the
microstrip dipole antenna, coupler and mixer can be integrated into one board which
allows a low cost receiver. Simulation and measurement for testing DCR circuit have
been implemented as discussed in this chapter. In experimental setup, 1 kHz
sinusoidal signal act as a baseband have been generated and modulated using signal
generator. The demodulated signal is detected using direct conversion receiver
circuit and the baseband signal at the output ports is successfully detected using
oscilloscope.
 CHAPTER 5

CONCLUSION

Five types of receiver have been discussed in this thesis. However, Direct
Conversion Receiver (DCR) techniques have been chosen to be implemented with
Active Integrated Antenna (AIA). The research work has design a DCR circuit for
frequency at 2.4 GHz and circuit simulation was done in ADS. The proposed
microstrip dipole antenna with a bandwidth up to 24% bandwidth is implemented.
The hybrid coupler provides the required 90° characteristics to operate with the I and
Q signal for direct conversion. Two schottky diodes are connected at the end of the
coupler’s output ports are used as the mixer.

Overall, the microstrip dipole antenna, coupler and mixer can be integrated
into one board which allows a low cost receiver. In the simulation mode, sinusoidal
wave have been successfully modulated and detected throughout the receiver. In the
measurement mode, the designed DCR circuit is tested to receive baseband signal
from Synthesized Signal generator. This DCR circuit with AIA has successfully
developed when it successfully detected baseband signal using oscilloscope.
 58

5.1 Future Work

The following suggestions are made to possibly complement and further

extend results:

• Use I&Q Modulator to transmit baseband signal. This can be used to

detect I & Q signal at the DCR circuit
• Design of Direct Conversion Transceiver in one circuit board.
Implementation of transceiver circuit in one circuit board is needed. This
idea is used for RF ID application.
• Use different type of antenna to perform AIA with direct conversion
technique. Different type of antenna such as circular patch antenna,
triangular patch antenna and others type of antenna can be implemented
as AIA and perform DCR.

5.2 Summary

This chapter concluded the research work. Some extension work is already
under progress. The research project will further improved and enhanced as
explained in the previous section suggestion.
 59

REFERENCES

1. Abid, A.A, “Direct Conversion radio transceiver for digital communication”,

IEEE J. Solid-State Circuits,1995,30, (12),pp.1399-1410.

2. Behzad Razavi:, “RF Microelectronics”, Prentice Hall PTR, 1998

3. Behzad Razavi, “Design Considerations for Direct Conversion Receiver”,

IEEE Transaction on Circuits and System-II: Analog & Digital
Processing, vol 44, no 6,pp 428-435, June 1997

4. King RJ, "Microwave homodyne systems",. IEEE 1978, Peter Peregrinus Ltd

5. Ma, G., Hall, P.S., Gardner,P., and Hajian,M, “ zero-IF detection Active
Antenna”, Electronic Letters, 2001,37, (1), pp,3-4.

6. Hall,P.S., Gardner.,P., and Ma, G., “Active Integrated Antenna”, IEICE

Trans. Commun., 2002, E85-B, (9),pp. 1661-1666.

7. Park, J.Y., Jeon, S.S., Wang, Y., and Itoh, T., “Integrated Antenna with
Direct Conversion Circuitry for Broad-Band Milimeter- Wave
Communications”,IEEE Tran. Microwave Theory Techniques, Vol. 51,
No.5, pp 1482-1488, May 2003

8. J.C.Liu, C. S. Cheng, H. C. Chen and P., C, Chen, “Active Integration Ring

Antenna/phase shifter for direct conversions”, IEE Proc.- Microw.
Antennas Propag., Vol. 151, No 4, pp 357-361,August 2004

9. Kai Chang, Robert, A. York, , Peter S. Hall, and Tatsuo Itoh, “Active
Integrated Antennas”, IEEE transactions on microwave theory and
techniques, Vol.50, No.3, ,pp 937-945 Mar 2002
 60

10. Zhijun Zhang, M.F. Iskander, J.C. Langer, J. Mathews, “Wideband dipole
antenna for WLAN” , IEEE Antennas and Propagation Society
Symposium 2004, Volume 2, 20-25 June 2004, page(s):1963 – 1966.

11. L. Lessing, "Man of High Fidelity: Edwin Howard Armstrong, a Biography,"

Bantam Books, New York, 1969.

12. F.M. Colebrook, "Homodyne," Wireless World and Radio Rev., 13, 1924,
p.774.

13. D.G. Tucker, "The Synchrodyne," Electronic Engng, 19, March 1947,
pp. 75-76.

14. D.G. Tucker, "The History of the Homodyne and the Synchrodyne," Journal
of the British Institution of Radio Engineers, April 1954.

15. S.J. Franke, "ECE 353 Radio Communication Circuits," Department of

Electrical and Computer Engineering, University of Illinois, Urbana, IL,
1994.

16. J.C. Rudell, et al., "Recent Developments in High Integration Multi-standard

CMOS Transceivers for Personal Communication Systems," International
Symposium on Low Power Electronics and Design, 1998.

17. J.C. Rudell, "Issues in RFIC Design," lecture notes, University of California
Berkeley/National Technological University, 1997.

18. R. Hartley, "Single-sideband Modulator," U.S. Patent No. 1666206, April

1928.

19. D.K. Weaver, "A Third Method of Generation and Detection of Single
Sideband Signals," Proceedings of the IRE, Vol. 44, December 1956, pp.
1703-1705.
 61

20. Paul Laferiere ,Dave Rahn, Calvin Plett and John Rogers” A 5 GHz Direct
Conversion Receiver With DC Offset Correction” IEEE Transaction on
ISCAS ,2004, pp. 269-272

21. Tatsuo Itoh, “Recent Progress in Active Integrated Antenna” , Microwave

Conference and Exhibition, 27th European Volume 2, September 8-12,
1997, Page(s):992 – 997

22. Parini, C.G.;, “What are Active Integrated Antennas?:-Can Successful

CAD be Achieved?” High Performance Electron Devices for Microwave
and Optoelectronic Applications, 1999. EDMO. 1999 Symposium on 22-
23 Nov. 1999, Page(s):53 - 57, 58a-b

23. David M.Pozar, “Microwave Engineering”,John Wiley & Sons, Inc,1998

24. Dr E.H Fooks and Dr R.A Zakarevicians, Microwave Engineering using

Microstrip Circuits, Prentice Hall New York, 1998
Varactor-Tuned Oscillators
Technical Data
Features
• 600 MHz to 10.85 GHz
Coverage
• Fast Tuning
• +7 to +13 dBm Output
Power
• ±1.5 dB Output Flatness
• Hermetic Thin-film
Construction
Description
Agilent Technologies’s VTO-8000
Series oscillators use a silicon
transistor chip as a negative
resistance oscillator. The oscilla-
tion frequency is determined by a
silicon abrupt varactor diode
acting as a voltage-variable
capacitor in a thin-film micro-
stripline resonator. This provides
extremely fast tuning speed,
limited primarily by the internal
impedance of the user-supplied
voltage driver. Fast settling is
another feature of the Agilent
VTO-8000 Series oscillators.
Typical settling times for the
VTO-8090 are <200 kHz within one
microsecond while the VTO-8950
settles to <2 MHz within two
microseconds referenced to ten
milliseconds. The VTO-8850
combines a bipolar transistor
oscillator with a GaAs FET buffer
stage. This GaAs FET buffer
isolates the oscillator from
variations in load impedance for
low frequency pulling, allows the
oscillator to run lighty-loaded for
low phase noise content and
provides +10 dBm of minimum
output power over the full tuning
range. The VTO-8000 Series
varactor-tuned oscillators are
packaged in TO-8 transistor cans
for simple installation in a
conventional 50-ohm micro-
stripline PC board. They are ideal
for most compact, lightweight
commercial and military equip-
ment designs. Test fixturing is
also available for lab bench test
applications. See the “Test
Fixtures for TO-8 Packages”
section for additional information
and outlines.
Applications
Frequency agile systems, such as
digitally controlled receivers and
active jamming transmitters often
use externally linearized
varactor-tuned oscillators.
Agilent oscillators are monotonic
making external linearization
easy using analog (opamp) or
digital (EPROM) linearizing
techniques. The Agilent VTO
Series has been designed with a
tuning input bypass capacitance
which is sufficient to provide the
VTO-8000 Series
Pin Configuration
TO-8V
GROUND
3
+V
TUNE
RF OUT
2 4
1
+DC
VOLTAGE CASE GROUND
necessary RF filtering action yet
as low as possible to maximize
∆V/∆T characteristics for excel-
lent tuning speeds. Used in a
phase locked loop PLL circuit, a
VTO provides a receiver LO with
stability equivalent to the refer-
ence oscillator (usually crystal
controlled), yet variable in
discrete steps or continuously
depending on the PLL
configuration.
Another important aspect of VTOs
used in an LO application is their
power vs. frequency flatness
(±1.5 dB). This assures that once a
receiver mixer is biased for best
dynamic range the local oscillator
drive will remain constant
throughout the tuning range
without complex leveling
circuitry.
 2

Electrical and Performance Specifications

Guaranteed Specifications @ 25°C Case Temperature (0° to +65°C Operating Temperature)
Part Number VTO–8060 VTO–8080 VTO–8090 VTO–8150 VTO–8200
Frequency Range, Min. 600–1000 MHz 800–1400 MHz 900–1600 MHz 1500–2500 MHz 2000–3000 MHz
Power Output into 50–ohm Load,Min. 20 mW/+13 dBm 20 mW/+13 dBm 20 mW/+13 dBm 10 mW/+10 dBm 10 mW/+10 dBm
Power Output Variation @ 25°C, Max. ±1.5 dB ±1.5 dB ±1.5 dB ±1.5 dB ±1.5 dB
Operating Case Temperature Range 0° to +65°C 0° to +65°C 0° to +65°C 0° to +65°C 0° to +65°C
Frequency Drift Over Operating 8 MHz 10 MHz 10 MHz 18 MHz 30 MHz
Temperature, Typ.
Pulling Figure (12 dB Return Loss), Typ. 25 MHz 25 MHz 25 MHz 35 MHz 35 MHz
Pushing Figure, +15 VDC Supply, Typ. 5 MHz/V 6 MHz/V 6 MHz/V 6 MHz/V 6 MHz/V
Harmonics, Below Carrier, Typ. –15 dB –15 dB –15 dB –15 dB –18 dB
Spurious Output Below Carrier, Min. –60 dB –60 dB –60 dB –60 dB –60 dB
Tuning Voltage
Low Frequency 3±1 VDC 2±1.5 VDC 2±1 VDC 2.5±1 VDC 2+2/–1 VDC
High Frequency 40±8 VDC 35±10 VDC 48+8/–10 VDC 47±8 VDC 20±4 VDC
Maximum Tuning Voltage +60 VDC +60 VDC +60 VDC +60 VDC +45 VDC
Tuning Port Capacitance, Nom. 180 pF 180 pF 180 pF 90 pF 45 pF
Phase Noise, Singie Sideband,
1 Hz Bandwidth, Typ.
50 kHz From Carrier –110 dBc/Hz –100 dBc/Hz –100 dBc/Hz –95 dBc/Hz –95 dBc/Hz
100 kHz From Carrier –117 dBc/Hz –107 dBc/Hz –107 dBc/Hz –102 dBc/Hz –102 dBc/Hz
Input Power ±1% Regulation
Voltage, Nom. +15 VDC +15 VDC +15 VDC +15 VDC +15 VDC
Current, Max. 50 mA 50 mA 50 mA 50 mA 50 mA
Case Style TO–8V TO–8V TO–8V TO–8V TO–8V

Part Number VTO–8240 VTO-8248 VTO-8360 VTO–8430 VTO–8580

Frequency Range, Min. 2400–3700 MHz 2488 MHz 3600–4300 MHz 4300–5800 MHz 5800–6600 MHz
Power Output Into 50–ohm Load, Min. 10 mW/+10 dBm +8 dBm 10 mW/+10 dBm 10 mW/+10 dBm 5 mW/+7 dBm
Power Output Variation @25°C., Max. ±1.5 dB N/A ±1.5 dB ±1.5 dB ±1.5 dB
Operating Case Temperature Range 0° to +65°C 0° to +65°C 0° to +65°C 0° to +65°C 0° to +65°C
Frequency Drift Over Operating 30 MHz 10 MHz 35 MHz 60 MHz 70 MHz
Temperature, Typ.
Pulling Figure (12 dB Return Loss), Typ. 35 MHz 2 MHz 40 MHz 50 MHZ 70 MHz
Pushing Figure, +15 VDC Supply, Typ. 6 MHz/V * 6 MHz/V 6 MHz/V 6 MHz/V 8 MHz/V
Harmonics, Below Carrier, Typ. –18 dB –20 dB –25 dB –25 dB –25 dB
Spurious Output Below Carrier, Min. –60 dB –60 dB –60 dB –60 dB –60 dB
Tuning Voltage
Low Frequency 2+2/–1 VDC 4 VDC 8±2 VDC 1.0 VDC Min 5±2.5 VDC
High Frequency 30±8 VDC 8 VDC 24±4 VDC 20.0 VDC Max. 24+3/–5 VDC
Maximum Tuning Voltage +45 VDC +10 VDC +30 VDC +30 VDC +30 VDC
Tuning Port Capacitance, Nom. 45 pF 23 pF 45 pF 45 pF 45 pF
Phase Noise, Single Sideband,
1 Hz Bandwidth, Typ.
50 kHz From Carrier –95 dBc/Hz –105 dBc/Hz –100 dBc/Hz –90 dBc/Hz –85 dBc/Hz
100 kHz From Carrier –102 dBc/Hz –115 dBc/Hz –108 dBc/Hz –97 dBc/Hz –92 dBc/Hz
Input Power ±1% Regulation
Voltage, Nom. +15 VDC +5 VDC +15 VDC +15 VDC +15 VDC
Current, Max. 50 mA 50 mA 50 mA 50 mA 50 mA
Case Style TO–8V TO–8V TO–8V TO–8V TO–8V

* +5 VDC supply
 3

Electrical and Performance Specifications

Guaranteed Specifications @ 25°C Case Temperature (0° to +65°C Operating Temperature)
Part Number VTO–8650 VTO–8810 VTO–8850 VTO–8950 VTO-810750
Frequency Range, Min. 6500-8600 MHz 8100–9100 MHz 8500–9600 MHz 9500–10500 MHz 10650–10850 MHz
Power Output Into 50–ohm load, Min. 10 mW/+10 dBm 10 mW/+10 dBm 10 mW/+10 dBm 10 mW/+10 dBm 10 mW/+10 dBm
Power Output Variation @ 25°C., Max. ±1.5 dB ±1.5 dB ±1.5 dB ±1.5 dB ±1.5 dB
Operating Case Temperature Range 0° to +65°C 0° to +65°C 0° to +65°C 0° to +65°C 0° to +65°C
Frequency Drift Over Operating 100 MHz 110 MHz 110 MHz 160 MHz 130 MHz
Temperature, Typ.
Pulling Figure (12 dB Return Loss), Typ. 15 MHz 8 MHz 10 MHz 20 MHz 10 MHz
Pushing Figure, +15 VDC Supply, Typ. 10 MHz/V 12 MHz/V 15 MHz/V 10 MHz/V 5 MHz/V
Harmonics, Below Carrier, Typ. –20 dB –15 dB –25 dB –20 dB –20 dB
Spurious Output Below Carrier, Min. –60 dB –60 dB –60 dB –60 dB –60 dB
Tuning Voltage
Low Frequency 2±1 VDC 2 VDC Min. 5±2 VDC 4±1 VDC 4 VDC Min.
High Frequency 20±5 VDC 16 VDC Max. 13±5 VDC 10 VDC Max. 6 VDC Max.
Maximum Tuning Voltage 30 VDC +30 VDC +30 VDC +15 VDC +15 VDC
Tuning Port Capacitance, Nom. 26 pF 26 pF 26 pF 26 pF 26 pF
Phase Noise, Single Sideband,
1 Hz Bandwldth, Typ.
50 kHz From Carrier –80 dBc/Hz –80 dBc/Hz –82 dBc/Hz –73 dBc/Hz –77 dBc/Hz
100 kHz From Carrier –88 dBc/Hz –88 dBc/Hz –90 dBc/Hz –80 dBc/Hz –85 dBc/Hz
Input Power ±1% Regulation
Voltage, Nom. +15 VDC +15 VDC +15 VDC +15 VDC +15 VDC
Current, Max. 50 mA 100 mA 100 mA 100 mA 100 mA
Case Style TO–8V TO–8V TO–8V TO–8V TO–8V

Schematic
+15 V

Output Matching RF Output

Series Feedback

Varactor
V Tune
Tuning Resonator
Port
Capacitor
 4

Typical Performance @ 25ºC Case Temperature

OUTPUT, dBm

OUTPUT, dBm
17 15
POWER

POWER
14 POWER OUTPUT
16
15 POWER OUTPUT 13
12
14 11

SENSITIVITY, MHz/V

SENSITIVITY, MHz/V
160 1500 125

MODULATION

FREQUENCY,
1.1

MODULATION
140
FREQUENCY,

1.0 120 TUNING CURVE

MHz
.9 TUNING CURVE 100 1000
GHz

.8 80
.7 60
MODULATION MODULATION
.6 40 500 25
.5 SENSITIVITY SENSITIVITY
20
0 5 10 15 20 25 30 35 40 45 50 0 8 16 24 32 40 48
TUNING VOLTAGE, VDC TUNING VOLTAGE, VDC
Figure 1. VTO–8060 Power Output, Frequency Figure 2. VTO–8080 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage. and Modulation Sensitivity vs. Tuning Voltage.
OUTPUT, dBm

OUTPUT, dBm
15 15
POWER

POWER

14 14 POWER OUTPUT
13 POWER OUTPUT 13
100
SENSITIVITY, MHz/V

SENSITIVITY, MHz/V
1.6 90 180
MODULATION

1.5 80 160

MODULATION
FREQUENCY,

FREQUENCY,

1.4 TUNING CURVE 70 TUNING CURVE 140

1.3 60 2.5 120
GHz

GHz

1.2 50 100
1.1 40 2.0 80
1.0 MODULATION 30 60
MODULATION
.9 SENSITIVITY 20 1.5 40
.8 10 SENSITIVITY 20

0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
TUNING VOLTAGE, VDC TUNING VOLTAGE, VDC
Figure 3. VTO–8090 Power Output, Frequency Figure 4. VTO–8150 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage. and Modulation Sensitivity vs. Tuning Voltage.
OUTPUT, dBm

OUTPUT, dBm

14
POWER

14
POWER

13 13 POWER OUTPUT
12 12
11 POWER OUTPUT
10 11

3500 250
SENSITIVITY, MHz/V

SENSITIVITY, MHz/V

4.0 TUNING CURVE 160

FREQUENCY,

FREQUENCY,
MODULATION

MODULATION

3000 TUNING CURVE

3.5 120
MHz

GHz

2500
3.0 80
2000 MODULATION MODULATION
1500 SENSITIVITY 50 2.5 SENSITIVITY 40

0 8 16 24 32 40 48 0 5 10 15 20 25 30 35 40 45 50
TUNING VOLTAGE, VDC TUNING VOLTAGE, VDC
Figure 5. VTO–8200 Power Output, Frequency Figure 6. VTO–8240 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage. and Modulation Sensitivity vs. Tuning Voltage.
 5

Typical Performance (Continued)

OUTPUT, dBm

OUTPUT, dBm
10
POWER

POWER
11.5
POWER OUTPUT
9 11.0 POWER OUTPUT
8 10.5

SENSITIVITY, MHz/V
9

SENSITIVITY, MHz/V
MODULATION 4.3 90
2530 8

MODULATION
SENSITIVITY 4.2 TUNING CURVE 80
FREQUENCY,

MODULATION
FREQUENCY,
2520 7 4.1 70
2510 6 4.0 60
MHz

GHz
2500 5 3.9 MODULATION 50
2490 4 3.8 40
2480 3 3.7 SENSITIVITY
30
2470 TUNING CURVE 2 3.6 20
1 3.5 10
0 2 4 6 8 10 5 10 15 20 25 30
TUNING VOLTAGE, VDC TUNING VOLTAGE, VDC
Figure 7. VTO–8248 Power Output, Frequency Figure 8. VTO–8360 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage. and Modulation Sensitivity vs. Tuning Voltage.

OUTPUT, dBm
OUTPUT, dBm

13 13
POWER
POWER

12 12 POWER OUTPUT
11 POWER OUTPUT
10 11
9 10

7.0
SENSITIVITY, MHz/V

6500 1000

SENSITIVITY, MHz/V
140
FREQUENCY,
MODULATION
FREQUENCY,

TUNING CURVE

MODULATION
5500 6.5 TUNING CURVE 120
100
GHz
MHz

4500 6.0 MODULATION 80

SENSITIVITY 60
MODULATION 5.5 40
3500 SENSITIVITY 250
20
0
0 8 16 24 32 40 48 0 5 10 15 20 25
TUNING VOLTAGE, VDC TUNING VOLTAGE, VDC

Figure 9. VTO–8430 Power Output, Frequency Figure 10. VTO–8580 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage. and Modulation Sensitivity vs. Tuning Voltage.
OUTPUT, dBm

OUTPUT, dBm

14
13
POWER

15
POWER

12 POWER OUTPUT
POWER OUTPUT 14
11
10 13
1000
SENSITIVITY, MHz/V

SENSITIVITY, MHz/V

800 10 1200
8
MODULATION

FREQUENCY,

TUNING CURVE
MODULATION

9
FREQUENCY,

7 600 TUNING CURVE

8
GHz
GHz

6 400 7 600
MODULATION MODULATION
6
5 SENSITIVITY 200 SENSITIVITY
5
4 0 0
0 2 4 6 8 10 12 14 16 18 20 22 0 4 8 12 16 20
TUNING VOLTAGE, VDC TUNING VOLTAGE, VDC
Figure 11. VTO–8650 Power Output, Frequency Figure 12. VTO–8810 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage. and Modulation Sensitivity vs. Tuning Voltage.
 6

Typical Performance (Continued)

OUTPUT, dBm
OUTPUT, dBm

13

POWER
15
POWER

12
14 11 POWER OUTPUT
13 POWER OUTPUT 10
12 800

SENSITIVITY, MHz/V
SENSITIVITY, MHz/V

MODULATION
TUNING CURVE 11 600
FREQUENCY,

10

MODULATION

FREQUENCY,
TUNING CURVE
400
GHz

10 400

GHz
9 300 MODULATION
MODULATION 200 9 SENSITIVITY 200
8 SENSITIVITY 100
0 8 0
0 5 10 15 20 25 30 35 40 45 50 0 2 4 6 8 10 12 14 16
TUNING VOLTAGE, VDC TUNING VOLTAGE, VDC
Figure 13. VTO–8850 Power Output, Frequency Figure 14. VTO–8950 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage. and Modulation Sensitivity vs. Tuning Voltage.
OUTPUT, dBm

–20
13 8650 810750
POWER

–40
LOG £(f), dBc/Hz

12 8240
–60
11 POWER OUTPUT
–80 8248
–100
SENSITIVITY, MHz/V

11.5 300
–120 8950
FREQUENCY,

MODULATION

11 TUNING CURVE –140

10.5 200
GHz

–160
10 1k 10k 100k 1M 10M
9.5 MODULATION 100 FOURIER FREQUENCY, Hz
9 SENSITIVITY
Figure 16. Noise Comparison Single Sideband
2 4 6 8 10 Phase Noise.
TUNING VOLTAGE, VDC
Figure 15. VTO–810750 Power Output, Frequency
and Modulation Sensitivity vs. Tuning Voltage.

TO-8V Case Drawing

.300
.18 TYP
.150 GROUND
.017 +.002
TYP
–.001
RF OUT
3
GLASS RING
.300 2
.50 .45 .060 DIA TYP
DIA DIA TYP (3X)
.150 4
TYP 1

CASE
GROUND
V TUNE
.22
MIN V+

APPROXIMATE WEIGHT 1.7 GRAMS

NOTES (UNLESS OTHERWISE SPECIFIED):

1. DIMENSIONS ARE SPECIFIED IN INCHES
2. TOLERANCES: xx ± .02
xxx ± .010
 7

Test Fixtures for Description clamp is placed over the device

To facilitate testing and
TO-8 Packages prototyping of products in the
( TF 801/802) TO-8V package, a series of test
Oscillators ( VTO) fixtures is available. Designated
the TF Series test fixtures, they
Features feature rugged construction for
• DC to 11 GHz Frequency precise, repeatable
Range measurements.
• Connectorized Tuning Port
and RF Output The TF Series test fixtures come
supplied with mounting hardware
• Easy to Test Package to ensure excellent ground
• Repeatable Performance contact between the oscillator
package and test fixture. This
assures excellent contact between
Applications
package pins and test fixture
• Engineering
connector pins for reliable testing.
Characterization
• Incoming Inspection The device under test is aligned
• System Prototype according to Figure 15, and
• Demonstration of Device pushed fully down onto the
Performance fixture. The steel mounting ring
under test and secured by ma-
chine screws prior to testing.
Orientation of pins can be verified
by comparison with part (c) of
Figure 15. It is recommended that
both machine screws be used to
fasten the ring clamp. Screws
should be tightened down snugly
with a jewelers type screwdriver.
For different connector options
check the table in Figure 15 to
identify the correct part numbers.
It should be noted that some
output power variation may be
seen, from unit data, at frequen-
cies above 8 GHz. This is
due to small differences in lengths
of test fixture RF output
connector pins.

TUNING VOLTAGE
CONNECTOR TUNING VOLTAGE
.53 .35
POWER INPUT + TUNING
VTO IN CONNECTOR
PLACE VOLTAGE DCPIN
PIN

.83 .35 VDC

.45
GROUND
.20 GROUND GROUND
RFOUT .35
.55 RFOUT TAB ON PACKAGE
.15 .70
.65
(a) (b) (c)

+ TUNING .300
VOLTAGE TYP
.150
TYP GROUND
CASE
3 GROUND
CONNECTOR OPTIONS .45 2 4
1
TUNING RF RFOUT
SERIES VOLTAGE OUTPUT .150 +DC VOLTAGE
TYP
TF-801 SMA SMA
(Bottom View)

Figure 15. TO-8 Test Fixture.

www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies, Inc.
Obsoletes 5964-9815E
5980-1278E (6/00)
 Agilent HSMS-8101, 8202, 8207,
8209 Surface Mount Microwave
Schottky Mixer Diodes
Data Sheet

Features
• Optimized for use at
10-14 GHz
• Low Capacitance
• Low Conversion Loss
Description/Applications Plastic SOT-23 Package • Low RD
These low cost microwave • Low Cost Surface Mount
Schottky diodes are specifically Plastic Package
designed for use at X/Ku-bands
• Lead-free Option Available
and are ideal for DBS and VSAT
downconverter applications. They
are available in SOT-23 and
SOT-143 standard package
configurations. Package Lead Code
Note that Agilent's manufacturing Plastic SOT-143 Package Identification
techniques assure that dice found in (Top View)
pairs and quads are taken from SINGLE SERIES
adjacent sites on the wafer, assur- 3 3
ing the highest degree of match.

1 2 1 2
#1 #2

RING CROSS-OVER
Absolute Maximum Ratings [1], TA = +25°C QUAD QUAD
3 4 3 4
Symbol Parameter Unit Min. Max.
[2]
PT Total Device Dissipation mW — 75
PIV Peak Inverse Voltage V — 4 1 2 1 2
#7 #9
TJ Junction Temperature °C — +150
TSTG, Top Storage and Operating °C -65 +150
Temperature
Notes: Attention:
1. Operation in excess of any one of these conditions may result in Observe precautions for
permanent damage to the device. handling electrostatic
2. Measured in an infinite heat sink at TCASE = 25°C. Derate linearly to sensitive devices.
zero at 150°C per diode. ESD Machine Model (Class A)

ESD Human Body Model (Class 0)

Refer to Agilent Application Note A004R:

Electrostatic Discharge Damage and Control.
 2

DC Electrical Specifications, TA = 25°C HSMS-8101 HSMS-8202 HSMS-8207 HSMS-8209

Symbol Parameters and Test Conditions Units Min. Max. Min. Max. Min. Max. Min. Max.
VBR Breakdown Voltage V 4 4 4 4
IR = 10 µA
CT Total Capacitance pF 0.26 0.26 0.26 0.26
VR = 0 V, f = 1 MHz
∆C T Capacitance Difference pF — 0.04 0.04 0.04
VR = 0 V, f = 1 MHz
RD Dynamic Resistance Ω 14 14 14 14
IF = 5 mA
∆RD Dynamic Resistance Difference Ω — 2 2 2
IF = 5 mA
VF Forward Voltage mV 250 350 250 350 250 350 250 350
IF = 1 mA
∆VF Forward Voltage Difference mV — 20 20 20
IF = 1 mA
Lead Code 1 2 7 9
Package Marking Code in White R1x 2Rx R7x R9x
where x is date code

RF Electrical Parameters, TA = 25°C

Symbol Parameter Units Typical
Lc Conversion Loss at 12 GHz dB 6.3
Z IF IF Impedance Ω 150
SWR SWR at 12 GHz 1.2
Note:
DC Load Resistance = 0 Ω; LO Power = 1 mW.

SPICE Parameters Linear Equivalent Circuit

IS = 4.6 E-8 EG = 0.69 TT = 0 0.08 pF
RS = 6 CJO = 0.18 E-12
N = 1.09 PB (VJ) = 0.5
BV = 7.3 M = 0.5 1.0 nH 1.3 nH 6Ω 0.17 pF
IBV = 10E-5 FC = 0.5

Rj

Self Bias
1 mA 2.5 mA
Rj 256 142
 3

Typical Performance, TC = 25°C

∆VF - FORWARD VOLTAGE DIFFERENCE (mV)

100 30 30 9

IF - FORWARD CURRENT (mA)

IF (Left Scale)
FORWARD CURRENT (mA)

CONVERSION LOSS (dB)

10 10 10
8

∆VF (Right Scale) 7

TA = +125°C
0.1 1 1
TA = +25°C
TA = –55°C

0.01 0.3 0.3 6

0 0.2 0.4 0.6 0.8 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 –7 –5 –3 –1 1 3 5 7 9 11 13
FORWARD VOLTAGE (V) V - FORWARD VOLTAGE (V) LOCAL OSCILLATOR POWER (dBm)

Figure 1. Typical Forward Current Figure 2. Typical VF Match, HSMS- Figure 3. Typical Conversion Loss
vs. Forward Voltage at Three 820X Pairs and Quads. vs. Local Oscillator Power.
Temperatures.

Ordering Information Profile Option

Specify part number followed by option. For example: Descriptions
-BLK = Bulk
HSMS - 8101 - XXX -TR1 = 3K pc. Tape and Reel,
Bulk or Tape and Reel Option Device Orientation
Part Number Figures 4, 5
-TR2 = 10K pc. Tape and Reel,
Surface Mount Schottky Device Orientation
Figures 4, 5
Tape and Reeling conforms to
Device Orientation Electronic Industries RS-481,
REEL “Taping of Surface Mounted
Components for Automated
Placement.”
For lead-free option, the part
number will have the character "G"
CARRIER at the end, eg. -TR2G for a 10K pc
TAPE
lead-free reel.
USER
FEED
DIRECTION
COVER TAPE

TOP VIEW END VIEW TOP VIEW END VIEW

4 mm 4 mm

8 mm 8 mm ABC ABC ABC ABC

ABC ABC ABC ABC

Note: "AB" represents package marking code. Note: "AB" represents package marking code.
"C" represents date code. "C" represents date code.
Figure 4. Option -TR1/-TR2 for SOT-23 Packages. Figure 5. Option -TR1/-TR2 for SOT-143 Packages.
 4

Package Characteristics
Lead Material ...................................................................................... Alloy 42
Lead Finish ................................... Tin-Lead 85-15% (Non lead-free option)
or Tin 100% (Lead-free option)
Maximum Soldering Temperature .............................. 260°C for 5 seconds
Minimum Lead Strength .......................................................... 2 pounds pull
Typical Package Inductance .................................................................. 2 nH
Typical Package Capacitance .............................. 0.08 pF (opposite leads)

Package Dimensions Recommended PCB Pad Layout for

Outline 23 (SOT-23) Agilent’s SOT-23 Products
e2
0.039
e1 0.039 1
1

E E1
XXX
0.079
2.0
e
L

B C 0.035
0.9
D DIMENSIONS (mm)
SYMBOL MIN. MAX.
A 0.79 1.20
0.031
A1 0.000 0.100 0.8
A B 0.37 0.54
C 0.086 0.152 inches
Dimensions in
A1
D 2.73 3.13 mm
E1 1.15 1.50
e 0.89 1.02
e1 1.78 2.04
Notes: e2 0.45 0.60
XXX-package marking E 2.10 2.70
Drawings are not to scale L 0.45 0.69

Outline 143 (SOT-143) Recommended PCB Pad Layout

e2 for Agilent’s SOT-143 Products
e1

B1 0.112
2.85
0.079
2
E
XXX E1
0.033
0.85

L
0.081 0.048 0.114
2.05 0.071 1.2 2.9
B C
e
1.8
DIMENSIONS (mm) 0.033
D
SYMBOL MIN. MAX. 0.85
A 0.79 1.097
A1 0.013 0.10
A B 0.36 0.54
B1 0.76 0.92 0.047 0.031 0.033
C 0.086 0.152 1.2 0.8 0.85
A1 D 2.80 3.06 e
E1 1.20 1.40
inches
e 0.89 1.02 Dimensions in mm
e1 1.78 2.04
Notes: e2 0.45 0.60
XXX-package marking E 2.10 2.65
Drawings are not to scale L 0.45 0.69
 5

Tape Dimensions and Product Orientation

For Outline SOT-23
P D P2

E
P0

D1
t1

9° MAX Ko 8° MAX 13.5° MAX

A0 B0

DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)

CAVITY LENGTH A0 3.15 ± 0.10 0.124 ± 0.004
WIDTH B0 2.77 ± 0.10 0.109 ± 0.004
DEPTH K0 1.22 ± 0.10 0.048 ± 0.004
PITCH P 4.00 ± 0.10 0.157 ± 0.004
BOTTOM HOLE DIAMETER D1 1.00 + 0.05 0.039 ± 0.002
PERFORATION DIAMETER D 1.50 + 0.10 0.059 + 0.004
PITCH P0 4.00 ± 0.10 0.157 ± 0.004
POSITION E 1.75 ± 0.10 0.069 ± 0.004

CARRIER TAPE WIDTH W 8.00 +0.30 –0.10 0.315 +0.012 –0.004

THICKNESS t1 0.229 ± 0.013 0.009 ± 0.0005

DISTANCE CAVITY TO PERFORATION F 3.50 ± 0.05 0.138 ± 0.002

BETWEEN (WIDTH DIRECTION)
CENTERLINE CAVITY TO PERFORATION P2 2.00 ± 0.05 0.079 ± 0.002
(LENGTH DIRECTION)
Tape Dimensions and Product Orientation
For Outline SOT-143

P D
P2
P0

F W

D1
t1

9° MAX K0 9° MAX

A0 B0

DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)

CAVITY LENGTH A0 3.19 ± 0.10 0.126 ± 0.004
WIDTH B0 2.80 ± 0.10 0.110 ± 0.004
DEPTH K0 1.31 ± 0.10 0.052 ± 0.004
PITCH P 4.00 ± 0.10 0.157 ± 0.004
BOTTOM HOLE DIAMETER D1 1.00 + 0.25 0.039 + 0.010
PERFORATION DIAMETER D 1.50 + 0.10 0.059 + 0.004
PITCH P0 4.00 ± 0.10 0.157 ± 0.004
POSITION E 1.75 ± 0.10 0.069 ± 0.004

CARRIER TAPE WIDTH W 8.00 +0.30 –0.10 0.315+0.012 –0.004

THICKNESS t1 0.254 ± 0.013 0.0100 ± 0.0005

DISTANCE CAVITY TO PERFORATION F 3.50 ± 0.05 0.138 ± 0.002

(WIDTH DIRECTION)
CAVITY TO PERFORATION P2 2.00 ± 0.05 0.079 ± 0.002
(LENGTH DIRECTION)

www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or
(916) 788-6763
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (65) 6756 2394
India, Australia, New Zealand: (65) 6755 1939
Japan: (+81 3) 3335-8152(Domestic/International), or
0120-61-1280(Domestic Only)
Korea: (65) 6755 1989
Singapore, Malaysia, Vietnam, Thailand, Philippines,
Indonesia: (65) 6755 2044
Taiwan: (65) 6755 1843
Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
Obsoletes 5989-0481EN
July 19, 2005
5989-2496EN