Programmable Peripheral Interfacing Chips 401 If programmed as inputs— All input lines can be accessed during a normal port C read. If programmed as outputs— Bits in C upper (PC,-PC,) must be individually accessed using the bit sct/reset function, Bits in C lower (PC,-PC,) can be accessed using the bit set/reset function or accessed as fa threesome by writing into port C. Some of the several configurations in Mode 2 are given in Figure 12.21 pc, + nr, sft, Papa, Moy z ve, opr, oar, PCy ACK, C4} — ACK; 8255 PC, STB; ‘Jest, pc, + IBF, a wwe rete 34410 gy 340 = z wrod PPR, weed rm dead Node pc, + intr, |—+ rr, Pa,-PAy oy rc, onr, Pc, ACK; 8255 vc, e— sre, pc, + IBF, pc, | + IBF, Papp, |e) pepe, OF awe res ok, gy Pc, | ~—+ st, Pc ACK, PC, iF, wr PCyf-——FINTR, re Pc, f > INTR, Mode 2 and Mode 2 and mode I (output) mode 1 (input) Figure 12.21 Mode 2 combinations 12.7 8255 INTERFACING Interfacing 8255 with 8086 means how we connect the various signals of 8255 with 8086, So for interfacing we have to find out the signals in 8255 which are to be connected to 8086402 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing ‘and their counterparts in 8086. The various signals of 8255 which are being connected to the processor are: @ DD, (b) Ay Ay (c) RDT (@) WR () C () Reset. ‘These signals are connected with the following signals of 8086 or derived from 8086: (2) Demultiplexed D-D,, data lines (b) A, and A, lines of demultiplexed address bus. (6) IGR™ or MEMR™ (a) 10W- or MEMW" (©) The remaining address lines of 8086 (ie. A,~A, of A,~Ay, or A,-A,,) are used to gonerate a chip select signal (© Reset line of the clock generator of 8086, 8255 can be interfaced with 8086 in two different ways, ie, IO mapped 10 and Memory mapped 10 techniques. 12.7.1 10 Mapped 10 In this technique the control signals are IOR” and IOW~ which are generated by a control signal generating logic of 8086, The port addresses in this case are of 8-bit, ie. the chip select logic has to decode only A;~Ay address lines to generate the chip select signal. Figure 12.22 shows one such interfacing of 8086 with 8255. In this figure the port and the CWR addresses are: ADAG Ag Ay AS AD AY Ay roriod 0 0 0) = ASH= Port A 101 01 0 1 0 = AAH= Port B 10 1 o 4 1 0 0 = ACH= Port Cf Even port 101 01 1 1 0 = ABH=CWR to 1 0 1 0 0 1 = ADH = Port A 10 1 04 0 1 1 = ABH= Por B 10 1 0 1 0 0 1 = ADH= Port € Odd port 10 1 0 1 11 1 = AFH = cwR Used toenabie the decoder 12.7.2. Memory Mapped 10 In this technique the control signals are MEMR™ and MEMW™ which are generated by a control signal generating logic. The port addresses in this case aro of 20-bit, ic. the chip select logic has to decode all the A;~A,e address lines to generate the chip select signal and A, and ‘Ay are connected to the Ap and A; lines of $255 to select the ports and CWR of 8255Programmable Peripheral Interfacing Chips 403 1 [a A aE a nd a Od les 2 Kon - RS | re Veo ed shove Reset a o.cGr eS F ven por, a wea iy) fax 0 B decoder Proe wot fe +f 8 Tow Kr 6 Control signal generator +80 PA De, 8 AA oa kk oS Ales tiry s 6 OOF] sf NS re As ° we Ada 4 fv nese AL poser 01 pr jc 5 Chip eet oie Glock gevaator [4 on Figure 12.22 Interfacing of 8255 with S086 in IO mapped IO technique Figure 12.23 shows one such interfacing of 8086 with 8255, In this figure the port and the CWR addresses are: Ais Aig Air Ais AisAue Ais Aizu Ay As Ae Ay Ag AS Ag Ay Ar Ay Ay XX XXX 1 Trititi101 0080 XX XXX 1111112121101 010 XXX KX 1 Tiititiie1r toe XX XXX 1 Tirtitiireri.i18 XxX XXX patria 10 1 0 6 1 = 83PRoH XXX XX Prt tradi 10 0 0 1 =ssrEBnfoag XXX XX ttt ta dt 10 4 0 6 1 =asmnpnfpor XX XXX Ltt tid i 10 0 01 ss As shown in Figure 12.23 the address lines A,,~Ayg are not decoded by the chip select, logic as these lines are not connected to this logic. These lines may assume any value, 0 or 1. Here we assume that all these lines are 0 which give rises to the above port addresses,404 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing 1 a ALE Le es ADPAD, Lack aApo-. » KP 7k 8 : 5 2 v. 7 » x f WW Ro 6, 6.86.5] SS Even por well, a OS 3 107M - 6 A, >, BE Chip sleet logic Clock generator 3284 Figure 12.23 Interfacing of $255 with 8086 in memory mapped 10 technique, 12.8 INTERFACING AND DESIGN PROBLEMS EXAMPLE 12.3 Program 8255, for the following: (A) Set PC, to high and (B) Use PG, to generate a square wave of 66% duty cycle. Solution (A) Let the address of the CWR is 86H, then MOV AL, CooooLOIB ; CaR in BSR mode OUT 86H, AL (B) LOOP: MOV AL, Oxxx 101 OUT 86H, AL CALL Delay CALL DelayProgrammable Peripheral Interfacing Chips 405 MOV AL, OxoxL400 OUT 8éH, AL CALL Delay Ive LOOP EXAMPLE 12.4 Interface an input port and an output port with 8086 through 8255 and write a program to read data from input port and transfer it to the output port. Solution Let us assume that the input port is interfaced with port C and port B is interfaced with the display. The program is to repeat indefinitely. Required control word is shown in Figure 12.24 and the CWR byte is 89H. De] [P| Pe] Ds] Pz] Pr] Pe ]= 10001001 =011 110 mode «1 Toy post ex input 00 Ga in mode 0 {+ 9 Pore B= Output O Port A +0 GB in mode 0 1 Port CU Iapat Figure 1224 CWR for Example 12.4 ‘The complete interfacing is shown in Figure 12.25, 8255 is interfaced in IO mapped 10 technique. ‘The addresses of the ports A, B, C, and the CWR is Even port Odd port Port A ASH ASH Port B AAI ABH Port ACH ADH cWR AEH AFH Program: MOV AL, CWRBYTE : Transfer control byte to AL OUT AEH, AL : Send the control byte to the CiR of even port OUT AFH, AL Send the control byte to the CAR of cdd port LooP: IN AK, ACH Read data from ingut port OUT AH, AL : Send AL data to output port INP LOOP Jump to loop EXAMPLE 12.5 Interface 8 keys and 8 LEDs with 8086 through $255, Write a program to flash the 8 LEDs connected to port B until port C becomes FFH, Solution As only 8 LEDs are to be connected we interface only one 8255 as an even port. Control word for port B as output and port C as input. 100x101 = 89H, assuming x = 0 ‘The interfacing of the keyboard and LED display is shown in Figure 12.26, Here the LED display is interfaced with port B of the Even Port 8255. A keyboard is connected to port C406 Microprocessor 808¢—Atrchitecture, Programming ane Interfacing AL LE ra AD ADs Lateh |“! a ae roa ales 2 5 . suo 5 cP U ‘ouput i atwee Res wares F Even por wrt—fa 38 8 ow IB Decoder ° ecouer Pre 3 107M jc - i, 8 Tow Ay As eck] Inoue WRT Reset consorapalaenn | mito | Ae FP decoder ‘Oda port Ate 5 Chip select ogic ‘Clock generator [4 wR Figure 12.25. Interfacing of IO with S686 for Example 12.4 of this 8255, When the keyboard generates FF (ie, all the keys are open), then LED display stops blinking ‘The port and CWR addresses will be ADAG As Ay As A, AL Ay 1 0 1 0 1 0 0 O = ASH = Pon A 1 6 1 0 1 0 1 0 = AAH=Port B 1 0 1 0 1 1 0 0 = ACH =Por ¢ f Even port 10 1 0 1 1 1 0 = AEH =CWR Used to enable the decoder Program: MOV AL, CWRBYTE : Transfer control byte to AL QUT AEH, AL : Send the control byte to the CiR of even port LOOP: IN AL, ACK OP AL, FFH JE LASTProgrammable Peripheral Interfacing Chips 407 MOV AL, FFH OUT AAH, AL + LEDs ON CALL DEALY, MOV AL, OCH QUT AAH, AL : LEDs OFF CALL DEALY. IMP LOOP LAST: HLT i sv ALE se LL; AD (ADs Latch | Av te fed, HH Ded; Ls Vee _— l es Lee ° Lt a Chosed~0 A ox 8 B pecosee frye} 80™ a gre 9 orm} ale POR at wre * Tow" ven prt é Conot signal gevertst, LED display generator Chip sleet Topie rat Figure 12.26 Interfacing of Example 12.5 EXAMPLE 12.6 In a control process the level of a liquid is required to be monitored by ‘wo sensors. Sensor S, monitors the lower limit and sensor S, monitors the upper limit. When the liquid level is above the upper limit the supply pump is to be switched off. If the liquid level falls below the lower limit, an alarm is to be raised. ‘Write an assembly language program to perform this task