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  • Verilog ASSIGNMENT 2

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    Narendra babu
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    This document outlines assignments for a Verilog course. It includes questions about implementing a D flip-flop using behavioral and gate level logic with a testbench, comparing a D latch to a D flip-flop, designing a D flip-flop with synchronous and asynchronous reset with a testbench, designing a 4-bit ripple counter with a testbench, designing a ring counter using behavioral and structural models with a 4-bit up-down version, implementing and verifying Gray, mod-n, Johnson and decade counters, and creating a parameterizable multiple bit register module with a testbench to write to and read from the register.

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    Verilog_ASSIGNMENT_2 (2)

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    This document outlines assignments for a Verilog course. It includes questions about implementing a D flip-flop using behavioral and gate level logic with a testbench, comparing a D latch to a D flip-flop, designing a D flip-flop with synchronous and asynchronous reset with a testbench, designing a 4-bit ripple counter with a testbench, designing a ring counter using behavioral and structural models with a 4-bit up-down version, implementing and verifying Gray, mod-n, Johnson and decade counters, and creating a parameterizable multiple bit register module with a testbench to write to and read from the register.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Download as pdf or txt
    6 views1 page

    Verilog ASSIGNMENT 2

    Uploaded by

    Narendra babu
    This document outlines assignments for a Verilog course. It includes questions about implementing a D flip-flop using behavioral and gate level logic with a testbench, comparing a D latch to a D flip-flop, designing a D flip-flop with synchronous and asynchronous reset with a testbench, designing a 4-bit ripple counter with a testbench, designing a ring counter using behavioral and structural models with a 4-bit up-down version, implementing and verifying Gray, mod-n, Johnson and decade counters, and creating a parameterizable multiple bit register module with a testbench to write to and read from the register.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    Training

    VERILOG ASSIGNMENT-2

    Q.No. Questions
    1) a) Implement D-flip flop using behavioral logic and gate level.
    b) Write a testbench to verify the above flipflop functionality.
    2) a) Implement D-latch and compare the output waveform with D-flipflop.

    3) a) Design D-Flipflop with synchronous and asynchronous reset and verify


    the functionality by writing test bench.

    b) Design 4-bit Ripple counter and verify.

    4) a) Design ring counter using behavioral, structural model and verify.


    b) Implement 4bit up-down ring counter and verify by applying random up-
    down control.
    5) Implement the following counters and verify the functionality by develop
    test bench.
    a) Gray counter
    b) Mod-n Counter
    c) Johnson’s counter
    d) Decade counter

    6) a) Create a parameterizable module for multiple bit register with width of


    register as parameter. Instantiate above module in TB, perform write to
    register, read from register.

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