Half Adder

Code:--
module HA(A,B,C,S);
input A,B;
output C,S;
assign S=A^B;
assign C=A&B;
endmodule;

Testbench:--
module HAF_TB;
reg A,B;
wire C,S;
HA HAF_inst(A,B, C,S );
initial
begin

$monitor("A=%d,B=%d,C=%
d,S=%d",A,B, C,S );
A=1'b0;
B=1'b0;
#10
A=1'b0;
B=1'b1;
#10
A=1'b1;
B=1'b0;
#10
A=1'b1;
B=1'b1;
#10
$finish;
end
initial
begin
$dumpfile("HAF_inst.vcd");
$dumpvars;
end
endmodule
Full Adder
07 November 2022 22:08

Code:-
module FA(A,B,Cin,S,Cout);
input A,B,Cin;
output S,Cout;
assign S=A^B^Cin;
assign Cout=(A^B)&Cin|A&B;
endmodule;

Testbench:-

module FA_TB;
reg A,B,Cin;
wire S,Cout;
FA FA_inst( A,B,Cin,S,Cout);
initial
begin
$monitor("A=%d,B=%d,Cin=%d,S=%d,Cout=%d",A,B,Cin,S,Cout);
A=1'b0;
B=1'b0;
Cin=1'b0;
#10
A=1'b0;
B=1'b0;
Cin=1'b1;
#10
A=1'b0;
B=1'b1;
Cin=1'b0;
#10
A=1'b0;
B=1'b1;
Cin=1'b1;
#10
A=1'b1;
B=1'b0;
Cin=1'b0;
#10
A=1'b1;
B=1'b0;
Cin=1'b1;
#10
A=1'b1;
B=1'b1;
Cin=1'b0;
#10
A=1'b1;
B=1'b1;
Cin=1'b1;
#10
$finish;
end
initial
begin
$dumpfile("FA_inst.vcd");
$dumpvars;
end
endmodule
Full Subtractor
07 November 2022 22:09

Code:-

module FS(A,B,Bin,D,Bout);
input A,B,Bin;
output D,Bout;
assign D=!A&!B&Bin|A&!B&!Bin|!A&B&!Bin|A&B&Bin;
assign Bout=!A&Bin|!A&B|B&Bin;
endmodule;

Testbench:-

module FS_TB;
reg A,B,Bin;
wire D,Bout;
FS fullsub_inst(A,B,Bin,D,Bout);
initial
begin
$monitor("A=%d,B=%d,Bin=%d,D=%d,Bout=%d",A,B,Bin,D,Bout);
A=1'b0; B=1'b0; Bin=1'b0;
#10
A=1'b0; B=1'b0; Bin=1'b1;
#10
A=1'b0; B=1'b1; Bin=1'b0;
#10
A=1'b0; B=1'b1; Bin=1'b1;
#10
A=1'b1; B=1'b0; Bin=1'b0;
#10
A=1'b1; B=1'b0; Bin=1'b1;
#10
A=1'b1; B=1'b1; Bin=1'b0;
#10
A=1'b1; B=1'b1; Bin=1'b1;
#10
$finish;
end
initial
begin
$dumpfile("fullsub_inst.vcd");
$dumpvars;
end
endmodule
Binary to Gray
07 November 2022 22:09

Code:-
module B2G(B0,B1,B2,B3,G0,G1,G2,G3);
input B0,B1,B2,B3;
output G0,G1,G2,G3;
assign G0=B0;
assign G1=B0^B1;
assign G2=B1^B2;
assign G3=B2^B3;
endmodule

Testbench:-

module B2G_TB;
reg B0, B1,B2,B3;
wire G0,G1,G2,G3;
B2G b_inst(B0,B1,B2, B3, G0,G1,G2,G3);
initial begin
$monitor ("B0=%d,B1=%d,B2=%d,B3=%d, G0=%d,G1=%d,G2=%d,G3=%d", B0,B1,B2, B3,
G0,G1,G2,G3);
B0=1'b0; B1=1'b0; B2=1'b0; B3=1'b0;
#10;
B0=1'b0; B1=1'b0; B2=1'b0; B3=1'b1;
#10;
B0=1'b0; B1=1'b0; B2=1'b1; B3=1'b0;
#10;
B0=1'b0; B1=1'b0; B2=1'b1; B3=1'b1;
#10;
B0=1'b0; B1=1'b1; B2=1'b0; B3=1'b0;
#10;
B0=1'b0; B1=1'b1; B2=1'b0; B3=1'b1;
#10;
B0=1'b0; B1=1'b1; B2=1'b1; B3=1'b0;
#10;
B0=1'b0; B1=1'b1; B2=1'b1; B3=1'b1;
#10;
B0=1'b1; B1=1'b0; B2=1'b0; B3=1'b0;
#10;
B0=1'b1; B1=1'b0; B2=1'b0; B3=1'b1;
#10;
B0=1'b1; B1=1'b0; B2=1'b1; B3=1'b0;
#10;
B0=1'b1; B1=1'b0; B2=1'b1; B3=1'b1;
#10;
B0=1'b1; B1=1'b1; B2=1'b0; B3=1'b0;
#10;
B0=1'b1; B1=1'b1; B2=1'b0; B3=1'b1;
#10;
B0=1'b1; B1=1'b1; B2=1'b1; B3=1'b0;
#10;
B0=1'b1; B1=1'b1; B2=1'b1; B3=1'b1;
#10;
$finish;
end

initial begin
$dumpfile ("b_inst.vcd");
$dumpvars;
end

endmodule
Half Subtractor
07 November 2022 22:08

Code:-

module HS(A,B,D,Bout);
input A,B;
output D,Bout;
assign Bout=!A&B;
assign D=A^B;
endmodule;

Testbench:-

module HalfS_TB;
reg A,B;
wire D,Bout;
HS hs_inst(A,B,D,Bout);
initial
begin
$monitor("A=%d,B=%d,D=%d,Bout=%d",A,B,D,Bout);
A=1'b0;
B=1'b0;
#10
A=1'b0;
B=1'b1;
#10
A=1'b1;
B=1'b0;
#10
A=1'b1;
B=1'b1;
#10
$finish;
end
initial
begin
$dumpfile("hs_inst.vcd");
$dumpvars;
end
endmodule
Gray to binary
07 November 2022 22:09

Code:-

module G2B(G3,G2,G1,G0,B3,B2,B1,B0);
input G3,G2,G1,G0;
output B3,B2,B1,B0;
assign B3=G3;
assign B2=G3^G2;
assign B1=G3^G2^G1;
assign B0=G3^G2^G1^G0;
endmodule;

Testbench:-

module G2B_TB;
reg G3,G2,G1,G0;
wire B3,B2,B1,B0;
G2B gray2B_inst(G3,G2,G1,G0, B3,B2,B1,B0);
initial
begin

$monitor("G3=%d,G2=%d,G1=%d,G0=%d,B3=%d,B2=%d,B1=%d,B0=%d",G3,G2,G
1,G0,B3,B2,B1,B0);

G3=1'b0; G2=1'b0; G1=1'b0; G0=1'b0;

#10
G3=1'b0; G2=1'b0; G1=1'b0; G0=1'b1;
#10
G3=1'b0; G2=1'b0; G1=1'b1; G0=1'b1;
#10
G3=1'b0; G2=1'b0; G1=1'b1; G0=1'b0;
#10
G3=1'b0; G2=1'b1; G1=1'b1; G0=1'b0;
#10
G3=1'b0; G2=1'b1; G1=1'b1; G0=1'b1;
#10
G3=1'b0; G2=1'b1; G1=1'b0; G0=1'b1;
#10
G3=1'b0; G2=1'b1; G1=1'b0; G0=1'b0;
#10
G3=1'b1; G2=1'b1; G1=1'b0; G0=1'b0;
#10
G3=1'b1; G2=1'b1; G1=1'b0; G0=1'b1;
#10
G3=1'b1; G2=1'b1; G1=1'b1; G0=1'b1;
#10
G3=1'b1; G2=1'b1; G1=1'b1; G0=1'b0;
#10
G3=1'b1; G2=1'b0; G1=1'b1; G0=1'b0;
#10
G3=1'b1; G2=1'b0; G1=1'b1; G0=1'b1;
#10
G3=1'b1; G2=1'b0; G1=1'b0; G0=1'b1;
#10
G3=1'b1; G2=1'b0; G1=1'b0; G0=1'b0;
#10
$finish;
end
initial
begin
$dumpfile("gray2B_inst.vcd");
$dumpvars;
end
endmodule
2:4 Decoder
07 November 2022 22:10

Code:-

module D2X4(I1,I0,Y3,Y2,Y1,Y0);
input I1,I0;
output Y3,Y2,Y1,Y0;
assign Y3=I1&I0;
assign Y2=I1&!I0;
assign Y1=!I1&I0;
assign Y0=!I1&!I0;
endmodule;

Testbench:-

module D2X4_TB;
reg I1,I0;
wire Y3,Y2,Y1,Y0;
D2X4 DE_inst(I1,I0,Y3,Y2,Y1,Y0);
initial
begin
$monitor("I1=%d,I0=%d,Y3=%d,Y2=%d,Y1=%d,Y0=%d",I1,I0, Y3,Y2,Y1,Y0);
I1=1'b0; I0=1'b0;
#10
I1=1'b0; I0=1'b1;
#10
I1=1'b1; I0=1'b0;
#10
I1=1'b1; I0=1'b1;
#10
$finish;
end
initial
begin
$dumpfile("DE_inst.vcd");
$dumpvars;
end
endmodule
4x1 mux
07 November 2022 22:11

Code:-

module Mux4X1(S0,S1,I0,I1,I2,I3,Y);
input S0,S1,I0,I1,I2,I3;
output Y;
assign Y={(!S1)&(!S0)&I0}|{(!S1)&S0&I1}|{S1&(!S0)&I2}|{S1&S0&I3};
endmodule;

Testbench:-

module Mux_TB;
reg S0,S1,I0,I1,I2,I3;
wire Y;
Mux4X1 mux_inst(S0,S1,I0,I1,I2,I3,Y);
initial
begin

$monitor("S0=%d,S1=%d,I0=%d,I1=%d,I2=%d,I3=%d,Y=%d",S0,S1,I0,I1,I
2,I3,Y);

S1=1'b0; S0=1'b0;
I0=1'b1; I1=1'b0; I2=1'b0; I3=1'b0;
#10

S1=1'b0; S0=1'b1;
I0=1'b0; I1=1'b1; I2=1'b0; I3=1'b0;
#10

S1=1'b1; S0=1'b0;
I0=1'b0; I1=1'b0; I2=1'b1; I3=1'b0;
#10

S1=1'b1; S0=1'b1;
I0=1'b0; I1=1'b0; I2=1'b1; I3=1'b0;
#10
$finish;
end
initial
begin
$dumpfile("mux_inst.vcd");
$dumpvars;
end
endmodule