E314 Microprocessors

8086 Interrupt

Interrupt
ƒ Interrupt:
Š suspend (or interrupt) the “current” program,
Š run an interrupt service routine (ISR),
Š resume the suspended program upon completion of the
interrupt service routine.

CS:IP
Interrupt
Current Service
Program routine
(ISR)

IRET
Š Similar to a FAR CALL, except ...

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 How to raise an Interrupt?
ƒ 3 ways to raise an interrupt (i.e. to activate or call an
Interrupt Service Routine):
1. Hardware: an external hardware raises a signal at
INTR or NMI pins of 8086.
2. Software: programmer issues an “INT n” instruction
(similar to a FAR CALL instruction – which can only be
issued via software instruction).
3. Internally Generated: µP automatically triggers an
interrupt upon certain events, such as “Divide by Zero”
or “General Protection Fault”.

80x86 Interrupt Structure

ƒ Hardware pins: 2 interrupt request pins - INTR (Interrupt
Request) and NMI (Non-maskable Interrupt), 1 output pin
~INTA (Interrupt Acknowledged) that acknowledges INTR.
ƒ Software instructions: INT n (0≤n ≤255), INTO.
ƒ Two flags:
Š IF (Interrupt Flag): for enabling/disabling maskable
INTR. Use STI (Set Interrupt flag) and CLI (Clear
Interrupt flag) instructions to set and clear the IF.
Š TF (Trap Flag): for activating single-step interrupt (for
debugging purpose).
NMI
Flags
8086
INTR
O D I T S Z A P C
INTA
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 Interrupt Types (or Interrupt Numbers)
ƒ 80x86 interrupt is identified using an “Interrupt Type
number”.
ƒ There are 256 types of interrupts, from Type 0 to Type 255.
ƒ Each interrupt type is associated with an Interrupt Service
Routine (ISR).
ƒ Recall that “Interrupt” means “suspend the current program
and run an Interrupt Service Routine”. Since there are 256
types of interrupts, there could be up to 256 different
Interrupt Service Routines.
ƒ You (the designer and programmer) must write the Interrupt
Service Routines for your specific purpose and application.
Intel did not provide any Interrupt Service Routines. If you
are running under an operating system like DOS, Windows,
or Linux, operating system will provide the interrupt service
routines.
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Implementing Interrupt
ƒ For example, you have a switch connecting to the INTR pin.
Upon pressing the switch, you wish to sound a alarm.
Š Step 1: pick an Interrupt type number for your application
(says Type 54H).
Š Step 2: Write the Interrupt Service Routine, which will be
called upon activating the interrupt (pressing the switch):
ISR SEGMENT ;Segment begins at ABCD0H
ORG 1234H
ISR54H PROC
MOV DX, 88H ;Alarm connected to port 88H
MOV AL, 01H ;send 01H to sound the alarm
OUT DX, AL
IRET
ISR54H ENDP
ISR ENDS
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 Interrupt Vector (ISR Starting Address)
ƒ Each interrupt type is associated with a user-written Interrupt Service
Routine (ISR) via an Interrupt Vector.
ƒ An Interrupt Vector is a memory address (4-byte), in terms of a 16-bit
segment and 16-bit offset, that points to the starting address of the ISR
stored in memory.
ƒ Interrupt Vector = Starting Address of ISR.
ƒ Interrupt vector allows you to find the interrupt service routine.

Type N
Interrupt Type N
Interrupt Vector
Type N Interrupt
raised :
Service
Segment : Offset Routine
16-bit 16-bit
(ISR)
ISR N starting address
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Interrupt Vector Table

ƒ The 256 interrupt vectors are grouped into an Interrupt
Vector Table.
ƒ Each interrupt vector is 4 bytes (16-bit segment + 16-bit
offset). The interrupt vector table contains 256 interrupt
vectors, occupying 256×4 = 1024 Bytes = 1KB.
ƒ The interrupt vector table is located at the lowest 1KB of
memory addresses, starting from 00000H to 003FFH.

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 Interrupt Vector Table (cont.)

Int 255 vector 3FF 3FE : 3FD 3FC

... ... ...
... ... ...

Int 5 vector : 15 14
17 16
Int 4 vector
13 12
: 11 10
Int 3 vector
F E : D C
Int 2 vector B A : 9 8
Int 1 vector 7 6 : 5 4
Int 0 vector 3 2 : 1 0
16-bit Segment 16-bit Offset
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Implementing Interrupt (cont.)

ƒ Step 1: Choose an Interrupt Type Number (says 54H).
ƒ Step 2: Write the ISR.
... continue from Previous example:
ƒ Step 3: Store the ISR written by you into some fixed memory
locations (eg. burn to fixed-address ROM). Note down the
starting address of the ISR, in terms of segment:offset (in
our example, ABCDH:1234H).
ƒ Step 4: Based on the chosen Interrupt type, locate the
address of the interrupt vector. (Type 54H interrupt vector
occupies addresses 54H*4 = 150H, 151H, 152H and 153H.
ƒ Step 5: Store the starting address (segment:offset) of ISR
into addresses 150H-153H.
AB CD 12 34
153H 152H 151H 150H
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 Activating the Interrupt
... Continue our example
ƒ Suppose an user presses the switch.
ƒ µP responds by suspending its current program, and runs the
ISR54H routine written by you.
ƒ How to find the ISR54H routine?
Š Based on the interrupt type (54H) associated with the
interrupt, µP goes to 54H*4=150H, to look for the
interrupt vector for type 54H interrupt. The interrupt
vector points to the starting address of routine ISR54H,
that is supposed to be run.
Š Important to note that you are the one who writes the
ISR, places the starting address of ISR in the
corresponding interrupt vector location.

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Interrupt v.s. FAR CALL

ƒ Interrupt processing is similar to calling an far subroutine,
except that the starting address of the Interrupt Service
Routine (ISR) is obtained via the interrupt vector instead of
from the FAR CALL instruction itself.
ƒ Steps involved in FAR CALL CS:IP:
1. PUSH return-CS
2. PUSH return-IP
3. CS:IP ← CS:IP in the FAR CALL instruction
ƒ The FAR RET instruction pops the return IP and CS from the
stack and continues the suspended program.

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 Interrupt Processing
ƒ Steps involved in an INT processing:
1. PUSHF
2. IF ← 0 and TF ← 0 (Disable INTR and Single-step
Interrupts to prevent nested INTR and Trap)
3. PUSH return-CS
4. PUSH return-IP
5. CS:IP ← [n×4] (retrieve the interrupt vector, which gives
the starting address of the ISR)
ƒ A corresponding IRET instruction terminates the ISR and
returns control to the interrupted routine, by popping the IP,
CS and Flags from the stack. Note that IRET is different
from RET.

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Interrupt Vector Table (cont)

ƒ The 4-byte interrupt vector for “INT n” is located at
memory address n×4, n×4+1, n×4+2, n×4+3, where n×4+3
and n×4+2 keep the segment address, and n×4+1 and n×4
keep the offset address of the interrupt service routine (ISR).
ƒ Interrupt Vector = Starting address of the Interrupt Service
Routine (ISR)
ƒ Interrupt Vector Table located at physical address 00000H to
003FFH (lowest 1 KB memory)
ƒ Interrupt Type 0 to 31 are reserved by Intel.
ƒ Interrupt Type 32 to 255 are available to users.
ƒ Interrupt types are prioritized. If two interrupts occur at
the same time, the lower type number takes precedent.

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003FFH

Type 32-255: User-defined

00080H
...

Type 13: General Protection Fault - Internal

00034H
...

Type 6: Undefined Opcode – internally generated

00018H
Type 5: BOUND instruction – software instruction
00014H
Type 4: INTO instruction (Overflow) - software
00010H
Type 3: 1-byte instruction – software instruction
0000CH
Type 2: NMI pin – hardware triggered
00008H
Type 1: Single Step (Trap) – flags register
00004H
Type 0: Divide Error (DIV) – internally generated
00000H
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Predefined Interrupt Types

ƒ Type 0 (Divide Error): internally generated by the µP after
a DIV instruction, which has a zero divisor or resulted in
division overflow.
ƒ Type 1 (Single Step or Trap): activated after the
execution of each instruction if the TF (Trap Flag) is set.
Used for debugging.
ƒ Type 2 (NMI – nonmaskable hardware interrupt):
triggered by a 0→1 transition of the NMI pin. This interrupt
can not be masked (i.e. disabled).
ƒ Type 3 (1-Byte Interrupt): responds to INT 3 instruction,
which is a special 1-byte instruction. (All software interrupt
instructions “int n” takes 2 bytes with machine code CD xx,
except “int 3” with 1-byte machine code CCH). INT 3 is
often used to store a breakpoint in a program for debugging.

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 Predefined Interrupt Types (cont.)
ƒ Type 4 (INTO): responds to an INTO instruction, triggered
if the OF (Overflow Flag) is set.
ƒ Type 5 (BOUND): responds to a BOUND instruction,
triggered if the array index is out-of-bound.
ƒ Type 6 (Invalid Opcode): occurs when an invalid opcode
occurs in the program, fetched by CS:IP.
ƒ Type 8 (Double fault): activated whenever two separate
interrupts occur during the same instruction.
ƒ Type 9-12: others.
ƒ Type 13 (General Protection Fault): internally generated
by the µP whenever there is a protection error in the
protected mode.
ƒ Type 14-16: others.
ƒ Type 17-31: reserved by Intel
ƒ Type 32-255: user-defined, for your specific purpose.

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Types of Interrupts
ƒ Recall that there are 3 broad categories of interrupts:
Š Software Interrupt: programmer issues instructions
such as INT n, INTO etc. For example,
MOV AX, 1234H
INT 21H ; call ISR for type 21H
MOV BX, AX
Š Internally generated: µP automatically triggers an
interrupt for certain conditions such as Divide Error (Type
0), General Protection Fault (Type 13), Invalid Opcode
(Type 6).
Š Hardware Interrupt: triggered by applying appropriate
hardware signal to INTR or NMI pins.

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 Hardware Interrupt
ƒ One of the main purpose of interrupt is to service external
I/O requests (such as keyboard, printer etc).
ƒ Important to note that I/O devices typically operate at a
much slower rate compared with CPU.
ƒ Two approaches for servicing external I/O requests:
Š Software Polling:
y program continuously checks for I/O request;
y branch to I/O service routine once an I/O request is
sensed;
y after I/O routine completed, revert back to check.
Š Hardware Interrupt:
y µp executing instructions, external I/O signals a service
request by triggering a hardware interrupt;
y branch to an interrupt service routine to process the I/O;
y revert back to the suspended routine after I/O serviced.
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Interrupt v.s. Polling

ƒ Polling is easier and simpler to implement, but the processor
is totally occupied in sensing for I/O request and cannot
perform other tasks. Example of a polling routine to poll a
active-low switch connecting to bit 0 of I/O port 8008H:
MOV DX, 8008H
poll: IN AL, DX
TEST AL, 0000 0001B
JNZ poll
; code for processing the switch

ƒ Interrupt is slightly harder to implement, but it leaves the

processor free to carry out other useful tasks.

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 Hardware Interrupt
ƒ 2 hardware interrupt request pins:
Š NMI (non-maskable interrupt request):
y positive edge-triggered (0→1 transition)
y cannot be masked or “disabled”, triggers type 2 interrupt.
y commonly used for major hardware faults such as RAM
parity check failure.
Š INTR (Interrupt Request) & INTA (Interrupt
Acknowledged):
y INTR is positive level-triggered, it must be held at logic 1
until it is recognized.
y maskable: can be enabled/disabled via the IF (Interrupt
Flag) using STI (Set Interrupt) and CLI (Clear Interrupt)
instruction.
y The µP responds to an INTR request by sending INTA
output, for receiving an interrupt type number via D0-D7.
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INTR/~INTA timing diagram

*Output signal LOCK is used in a multiprocessor system to lock

out the other processors from using the buses.
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 Providing INT Type Number to INTR
74LS74
INTR Q CLK Interrupt
5V Request
D
CLR
INTA 5V
74LS244
1G 2A4 0 Interrupt Type
2A3 1
2G
2A2 0 = 01010100B
D0-D7 2Y4-2Y1 2A1 1 = 54H
8 1A4 0
1Y4-1Y1
1A3 1
8086/8 1A2 0
1A1 0
GND
ƒ Use ~INTA to enable a tri-state buffer such as 74LS244, with a hardwired
type number or set via DIP switches, connecting to low data bus D0-D7.
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Providing INT Type Number to INTR

74LS74
INTR Q CLK Interrupt
5V Request
D
CLR 5V
INTA 10kΩ
74LS244
1G 2A4
2G 2A3
2A2
D0-D7 2Y4-2Y1 2A1
8 1Y4-1Y1 1A4
8086/8 1A3
1A2
1A1
DIP GND
Switch

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 Multiple Devices interfacing to INTR
D7
D6
D5 Low Data Bus
D4
D3
D2
D1
D0
1 1 1 1 1 2 2 2 74LS244
YYYYYYYY
12341234
1G 11112222
INTA 2G AAAAAAAA
12341234
IR0
IR1
IR2
INTR IR3
IR4
IR5
8086/8 74LS30 IR6
IR7 25

Programmable Interrupt Controller 8259A

ƒ Each 8259A can support up to 8 devices using 8 consecutive
programmable interrupt type numbers.
ƒ The devices are prioritized.
ƒ Two 8259A are commonly cascaded, to support 15 devices.
(PC support IRQ0 to IRQ15, by cascading two 8259As, IRQ2
used for cascading).

IRQ0 IRQ8
IRQ1 IRQ9
IRQ2 IRQ10
8259A IRQ3 8259A IRQ11
Master IRQ4 Slave IRQ12
IRQ5 IRQ13
IRQ6 IRQ14
IRQ7 IRQ15

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