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    Labt2 IE

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    Talha Mustafa Jutt
    1) The document describes five Verilog tasks completed by a student named Talha Mustafa for their EE-380L lab. 2) The tasks include designing RS and SR latches using NOR and NAND gates, an RS flip flop using AND and NOR gates, an SR flip flop using NAND gates, and an XOR gate. 3) For each task, the student provides the circuit diagram, truth table, Verilog code, and simulation results.

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    Labt2 IE

    Uploaded by

    Talha Mustafa Jutt
    11 views10 pages
    1) The document describes five Verilog tasks completed by a student named Talha Mustafa for their EE-380L lab. 2) The tasks include designing RS and SR latches using NOR and NAND gates, an RS flip flop using AND and NOR gates, an SR flip flop using NAND gates, and an XOR gate. 3) For each task, the student provides the circuit diagram, truth table, Verilog code, and simulation results.

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    labt2 IE

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    1) The document describes five Verilog tasks completed by a student named Talha Mustafa for their EE-380L lab. 2) The tasks include designing RS and SR latches using NOR and NAND gates, an RS flip flop using AND and NOR gates, an SR flip flop using NAND gates, and an XOR gate. 3) For each task, the student provides the circuit diagram, truth table, Verilog code, and simulation results.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    11 views10 pages

    Labt2 IE

    Uploaded by

    Talha Mustafa Jutt
    1) The document describes five Verilog tasks completed by a student named Talha Mustafa for their EE-380L lab. 2) The tasks include designing RS and SR latches using NOR and NAND gates, an RS flip flop using AND and NOR gates, an SR flip flop using NAND gates, and an XOR gate. 3) For each task, the student provides the circuit diagram, truth table, Verilog code, and simulation results.

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    © All Rights Reserved
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    of 10

    Name: Talha Mustafa Course Code: EE-380L

    Roll No: 2020-EE-060 Section: B

    LAB No: 02
    Object:
    Follow the Verilog system, data types and getting function with design convenient.
    Task 01:
    To design RS latch with nor gate by using data flow modeling.

    Circuit Diagram:

    Truth Table:
    INPUT OUTPUT

    R S Q QB
    0 0 x x
    0 1 1 0
    1 0 0 1
    1 1 0 0

    Coding:
    //desige module
    module gate(Q,QB,R,S);
    input R,S;
    output Q,QB;
    assign Q=~(R|QB);
    assign QB=~(S|Q);
    endmodule

    //stimulus module
    module talha;
    reg R,S;

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    wire Q,QB;
    gate g1(Q,QB,R,S);
    initial
    begin
    R=1'b0;S=1'b0;
    #20
    R=1'b0;S=1'b1;
    #20
    R=1'b1;S=1'b0;
    #20
    R=1'b1;S=1'b1;
    #20
    $finish;
    end
    endmodule
    Result:

    Task:02
    To design SR latch with NAND gate by using data flow modeling.

    Circuit Diagram:

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    Truth Table:

    INPUT OUTPUT

    S R Q QB
    0 0 1 1
    0 1 1 0
    1 0 0 1
    1 1 0 1

    Coding:
    //desige module
    module gate(Q,QB,R,S);
    input R,S;
    output Q,QB;
    assign Q=~(R&QB);
    assign QB=~(S&Q);
    endmodule

    //stimulus module
    module talha;
    reg R,S;
    wire Q,QB;
    gate g1(Q,QB,R,S);
    initial
    begin
    R=1'b0;S=1'b0;
    #20
    R=1'b0;S=1'b1;
    #20

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    R=1'b1;S=1'b0;
    #20
    R=1'b1;S=1'b1;
    #20
    $finish;
    end
    endmodule

    Result:

    Task 3: : To design RS flip flop with AND,NOR gate by using data flow modeling.

    Circuit Diagram:

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    Truth Table:
    INPUT OUTPUT CLK

    R S Q QB Clk
    0 0 X X 0
    0 1 1 0 1
    1 0 0 1 0
    1 1 0 clk 1

    Coding:
    //desige module
    module gate(q,qb,r,s,clk);
    input r,s,clk;
    output q,qb;
    wire a,b;
    assign a=(r&clk);
    assign b=(s&clk);
    assign q=~(a|qb);
    assign qb=~(b|q);
    endmodule

    //stimulus module
    module talha;
    reg r,s,clk;
    wire q,qb;
    gate g1(q,qb,r,s,clk);
    initial
    clk=1'b0;

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    always#5
    clk=~clk;
    initial
    begin
    r=1'b0;s=1'b0;
    #20
    r=1'b0;s=1'b1;
    #20
    r=1'b1;s=1'b0;
    #20
    r=1'b1;s=1'b1;
    #20
    $finish;
    end
    endmodule

    Result:

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    Task 4: To design SR flip flop with NAND gate by using data flow modeling.
    Circuit Diagram:

    Truth Table:
    INPUT OUTPUT CLK

    S R Q QB Clk
    0 0 X X 0
    0 1 0 1 1
    1 0 1 0 0
    1 1 1 clk 1
    Coding:
    //desige module
    module gate(q,qb,s,r,clk);
    input s,r,clk;
    output q,qb;
    wire a,b;
    assign a=~(s&clk);
    assign b=~(r&clk);
    assign q=~(a&qb);
    assign qb=~(b&q);
    endmodule
    //stimulus module
    module talha;

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    reg s,r,clk;
    wire q,qb;
    gate g1(q,qb,s,r,clk);
    initial
    clk=1'b0;
    always#5
    clk=~clk;
    initial
    begin
    s=1'b0; r=1'b0;
    #20
    s=1'b0; r=1'b1;
    #20
    s=1'b1; r=1'b0;
    #20
    s=1'b1; r=1'b1;
    #20
    $finish;
    end
    endmodule

    Result:

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    Task 5: To design XOR gate by using data flow modeling.
    Circuit Diagram:

    Truth Table:
    INPUT OUTPUT

    A B Z
    0 0 0
    0 1 1
    1 0 1
    1 1 0

    Coding:
    //desige module
    module gate(Z,A,B);
    input A,B;
    output Z;
    assign Z=(A^B);
    endmodule

    //stimulus module
    module talha;
    reg A,B;
    wire Z;
    gate g1(Z,A,B);
    initial

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology
    Name: Talha Mustafa Course Code: EE-380L
    Roll No: 2020-EE-060 Section: B
    begin
    A=1'b0; B=1'b0;
    #20
    A=1'b0; B=1'b1;
    #20
    A=1'b1; B=1'b0;
    #20
    A=1'b1; B=1'b1;
    #20
    $finish;
    end
    endmodule

    Result:

    Electronic Engineering Department


    Sir Syed University Of Engineering And Technology

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