Analysis of Noise Margins Due to Device Parameter
Variations in Sub-100nm CMOS Technology
Zhicheng LIANG∗ , Makoto IKEDA∗† , Kunihiro ASADA∗†
∗ Department of Electronic Engineering, The University of Tokyo
† VLSI Design and Education Center(VDEC), The University of Tokyo
7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, JAPAN
{liang,ikeda,asada}@silicon.u-tokyo.ac.jp
Abstract— Increasing level of process variation in the sub-
100nm silicon technology is becoming an important issue. In
this paper we describe an approach to estimate the impact
of process variations on the static CMOS and the dual-rail
PLA down to 32nm process. This approach is built on accurate
variation modeling, published data including the ITRS, Predictive
Technology Models, and Monte-Carlo analysis. The analysis
results show that a challenge due to insufficient noise margins
is posed to the static CMOS at 32nm, and to the dual-rail PLA
from 90nm. Then a one-side virtual ground structure is also
proposed to improve the noise margins of the dual-rail PLA.
The improved dual-rail PLA is shown to work down to 32nm
process with keeping an operational margin of 150mv.
I. I NTRODUCTION
Process parameter variation is increasing and has been
expected as a bottleneck in the sub-100nm CMOS technology.
It is necessary to analyze, predict and alleviate the impact
of these process variations on integrated circuits for future
generations of MOSFET technology.
Compared with the static CMOS design, array-based design
approaches [1]-[3] are supposed to be able to alleviate process
variations and with more manufacturability. In this work,
we describe an approach to estimate the impact of process
variations on these two design styles: the static CMOS and
the PLA (Programmable Logic Array). Our approach is built
on accurate variation modeling, published data including the
ITRS [4], application of Predictive Technology Models (PTM)
[5], and Monte-Carlo analysis to estimate and predict the
trend of noise margins of the two design styles along with
technology scaling.
In Section II, process variations are analyzed in detail. In
Section III and IV, the static CMOS and the dual-rail PLA
are respectively analyzed with respect to process variations.
In section V, a one-side virtual ground structure is proposed
to improve the noise margins of the dual-rail PLA. Section VI
concludes the paper.
II. VARIATION M ODELS
A. Variation Decomposition
Process variations depend on different scales in time and
space. In general, these variations can be classified as lot-
lot (∆XL2L ), wafer-wafer (∆XW 2W ), die-die (∆XD2D ) and
1-4244-1161-0/07/$25.00 ©2007 IEEE
intra-die or called within-die (∆XW ID ) [6]-[9]. A model can
be expressed as
∆X = ∆XL2L + ∆XW 2W + ∆XD2D + ∆XW ID (1)


= ∆XD2D + ∆XW ID−SY S−layout
+∆XW ID−SY S−spatial + ∆XW ID−RAN (2)
The first three components in (1) affect all the devices on
the same chip in the same way, e.g., making the transistor gate
lengths of devices on the same chip all larger or all smaller.
Thus they are summarized into one term - ∆XD2D

in (2).
∆XW ID in (1), on the other hand, may affect different
devices differently on the same chip and they can be further
divided into three components in (2). ∆XW ID−SY S−layout
is the systematic layout pattern dependent variation which
is mainly caused by the layout dependency of the process.
∆XW ID−SY S−spatial is the systematic spatial variation. It
means the variations of transistors lying near each other are
more correlated, than the variations of transistors that are far
apart. The last component ∆XW ID−RAN , which is caused by
process fluctuations, is totally random.
B. Characteristics Analysis of static CMOS and PLA Varia-
tions


∆XD2D , ∆XW ID−SY S−spatial and ∆XW ID−RAN are
substantially independent of the physical implementation of
the IC. Hence, for both the static CMOS and the PLA,


the characteristics of them are the same. ∆XD2D and
∆XW ID−RAN are components of variations with the spa-
tial correlation of 1 and 0 within a chip, respectively.
∆XW ID−SY S−spatial is assumed to be systematic with spatial
correlation=1 on small area in this study [6]-[8].
The difference between the static CMOS and the PLA
regarding variations lies in ∆XW ID−SY S−layout . Early in the
design stage, the layout of the static CMOS is undecided.
Hence, ∆XW ID−SY S−layout is assumed to be random and
thus with spatial correlation ≈ 0. However, the layout of the
PLA is regular and decided; therefore ∆XW ID−SY S−layout
can be assumed to be systematic, with spatial correlation ≈ 1
and with small magnitude [9][10].
C. Sources of Variations Considered in This Study
In this paper we consider process variations in physical
gate length (Lg ) and width (Wg ), effective gate length (Lef f ),
 TABLE I
The variations of Lg , Wg , Lef f , Tox , Lovs and Lovd follow
3σ SETTINGS OF PARAMETER VARIATIONS
(4) and the variations of µ and Vth are totally random in this
Physical gate length (nm) 90 65 45 32 study.
3σLg /Lg , 3σWg /Lg 10% 10% 10% 12%
Based on the above variation modeling, we analyze the
3σLef f /Lef f 20% 20% 20% 20%
noise margins of the static CMOS and the dual-rail PLA
3σTox /Tox 4% 4% 4% 4% through 1000 runs of Monte-Carlo simulation with SPICE,
3σLovs /Lovs , 3σLovd /Lovd 15% 15% 15% 21% using the PTM from 90nm to 32nm technology [5]. Vdd is
3σµ /µ 10% 10% 10% 10% set from 1.2v to 0.9v for the four processes, respectively. Vdd
noise is set by σV dd = 50mv. Based on the simulation results,
TABLE II we use 6σ assurance for fault-free operations. That means out
σ2

σ 2 SETTINGS OF EACH COMPONENT IN (4) (A:
X
D2D
, B: of 1 billion gates only 1 gate exceeds the predetermined margin
σX2
2
σX 2
σX σX2 of safe operations.
W ID−SY S−layout W ID−SY S−spatial W ID−RAN
2
σX
, C: 2
σX
, D: 2
σX
)
III. THE VARIATION A NALYSIS OF STATIC CMOS
Component A B C D
In this section, we analyze the trend of noise margins of a
static CMOS 40% 30% 20% 10%
static CMOS inverter (INV) along with process scaling.
PLA 40% 3% 20% 10%
First the unity gain definition of the noise margins of an
INV is defined as Fig. 1 [12]. The region of the input voltage
between dVout /dVin = −1 and ground is defined as LOW
gate oxide thickness (Tox ), gate-source and gate-drain overlap noise margin (N ML ). The region between dVout /dVin = −1
length (Lovs , Lovd ), mobility of carriers (µ) and threshold and power (Vdd) is defined as HIGH noise margin (N MH ).
voltage (∆Vth ). All the variations are assumed to follow the The switching threshold of an INV is defined as Vm .
normal distribution and the standard deviations (σ) are listed
in Tab. I. 3σ of Lg , Wg , Lef f , Tox are referred from ITRS Vout
(high performance) [4]. 3σ of Lovs and Lovd are calculated
Vdd
by (3). 3σ of µ is assumed to be 10% in this study. σ of each
term in (2) can be expressed as (4) and they are set as Tab. II NML
[6]-[10]. Note that in Tab. II, term B of the PLA is assumed d Vout = 1
to be 1/10 of the static CMOS [10]. d Vin

Vm
σL2 + σ2
Lef f NMH
σLovs = σLovd = g
(3)
2
σX2
= σX 2
+ σX 2 45 Vin


D2D W ID−SY S−layout
2
+σX 2
+ σX (4) Vm Vdd
W ID−SY S−spatial W ID−RAN
2
= (A + B + C + D)σX Fig. 1. Unity gain definition of LOW noise margin (N ML ) and HIGH noise
margin (N MH ) of an inverter on the voltage transfer characteristic.
Moreover, variance of the gate-source and gate-drain over-
lap capacitance (Covs , Covd ) is estimated to be the combined 9.5
variance of Tox and Lovs , or Tox and Lovd based on the Ion variation of NMOS,90nm
σ(Ion)/mean(Ion) (%)

9
parallel capacitor across the gate oxide as 8.5
8
ox ox
∆Covs,d = (Lovs,d + ∆Lovs,d ) − Lovs,d 7.5
Tox + ∆Tox Tox 7
6.5
1) Random Fluctuaion of Dopants: In scaled CMOS de- 6
vices, there exists a statistical fluctuation in the number of 5.5
dopants, resulting in a threshold voltage variation (∆Vth ). This 5
discrete dopant effect on ∆Vth is estimated as [11] 4.5
1 2 3 4 5 6 7 8 9 10
 Wg/Lg
1 4 si q 3 Nch (|2φf + VBS |) 1
σVth =  (5) Fig. 2. Wg /Lg vs. σ(Ion)/mean(Ion) calculated by 1000 runs of Monte-
Cox 8 Lef f Wef f Carlo simulation. Wg /Lg = 4 is chosen for NMOS of the inverter because
when Wg /Lg > 2, the normalized variation of Ion approaches a stable value.
Cox is the gate oxide capacitance per unit area, si is the
silicon permittivity, q is the electron charge, Nch is the channel
doping concentration, φf is the Fermi potential and VBS is Regarding the size of the INV, Wg /Lg = 4 is chosen for the
the body bias voltage, respectively. VBS = 0 is assumed in NMOS based on Fig. 2, which indicates when Wg /Lg > 2,
the following analysis. the normalized variation of the on-current (Ion) of an NMOS
approaches a stabel value. After deciding the size of the
NMOS, the size of the PMOS is chosen to make Vm = V dd/2. 120
LOW noise margin
120
LOW noise margin
HIGH noise margin HIGH noise margin

quantity per 5mV

quantity per 5mV

100 100
From the simulation results, we estimate the trend of
80 80
noise margins of the INV defined in Fig 1. For comparison,
60 60
simulation results are shown in Fig. 3 in a form of voltage
40 40
transfer characteristic. It indicates that a pair of maximum
20 20
rectangles can no longer be embedded inside the loop when
0 0
the process shrinks to 32nm. The noise margin profiles of 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
voltage(V) voltage(V)
the INV are shown in Fig. 4. They are histograms with an
interval of 5mv. The trend of noise margins of the INV with 90nm 65nm
120 120
and without Vdd noise is shown in Fig. 5. It shows that there LOW noise margin
HIGH noise margin
LOW noise margin
HIGH noise margin

quantity per 5mV

quantity per 5mV

100 100
is no N MH left for 6σ assurance for a static CMOS INV at
80 80
32nm process when σV dd = 50mv. Insufficient noise margins
60 60
mean high possibility of malfunction and thus we predict the 40 40
static CMOS can not work reliably at 32nm process. Hence, 20 20
other circuit design styles that suppress the impact of process 0 0
variations should be investigated. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
voltage(V) voltage(V)

1.2 1.2 45nm 32nm

output/input voltage (V)

output/input voltage (V)

90nm 65nm Fig. 4. Noise margin profiles of an inverter defined in Fig. 1 along with
1 1 scaling. They are histograms with an interval of 5mv.
0.8 0.8
0.6 0.6 LOW noise margin
0.4 0.4 500

0.2 0.2 noise margin (mV) mean

400
0 0
0 0.5 1 0 0.5 1 300
mean 6σ, ideal Vdd
input/output voltage (V) input/output voltage (V)
1.2 1.2
output/input voltage (V)

output/input voltage (V)

200
45nm 32nm mean 6σ,
σ(Vdd)=50mv
1 1
100
0.8 0.8
0.6 0.6 0
90 65 45 32
0.4 0.4
physical gate length(nm)
0.2 0.2
0 0
0 0.5 1 0 0.5 1 HIGH noise margin
input/output voltage (V) input/output voltage (V) 500

Fig. 3. Voltage transfer characteristic of an inverter. A pair of maximum mean

noise margin (mV)

rectangles can no longer be embedded inside the loop when the process shrinks 400
to 32nm.
300
mean 6σ, ideal Vdd
IV. THE VARIATION A NALYSIS OF THE D UAL -R AIL PLA 200

A. The Dual-Rail PLA with Latch Sense Amplifiers [3] mean 6σ,
100
σ(Vdd)=50mv
This section begins with a simple review of the PLA which
will be analyzed in this paper. Fig. 6 shows a column circuit of 0
90 65 45 32
the dynamic dual-rail PLA with latch sense amplifiers (sense-
physical gate length(nm)
amp). Logical OR and NOR of the input signals (X0 − Xn−1 )
can be obtained from the output signals, OU T and OU T ,
respectively. Logical AND is also obtained by performing Fig. 5. The trend of noise margins of an inverter according to the unity gain
definition of Fig. 1 along with scaling. When σV dd = 50mv, there is no
logical NOR of complement input signals. Thus, an AND- HIGH noise margin left for 6σ assurance for an inverter at 32nm. thus we
plane and an OR-plane for a PLA can be realized by arranging predict the static CMOS can not work reliably at 32nm process.
the column circuits. By using a sense-amp, the output signals
are activated by sensing the differential voltage between the
bit-lines, BL and BL. Virtual ground (VG) is provided to Fig. 7 shows a timing diagram of control signals. In phase 1,
reduce the voltage swings of the bit-lines. the P C signal and all the input signals, (X0 −Xn−1 and X0 −
 X n-1 loop sense-amp to open loop as Fig. 8 to estimate the input
X n-1 2W Logic Cell
2W
offset voltage (Voff) variations, which is plotted in Fig. 9. Voff
variations increase along with process scaling due to increasing
BL BL process variations.
X0
X0 2W Logic Cell
2W 2W
Logic PC 2W
W Vout+
Part Reference Cell Vout-
W
Sense
VG Vin+ 4W 4W Vin- Amplifier
PC VG Controller
13W

4W 4W SAE
PC Precharge & 6W
Equalization Circuit W=2.25Lg
4W
SAE
4W 4W
Fig. 8. The closed loop sense amplifier used in Fig. 6 is changed to open
2W 2W loop to estimate the input offset voltage variations along with process scaling.

Sense OUT OUT

4W 4W
Amplifier

SAE
6W 1 90nm 1 65nm

Vout- (V)

Vout- (V)
0.5 0.5
W=2.25Lg
Vout+ 0 0

Vout+
Fig. 6. The column circuit of the dual-rail PLA proposed in [3] -0.5 -0.5

Phase 1 Phase 2 Phase 1 -1 -1

X,X
-1 0 1 -1 0 1
PC Vin+ Vin- (V) Vin+ Vin- (V)
Generated
SAE
Delay
1 45nm 1 32nm

Vout- (V)
Vout- (V)

BL , BL
0.5 0.5
OUT , OUT
0 0
Vout+
Vout+

Fig. 7. The timing diagram of signals in Fig. 6 -0.5 -0.5

-1 -1

Xn−1 ,) are low. Thus, the bit-lines are pre-charged high and
equalized. At the same time, VG is discharged low. When the
P C signal becomes high and the input signals are activated,
the circuit enters phase 2.
In phase 2, BL is pulled down by charge sharing with
VG through a reference cell. When at least one of the basic
logic cells pulls BL down, the voltage of BL becomes
lower than that of BL. Otherwise, BL stays high. This is
because the device size of the basic logic cells is twice of
the reference cell. The SAE signal is activated when the
developed voltage difference between the bit-lines becomes
larger than the designed sense voltage. By activating the sense-
amp, one of the output signals, i.e., OU T or OU T becomes
high depending on the developed voltage difference. After the
activation of the sense amplifier, the P C signal becomes low
and the circuit starts to pre-charge the bit-lines.
B. The Variation Analysis of the dual-rail PLA
We analyze the trend of noise margins of the described PLA
above. We divide a column PLA into 2 parts - the logic part
and the sense-amp as shown in Fig. 6. First change the closed
-1 0 1 -1 0 1
Vin+ Vin- (V) Vin+ Vin- (V)
Fig. 9. Input offset voltage variations of the sense-amp of Fig. 8
To work properly, the differential voltage generated between
bit lines of the logic part (Vdiff) must be larger than Voff of
the sense-amp. Fig. 10 shows the variations of Vdiff when
only one input is high. The upper graph shows the voltage of
BL and BL. The lower graph shows Vdiff: VBL − VBL . It
shows that there is no Vdiff margin from 45nm process.
Fig. 11 gives the profiles of Voff and the maximum Vdiff.
They are histograms with an interval of 5mv. In this paper
the noise margin of the dual-rail PLA is defined as the space
between the Voff and the maximum Vdiff profiles, which is
insufficient and disappears from 65nm process.
V. ONE - SIDE VIRTUAL GROUND STRUCTURE (1- SIDE VG)
TO IMPROVE THE NOISE MARGINS OF THE DUAL - RAIL PLA
To enlarge the noise margins of the dual-rail PLA, we
propose a one-side virtual ground (1-side VG) structure for
the logic part, which is showed as Fig. 12.The voltage of
VBL & VBL (V)

VBL & VBL (V)

VBL VBL the variations of Vdiff of the 1-side VG structure with one
1 1
0.5 VBL 0.5 VBL
input, when input=1 and input=0 along with process scaling.
0 0
Compared to Fig. 10, one can see that Vdiff is enlarged, which
0 1n 2n 3n 0 1n 2n 3n means noise margins are improved. Note that Vdiff decreases
Time (s) Time (s)
0.35 0.35 gradually in time at 32nm process due to large leakage current.

Vdiff (V)
Vdiff (V)

0 0
-0.1 -0.1 X0
0 1n 2n 3n 0 1n 2n 3n X0 2W
Time (s) Time (s) Logic Cell
2W
90nm 65nm PC
W
Reference Cell
VBL & VBL (V)

VBL & VBL (V)

W
1 VBL 1 VBL

0.5 0.5 VG
VBL VBL PC
Logic 13W
1 VG Controller
0 0 Part
0 1n 2n 3n 0 1n 2n 3n 4W 4W
Time (s) Time (s) PC Precharge &
0.35 0.35
Equalization Circuit
Vdiff (V)
Vdiff (V)

4W
4W 4W
0 0 SAE
-0.1 -0.1
0 1n 2n 3n 0 1n 2n 3n
Time (s) Time (s)
W=2.25Lg
45nm 32nm BL BL
Fig. 10. Variations of differential voltage between bit lines (Vdiff) when
only one input is high. Of each process, the upper graph shows the voltage of
BL and BL. The lower graph shows Vdiff: VBL − VBL . There is no Vdiff Fig. 12. A one-side virtual ground structure proposed in this paper for the
margin from 45nm process. logic part to enlarge the differential voltage generated between bit lines to
improve the noise margins of the dual-rail PLA (Fig. 6)
VBL & VBL (V)

VBL & VBL (V)

120 max Vdiff 120 max Vdiff
Voff Voff 1 VBL 1 VBL
quantity per 5mV

quantity per 5mV

100 100 VBL VBL

80 80
0.5 0.5
60 60 0 0
0 0.2n 0.4n 0 0.2n 0.4n
40 40 Time (s) Time (s)
Vdiff (V)

Vdiff (V)
20 20
0.6 0.6
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.4 0.4
voltage(V) voltage(V) 0.2 0.2
0 0
90nm 65nm 0 0.2n 0.4n 0 0.2n 0.4n
Time (s) Time (s)
120 max Vdiff 120 max Vdiff
Voff Voff
90nm 65nm
quantity per 5mV

quantity per 5mV

100 100
VBL & VBL (V)
VBL & VBL (V)

80 80 VBL
1 1
60 60 VBL VBL
0.5 0.5
40 40
0 VBL
20 20 0
0 0.2n 0.4n 0 0.2n 0.4n
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4
0
-0.2 -0.1 0 0.1 0.2 0.3 0.4
Time (s) Time (s)
Vdiff (V)

Vdiff (V)

voltage(V) voltage(V) 0.6 0.6

45nm 32nm 0.4 0.4
0.2 0.2
Fig. 11. The profiles of Voff and the maximum Vdiff. They are histograms 0 0
with an interval of 5mv. In this paper the noise margin of the dual-rail PLA 0 0.2n 0.4n 0 0.2n 0.4n
is defined as the space between the Voff and the maximum Vdiff profiles, Time (s) Time (s)
which is insufficient and disappears from 65nm process. (Voff: input offset
voltage of sense-amp (Fig. 9), max Vdiff: the maximum differential voltage
45nm 32nm
generated between bit lines (Fig. 10) Fig. 13. Variations of Vdiff of the one-side virtual ground structure with 1
input (Fig. 12). Of each process, the upper graph shows the voltage of BL
and BL (VBL =V dd when input=0 or VBL =0 when input=1. On the other
hand, VBL is always pulled down to about V dd/2 by charge sharing with
BL remains as Vdd when all the input signals are low, or VG through a reference cell.). The lower graph shows Vdiff: VBL − VBL
is pulled down to ground level when at least one of the input for input=1 and VBL − VBL for input=0
signals is high. On the other hand, the voltage of BL is always
pulled down to about V dd/2 by charge sharing with VG The trend of noise margins of the 1-side VG dual-rail PLA
through a reference cell. This scheme enlarges Vdiff and thus for both input=1 and input=0, with and without Vdd noise, is
improves the noise margins of the dual-rail PLA. Fig. 13 shows shown in Fig. 14. Vdiff is measured at 300ps. It shows the
 800
Input=1
σ(Vdd)=50mV

mean of noise margin (mV)

800 700
700 mean(1VG PLA)
600
Vdiff-Voff (mV)
600
mean(Vdiff) mean(Voff) 500
500 mean(INV)
400
400 mean 6σ(Vdiff Voff),
ideal Vdd mean UP
300
300
200 mean(original PLA)
200 mean 6σ(Vdiff Voff), σ(Vdd)=50mV
100 100
σ2(Vdiff Voff) = σ2(Vdiff) + σ2(Voff)
0 0
90 65 45 32 90 65 45 32
physical gate length(nm) physical gate length(nm)
600
Input=0
σ(Vdd)=50mV
800

6σ of noise margin (mV)

500
700
mean(Vdiff) mean(Voff) mean 6σ(1VG PLA)
Vdiff-Voff (mV)

600 400

500 mean 6σ(Vdiff Voff), mean 6σ UP

300
ideal Vdd
400
300 200 mean 6σ(INV)
mean 6σ(Vdiff Voff), σ(Vdd)=50mV
200
100
100 σ2(Vdiff Voff) = σ2(Vdiff) + σ2(Voff) mean 6σ(original PLA)
0 0
90 65 45 32 90 65 45 32
physical gate length(nm) physical gate length(nm)

Fig. 14. The trend of noise margins of the one-side virtual ground dual-rail
PLA. Vdiff is measured at 300ps. It shows the noise margins are increased.
This means the improved dual-rail PLA works more reliably along with
process scaling.
Fig. 15. The comparison of noise margins of a static CMOS INV (N MH ),
the original dual-rail PLA and the 1-side VG dual-rail PLA. While there is
no noise margin left for the 6σ assurance for the static CMOS from 32nm
process and for the original dual-rail PLA from 90nm process, the improved
dual-rail PLA with 1-side VG is shown to work down to 32nm process with
keeping an operational margin of 150mv.

noise margins are increased. This means the improved dual-

rail PLA works more reliably along with process scaling.
At last, The comparison of noise margins of a static CMOS
INV (N MH ), the original dual-rail PLA and the 1-side VG
dual-rail PLA are compared as Fig. 15. While there is no
noise margin left for 6σ assurance for static CMOS from 32nm
process and for the original dual-rail PLA from 90nm process,
the improved dual-rail PLA with 1-side VG is shown to work
down to 32nm process with keeping an operational margin of
150mv.
VI. C ONCLUSIONS
In this paper we estimated and predicted the impact of the
increasing process parameter variations on the noise margins
of the static CMOS and the dual-rail PLA down to 32nm pro-
cess, using accurate variation models, published data including
the ITRS, Predictive Technology Models, and Monte-Carlo
simulation with SPICE. The analysis results showed that a
challenge due to insufficient noise margins was posed to the
static CMOS at 32nm, and to the dual-railPLA from 90nm.
Then a one-side virtual ground structure was proposed to
improve the noise margins of the dual-rail PLA. The improved
dual-rail PLA was shown to work down to 32nm process with
keeping an operational margin of 150mv.
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