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    Pavansaikumar Samudrapu
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    This document appears to be an exam for a System Design Through Verilog course. It contains 6 questions, each worth 10 marks, and covers various topics related to Verilog HDL including: - Explanation of terms like functional verification, simulation tools, keywords, identifiers, strings, and data types. - Construction of logic gates and circuits like JK flip-flop, half adder, multiplexer using Verilog modules. - Syntax of Verilog constructs like for loops and disable. - Modeling of bi-directional gates and OR gate with MOS switches in Verilog. - File-based tasks, functions, user defined primitives, and modeling of simple latches and

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    Emi ledandi

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    V18ECT29-SDTV

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    This document appears to be an exam for a System Design Through Verilog course. It contains 6 questions, each worth 10 marks, and covers various topics related to Verilog HDL including: - Explanation of terms like functional verification, simulation tools, keywords, identifiers, strings, and data types. - Construction of logic gates and circuits like JK flip-flop, half adder, multiplexer using Verilog modules. - Syntax of Verilog constructs like for loops and disable. - Modeling of bi-directional gates and OR gate with MOS switches in Verilog. - File-based tasks, functions, user defined primitives, and modeling of simple latches and

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    7 views2 pages

    V18ect29 SDTV

    Uploaded by

    Pavansaikumar Samudrapu
    This document appears to be an exam for a System Design Through Verilog course. It contains 6 questions, each worth 10 marks, and covers various topics related to Verilog HDL including: - Explanation of terms like functional verification, simulation tools, keywords, identifiers, strings, and data types. - Construction of logic gates and circuits like JK flip-flop, half adder, multiplexer using Verilog modules. - Syntax of Verilog constructs like for loops and disable. - Modeling of bi-directional gates and OR gate with MOS switches in Verilog. - File-based tasks, functions, user defined primitives, and modeling of simple latches and

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    of 2

    Course Code: V18ECT29 V18 HTNO

    SRI VASAVI ENGINEERING COLLEGE (Autonomous)


    B.Tech VII Semester Advanced Supplementary Examinations, April-2022
    SYSTEM DESIGN THROUGH VERILOG
    (Electronics and Communication Engineering)
    Time: 3 Hrs Max. Marks: 60

    Answer All the Questions


    All Questions Carry Equal Marks

    1. 10 M
    A. i. Explain the following: (i) Strengths (ii) Parameters. CO1-K2(5M)
    ii. Explain lexical tokens in Verilog HDL. CO1-K2(5M)
    OR
    B. i. Explain the following terms relevant to Verilog HDL CO1-K2(5M)
    (i) Functional Verification (ii) Simulation tools.
    ii. Discuss the following terms relevant to Verilog HDL CO1-K2(5M)
    (i) Keywords (ii) Identifiers (iii) Strings (iv) Data types.

    2. 10 M
    A. i. Construct JK flip flop using gate primitives. CO2-K2(5M)
    ii. Develop Verilog module for Half adder circuit using Ex-OR gates and AND CO2-K3(5M)
    gates with a neat diagram.
    OR
    B. i. Explain the construction of any two Flip flops with gate primitives. CO2-K2(5M)
    ii. Develop Verilog module and test bench for this operation: Add two pairs of CO2-K3(5M)
    BCD nibbles -2 decimal numbers each of two digits.

    3. 10 M
    A. i. Explain the syntax of (i) for loop (ii) disable construct with suitable examples. CO3-K2(5M)
    ii. Develop a Verilog code for 8×1 MUX using case statement. CO3-K3(5M)
    OR
    B. i. Construct Verilog code for OR gate using for and disable constructs, also show CO3-K2(5M)
    the simulation results.
    ii. Develop Verilog module for AND, NAND and NOR functions using the CO3-K3(5M)
    disable construct.

    4. 10 M
    A. i. Explain Bi-directional gates with suitable logic diagrams and give their Verilog CO4-K2(5M)
    code using switch level modeling.
    ii. Develop Verilog code and test bench for OR gate with MOS switches with a neat CO4-K3(5M)
    diagram.
    OR
    B. i. Explain continuous assignment structures relevant to dataflow modeling with CO4-K2(5M)
    suitable examples.
    ii. Develop the skeletal edge-triggered flip flop with gates through continuous CO4-K3(5M)
    assignments and test bench.
    5. 10 M
    A. i. Explain File based tasks and functions in Verilog. CO5-K2(5M)
    ii. Explain User Defined Primitive (UDP) with an example. CO5-K2(5M)
    OR
    B. i. Explain simple latch with Verilog module. CO5-K2(5M)
    ii. Explain Moore machine. CO5-K2(5M)

    6. 10 M
    A. i. Explain the synthesis process of explicit state machines. CO6-K2(5M)
    ii. Illustrate the synthesis of sequential logic with flip flops. CO6-K3(5M)
    OR
    B. i. Differentiate accidental synthesis of latches and intentional synthesis of latches. CO6-K2(5M)
    ii. Illustrate the level sensitive cyclic behaviour with examples. CO6-K3(5M)

    * * *

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