Design Approach for the Folde ‘ascode Op Ai Step| _ Relationship Design Equation/Constraint Comments 1 | Slew Rate Is = SRC], 2 | Bias currents in output cascodes ly 12h 0 15h Avoid zero current in cascodes 3. [Maximum output 2s 2 Vsps(sat-Vsp7(sat) voltage, SEV spe Sy KpVspp 8 ‘Ss and Sg= $7) =0.5[¥pp-Voudmax)] outta) 4° | Minimum output hy 2g Vpso(sat)=/Ds11(sat) voltage, SUKy Pps 2 Ky psy? (S10-S11nd Sg-S9) |= 5[V,,,,(anin)-Vs5] Youtlmin) . ° Sm1 Sui? GBC? SPS" Ky ~ EyTs 6 | Minimum input 2s CM 35 eee " - 2 Ky Vin(ain)-Vss-(EVS) Yn) 7 | Maximum input ly > $4 and $5 must meet or cM S4= Ss Kp’ Vpp-Vinkmas)*V 71) exceed value in step 3 | Dilfereatel Yout {&m1 m2 _ 24) Rips Bas) Voltage Gain Vin 2 + 2+ )Rowt = (2428! SmPRout trast 9 | Power dissipation Paiss = Vpp-Vss\s*Ho~) (CMOS Analog Cireat Design OPE, Allen - 2006Example 6.5-3 Design of a Folded-Cascode Op Amp Follow the procedure given to design the folded-cascode op amp when the slew rate is 10V/ps, the load capacitor is 10pF, the maximum and minimum output voltages are £2V for £2.5V power supplies, the GB is 10MHz, the minimum input common mode voltage is -1.5V and the maximum input common mode voltage is 2.5V. The differential voltage gain should be greater than 5,000V/V and the power dissipation should be less than SmW. Use channel lengths of ym. Solution Following the approach outlined above we obtain the following results, J, = SR-Cy = 10x106-10-11 = 1008. Select Jy =/5 = 125A. Next, we see that the value of 0.5(Vpp-M,,Amax)) is 0.5V/2 or 0.25V. Thus, 2125HA 2125-16 Sa= 55 =50paV20.25V2= 50 = 80 and assuming worst case currents in M6 and M7 gives, 2125 125-16 = 50" AIV2(0.25V. So=5: The value of 0.5(¥,,,(min)-I/ss!) is also 0.25V which gives the value of Ss, So, Syq and Syyas (CMOS Analog Circuit Design © PE. Allen - 2006 Tn step 5, the value of GB gives Sy and S> as GB2-Cj? (20x10®)2(10-1)2 110x10-6:100x10~ ‘The minimum input common mode voltage defines $3 as 213 200x10-6 hs b 100 Kyl itminrFs5"\fRo5, - rnfe oxt0-4-1.542.5-\ eS | We need to check that the values of Sy and Ss are large enough to satisfy the maximum input common mode voltage. The maximum input common mode voltage of 2.5 requires S3= 2ly 2125p S4= S52 KOT pp-V,amaxyeV ae = 50x10 WAN2[0.7VE which is much less than 80. In fact, with Sy = S5 = 80, the maximum input common mode voltage is 3V. =102 The power dissipation is found to be Piss = SV(L25pA+125 pA) = 1.25mWExample 63:3 - Continued The small-signal voltage gain requires the following values to evaluate: Sy.85: Sp) = V2F125-50RO = 1000S and gy, = 125x10-6-0.05 = 6.25S SoS]! Sy =V2-75-50-80 = 774.6uS and gg, = 75x10°6-0.05 = 3.75 nS Ss. So. So. S11: Spy =V2°75-110-36.36 = 774.6S and gy, =75x10-6-0.04 = 3S Sy. S2: Sp = V2'50-110-35.9 = 628uS and gy, = 50x10-6(0.04) = 2S Thus, 1\1 Ry ~ Sm9'ds9'ds11 = c7.6us\qtslses} = 86.07MQ 1 1 Rour™ 86 07MOI774.605) 3-788) ousee25n8) = 19.40MQ . RilSasrtSas4) 86.0TMQ(2uS+6.25pS)(3.75 4S) be guttast = TIAGO ES = 3.4875 The small-signal, differential-input, voltage gain is Ava eae a 2E) SmBRou = ‘The gain is larger than required by the specifications which should be okay. 76. elo. 628x10-3-19.40x106 = 7,464 V/V