IC Design of

Power Management Circuits (II)

Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki

International Symposium on Integrated Circuits

Singapore, Dec. 14, 2009
 Part II

Switching Converters:
IC Design

Ki 2
 Content

IC Design: Control Loop

Biasing
RTCT oscillator
Comparators, hysteretic comparator
Operational amplifier
Current sensors
Compensation ramp

IC Design: Power Stage

Power transistor and gate drive
Synchronous rectification
Active diodes

IC Design: Peripheral Circuits

Under voltage lockout (UVLO)
Over current protection (OCP)
Soft start circuit
Ki 3
 Foreword

Analog IC design is ENGINEERING.

Analog IC design is ART.

There is no best design but good and reasonable designs.

Design examples shown are suggestions rather than

instructions, and unavoidably opinionated.

Suggestions and corrections are most welcome to make

a more relevant and accurate presentation.

Ki 4
 Guidelines for Analog IC Design

(1) Length of transistors are at least 4λ to 8λ for better

matching.

(2) Gate overdrive voltage Vov = (Vgs–Vt) of a transistor

should be at least 150mV for better current mirror
matching.

(3) Use 1% rule as initial point for matching, delay and

losses.

Ki 5
 PWM Voltage Mode Control (1)

A regulated switching converter consists of the power stage and

the feedback circuit.

MP Vo
L

Vg MN RL
C ck
R1 ramp va
va EA bVo
CMP A(s) Q
Q R Vref
R2
Q
Q S va
ramp
ck

For a buck converter, if an on-chip charge pump is not available,

then the NMOS power switch is replaced by a PMOS power switch.
Ki 6
 Current Mode PWM with Compensation Ramp

In practice, the output of EA (Va) should not be tempered, and a

compensation ramp of +mc is added to m1 instead.
L
MP Vo
iA
Vdd MN RL
C
R1

va EA bVo
CMP A(s)
Q R Vref
R2
Vdd
Q S
iA / N
(m1 + mc )R f −(m2 − mc )R f V2I
va ck
vb vb
NR f ramp from OSC
DT compensation
Ki ramp 7
 Synchronous Rectification

To eliminate loss due to forward diode drop, the power diode is

replaced by a power NMOS MN, and the scheme is known as
synchronous rectification. To eliminate short-circuit loss of MP and
MN, a break-before-make (BBM) buffer is used.
L
Q, VP
MP
iA
Vdd MN RL
VN
C

VP VN
Q R φ1 =
BBM Q
φ1 VP
Buffer Q S (ck) φ1

φ2 = VN
Additional logic is needed φ2 φ2
for DCM operation.
Ki Non-overlapping φ1 and φ2 8
 Simple Current Source and Current Mirror

The simple current source is supply dependent. If the power

supply would change considerably, for example, from 5V to 12V,
then the simple current source should not be used.

Vdd
1 ⎛W⎞ Vdd − V1
I1 = μnC ox ⎜ ⎟ ( V1 − Vtn ) =
2

2 ⎝ L ⎠1 R1
R1
(W / L)2 (1 + λn Vds2 )
I1 I2 I2 = I1
(W / L)1 (1 + λn Vds1 )
V1
(W / L)2
≈ I1 (1 + λn (Vds2 − Vds1 ))
M1 M2 (W / L)1

Ki 9
 CMOS Widlar Current Source

The self-biased CMOS Widlar current source appears very often in

textbooks. The version with a startup circuit is shown below.
Vdd 1 ⎛W⎞
I1 = μnC ox ⎜ ⎟ ( Vgs1 − I1R1 − Vtn )
2

long 2 ⎝ L ⎠1
L 6 M6 M3 V2
1 ⎛W⎞
I2 = μnC ox ⎜ ⎟ ( Vgs2 − Vtn )
M4 2

2 ⎝ L ⎠2

I1 I2 For (W/L)1 = 4(W/L)2 gives

V3
2I1 2
v1i v1o gm1 = = ⇒ gm1R1 = 2
V1 − Vtn R1
M7 M5 M1 V1
M2
4 : 1 A positive loop exists:
wide R1
W5 −v −g / g g −2
TV1 = 1o = m1 m2 m4 =
v1i 1 + gm1R1 gm3 3
startup
Ki 10
 CMOS Peaking Current Source (1)

The original peaking current source was designed in bipolar

processes. [Gray 01] gives a CMOS sub-threshold version, while
we suggest operating all transistors in the active region [Lo 09].
This current source does not need a start-up circuit.
Vdd
1 ⎛W⎞ V − V1
μnC ox ⎜ ⎟ ( V1 − Vtn ) = dd
2
M3 I1 =
Rb V3 2 ⎝ L ⎠1 Rb

1 ⎛W⎞
I2 = μnC ox ⎜ ⎟ ( V1 − I1R1 − Vtn )
2
I1 I2
2 ⎝ L ⎠2
V1
R1 dI2 V − Vtn
= 0 ⇒ I1R1 = 1
V2 dI1 2
M2
M1 V2
For I2 = I1, set (W/L)2 = 4(W/L)1.
1 : 4
Ki 11
 CMOS Peaking Current Source (2)

The peaking current source has very good power supply rejection.
v dd
From previous analysis,
Rb V1 − Vtn 1
1 / gm3 R1 = = ⇒ gm1R1 = 1
2I1 gm1
v1 v3

R1
Small signal analysis gives
v2
v 2 1 − gm1R1
= =0
v dd 1 + gm1R b
gm1 v1 gm2 v 2
v dd − v 3 gm2 1 − gm1R1
= =0
v dd gm3 1 + gm1R b

That means the currents generated by current mirroring using V2

and (Vdd–V3) has a very low dependence on the supply voltage.
Ki 12
 CMOS Peaking Current Source (3)

Assuming a 0.25µ CMOS process:

µnCox = 50µA/V2 Vtn = 0.8V λnLn = 0.05µm/V
µpCox = 25µA/V2 |Vtp| = 0.8V |λp|Lp = 0.05µm/V

Example: Vdd ranges from 4V to 6V, need I2 = 40μA.

Set ∂I2/∂I1 = 0 at Vdd = 5V with I1(5V) = 40μA. (W/L)2 = 40 gives

Vgs2-Vtn = 200mV, and 1mV change in Vtn causes 1% change in I2
(1% rule):
I1
Vtn = 0.799V ⇒ I2 = 40.4μA 50μA
Vtn = 0.800V ⇒ I2 = 40.0μA
Vtn = 0.801V ⇒ I2 = 39.6μA 40μA I2

Vdd I1 I2 30μA I1
4V 30μA 38.7μA
Vdd
5V 40μA 40.0μA 4V 5V 6V
Ki 6V 50μA 38.9μA 13
 Self-Biased Peaking Current Source

A current mirror (M3, M4) can be used to replace the large Rb to

reduce silicon area. The peaking current source becomes self-biased
and needs a startup circuit (may not be favorable).
Vdd
long M4
L 6 M6 M3 V2

I1 I2
Vb1

Vb2 R1

M7 M5 V1
M2
wide M1 V1
W5 1 : 4

startup
Ki 14
 RTCT Oscillator (1)

The RTCT oscillator generates a ramp that synchronized with the

clock, which fits the requirement of a PWM switching converter.

Vdd

Ich = Vref / R T

Vref EA VH CMP
VH S Q
ck
VL
VC T ramp Vm
Idch
RT Mdch CMP T = 1 / fs
CT VL
R
current
generator hysteretic
comparator

Ki 15
 RTCT Oscillator (2)

The charging current Ich is well-controlled by a bandgap derived

voltage Vref and an accurate 1% (external) resistor RT (1% rule).

Ich charges an accurate 1% (external) capacitor CT slowly from the

lower bound VL to the upper bound VH. The ramp excursion is Vm.

The hysteretic comparator trips when VCT > VH, and ck = 1.

When ck = 1, the NMOS Mdch is turned on, and discharges CT with

a large current Idch that is around 10 times of Ich.

When VCT < VL, the comparator trips again, and ck = 0.

Idch is not well-controlled, but the accuracy of the oscillation

(switching) frequency fs is well-controlled because it is dominated
by the accurate Ich.

Ki 16
 Current Regulator / Voltage Mirror

The error amplifier for generating the charging current can be

realized using a differential amplifier stage.
Vdd

Vref
Ich =
RT

Vref
Vref
RT
Ib RT

Ki 17
 Comparators

One-stage comparator Two-stage comparator

Vdd Vdd

Vb Vb

V− V+ Vo V−2 V− V+ Vo

V+
V−1 Vo
V−2

Low gain Higher gain

Equal rise and fall times Rise time longer than fall time
Add inverters to increase gain A second V- input may be
added to both comparators
Ki 18
 2-Stage Simple Operational Amplifier

The op amp of the PWM compensator should be ground-sensing

(common mode voltage close to ground).
Vdd

M5
Mb M7

Rb V− M1 M2 V+
Vo

Ib Rz
Cc

R b2 M3 M4 M6 CL

supply 2-stage op amp

independent bias

Ki 19
 Frequency Response of Op Amp

The op amp gain is Aop(s) (but the EA (compensator) gain is A(s)):

A dc (1 + s / z1 )
A op (s) = |A| A dc p1
(1 + s / p1 )(1 + s / p2 )

where
A dc = gm1 (rds2 || rds 4 ) × gm6 (rds6 || rds7 ) ωt
1 ω
z1 = p2
C c (R z − 1 / gm6 ) z1
1
p1 =
C c gm1 (rds2 || rds 4 )(rds6 || rds7 ) /A
g ω
p2 = m6
CL
g −90 o
ωt = m1 φm
Cc o
−180
choose p2 = 3ωt for φm = 70 o
Ki 20
 Current Mirror Amplifier

The simple 2-stage op-amp can be modified to be a 1-stage current

mirror amplifier.

Vdd A dc
A op (s) =
M0
(1 + s / p1 )
Vbp
M7 M8
A dc = gm1 (rds6 || rds8 )
V− M1 M2 V+ Vo
1
p1 =
CL (rds6 || rds8 )
CL
M5 M3 M4 M6
Rb gm1
ωt =
4 :1 CL
self-biased
Widlar current source

Ki 21
 Folded Cascode Op Amp (1)

To achieve high DC gain, a folded cascode op amp could be used

(assume μn=2μp).
Vdd 8 :2 :8 20μA 10μA 10μA
Mb6 Vb4
Mb4 M10
R b2 M0 M9
Vb3
Mb3 M8
M7
Vo
V− M1 M2 V+
Ro
Vb2 M5 M6
Ib Mb2
Rb
Mb1 Mb5 CL
Vb1 M3 M4
Mb0
1 :4 :4 :1 20μA 20μA
supply folded cascode
independent bias gain stage
Ki 22
 Folded Cascode Op Amp (2)

The gain function of the folded cascode op amp is:

A dc
A op (s) =
(1 + s / p1 )
where
A dc = gm1R o
1
p1 =
CL R o
with
R o = [gm6rds6 (rds 4 || rds2 )]|| [gm8rds8rds10 ]
and
gm1
ωt =
CL

Ki 23
 2-Stage Folded Cascode Op Amp (1)

To achieve high DC gain, a folded cascode op amp followed by an

inverting stage could be used (assume μn=2μp).
Vdd 8 :2 :8 20μA 10μA 10μA 20μA
Mb6 Vb4
Mb4 M12
R b2 M0 M9 M10
Vb3
Mb3 M8
M7

V− M1 M2 V+ Rz C Vo
c

R o1
Vb2 M5 M6
Ib Mb2
Rb
Mb1 Mb5 CL
Vb1 M3 M4
M11
Mb0
1 :4 :4 :1 20μA 20μA 20μA
supply folded cascode inverting
independent bias gain stage gain stage
Ki 24
 2-Stage Folded Cascode Op Amp (2)

The gain function of the folded cascode op amp is:

A dc (1 + s / z1 )
A op (s) =
(1 + s / p1 )(1 + s / p2 )
where
A dc = gm1R o1 × gm11 (rds11 || rds12 )
R o1 = [gm6rds6 (rds 4 || rds2 )]|| [gm8rds8rds10 ]
1
z1 =
C c (R z − 1 / gm11 )
1
p1 =
C c gm1R o1 (rds11 || rds12 )
g
p2 = m11
CL
g
ωt = m1
Cc
Ki 25
 V-to-I Conversion for Compensation Ramp

To add a compensation ramp to the inductor current, a V-to-I (V2I)

converter could be used. Two versions are shown below.

Vdd Vdd

Vin
Vin
R
R V1
(if Vgsn =
Vin | Vgsp |)
Vin V2
R
Ib R Vin R

Ki 26
 Power Transistor Design

Switch voltage of an ideal switch is 0V when conducting

⇒ MOS switch should have small Vds when conducting
⇒ MOS switch in triode (linear) region when conducting
⇒ For an NMOS power switch MN,

⎛W⎞ ⎡ 1 ⎤
Id = μnC ox ⎜ ⎟ ⎢(Vdd − Vtn )Vds − Vds 2 ⎥
⎝ L ⎠N ⎣ 2 ⎦
Vds 1
RN = =
Id μnC ox (W / L)N (Vdd − Vtn )

1% rule: conduction loss of RN is 1% of the load RL

If RL is 10Ω, 1% is 100mΩ. If duty ratio is 0.5, then MN conducts

half of the time, and RN can be 200mΩ.

Ki 27
 Buffer Design

To drive a power switch effectively starting from control logic

blocks, buffers (digital inverters) have to be used.

Minimum delay gives a ratio of e (=2.718), but too many stages

are then needed:
- large transistors give large switching loss;
- large buffers give large shoot-through (short-circuit) loss;
- last stage buffer should have a ratio of 25 to 40.

1 : 4 : 40 : 600 : 30000

Ki 28
 Eliminate Short-Circuit Loss (1)

For a large inverter, insert a starving resistor Rstarve to limit shoot-

through (short-circuit) current, but the most important observation
is at Vp and Vn. For input changes from ‘0’ to ‘1’, Vn drops
immediately, but Vp drops with a delay due to Rstarve.

Vp Vp
R starve
R starve
Vn Vn

Ki 29
 Eliminate Short-Circuit Loss (2)

Short circuit loss of the last stage (largest) buffer could be eliminated
if driven by a buffer with starving resistor.

(W / L)n
=4

40 : 600 40 : 600

Starving resistor can be replaced by transistors operating in the linear

region. A rule of the thumb design is 1/10 of the inverter transistors.

Ki 30
 Power PMOS or Power NMOS?

The PMOS switch may be replaced by an NMOS switch driven from

an on-chip step-up charge pump [Sze 08].
Vdd = 1.2V 3.8V
MPS 5X MNS
Vref + charge
⇒ pump level
− VNS
VPS shifter

Example: Vdd = 1.2V, and needs a 50mΩ switch (RPS = RNS = 50mΩ)

P-switch: (W/L)PS = 1/(μpCox×(Vdd-|Vtp|)×RPS)

= 500,000μ/0.25μ

N-switch: (W/L)NS = 1/(μnCox×(3.8-Vtn)×RNS)

= 33,300μ/0.25μ

Charge pump (1pF caps) + auxiliary circuits is about the size of MNS
⇒ P scheme : N scheme = 7.5 : 1
Ki 31
 Simple P-Current Sensor

On-chip current sensing can be achieved by a small sensing transistor

Mps that is forced to have the same Vd, Vg and Vs as the power
transistor MP using a matched current source [Ki 98].

PVdd 1mA 1A
1 : 1000
MPs
20 / 2
MP
Q
20000 / 2
Q MSW1 iA

0.999mA MSW2 Vo
L
Ms1 Ms2
MN RL
iAR f Ms5 C
1μA
to N
PWM PGnd
CMP Ms 4
Rf Ms3 Msb

AGnd
Ki 32
 Symmetrical Matching of CMOS Transistors

When a pair of transistors M1 and M2 of the same type are matched,

their W/L ratios are the same, i.e., (W/L)1 = (W/L)2, and in most
cases, W1=W2 and L1=L2. However, their drain currents may not be
the same due to channel length modulation.

If in addition to having the same W/L ratio, M1 and M2 are forced

(by an additional circuit) to have essentially the same drain, gate
and source voltages, then they are called symmetrically matched
(SM) [Lam 04b, Lam 07].

The simple current sensor uses the 4T cell to force Mps to be

symmetrically matched with MP. However, the accuracy is limited by
the 4T cell that itself is not symmetrically matched.

Ki 33
 Symmetrically Matched N-Current Sensor

Replace 4T cell by 8T cell with internal cross-biasing such that paired

transistors (M1, M2), (M3, M4), (M5, M6), (M7, M8) are symmetrically
matched, forcing Vy=Vx. Start-up circuit is needed [Lam04b, Lam 07].
M : 1 : 1 : M
Vdd
M4
M9 M6 M3 M8

Isense V4 V2 V3

M5 M1 M2 M7
V1
Vx Vy
iA

MN
Q MNs

1000 : 1
Ki 34
 Concept of Active Diode

The lossy passive diode may be replaced by an active diode, and

eliminate the need to control two switches for synchronous
rectification:
MP
Vx (A) (K)
Vo
L
(active diode)
Vdd MN RL
C

An active diode is simply a power transistor controlled by a (current)

comparator:
A K
CMP

CMP
A K
Ki 35
 Active Diode Implementation (1)

One implementation of the active diode is discussed in [Man 06],

and is used in a DCM boost converter. The capacitor C is added to
improve transient response.

VL (A) VH (K)

VH
C

Ki 36
 Active Diode Implementation (2)

Another active diode is used in a regulated charge pump [Lam 06].

VL VH VL VH
VH
VH

Vb

Active diodes can be used as maximum voltage selector for biasing

substrates of PMOS power switches in a multiple-output converter.
Vmax
V1 V2

Ki 37
 Power Management Peripherals

For a low-voltage system, e.g., Vdd=5V, there is usually only one

trimmed voltage reference.

For a system with Vdd = 15V, there are usually two voltage
references, one trimmed for accuracy, and a second one untrimmed
and could work at very low voltage for start-up, UVLO (under voltage
lockout) and OVP (over voltage protection).

15V 5V

VBG(untrim) VREF
+
_
untrim UVLO OVP trimmed functional
BGR BGR blocks

linear regulator

Ki 38
 UVLO Comparator

Vdd
Vbp
VH
Vin

VL

VoH
VoL

Ki 39
 Soft Start Circuit

Consider the buck converter. When Vo=0, EA drives Va to Vdd, and

D=1. SW1 is always on, causing large in-rush current. The soft start
circuit uses a very tiny current to charge a large CSS, such that VSS
rises very slowly, limiting the duty ratio.

Vdd
ramp R1
Va CMP R Q M1 M2
soft
start VSS
ck S Q

VSS

M2 is in sub-threshold region, sourcing Vbn CSS

a current in the range of nA.

Ki 40
 I/O Connections

Different types of ESD (electrostatic discharge) diodes.

Vdd

I/O I/O

GND

Schottky large diode-

diodes diodes connected
transistors

Ki 41
 Continual Fraction Expansion

Consider the continual fraction expansion of π:

π = 3.14159265359
1
≈3+
7.0625133
1
≈3+
7 + (1 / 15.99659)
1
≈3+
7 + (1 / [15 + (1 / 1.0034)])
Now,
1 22
3+ = = 3.14285714286
7 7
1 333
3+ = = 3.14150943396
7 + (1 / 15) 106
1 355
3+ = = 3.14159292035
7 + (1 / 16) 113
Ki 42
 Resistor String using Unit Resistors

In an analog circuit array (compared with a digital gate array), all

components are fixed except for the metal layers for
interconnection. Resistors are thus formed using unit resistors.

For example, if the unit resistor is 9.5kΩ and R1=10.8kΩ is needed.

Use continual fraction expansion:

R1 10.8
= = 1.136842
R unit 9.5
1
=1+
7.3077
1
=1+
7 + (1 / 3.25)
1
=1+
7 + (1 /[3 + (1 / 4)])

Ki 43
 Parallel/Series Connection of Resistors

For Runit = 9.5kΩ

[1+(1/7)]×Runit = 1.14286×Runit = 10.86kΩ 8 Runit
[1+(1/[7+(1/3)])]×Runit = 1.13636×Runit = 10.8kΩ 11 Runit
[1+(1/[7+(1/[3+(1/4)])])]×Runit = 1.13684×Runit = 10.8kΩ 15 Runit

Use 11 Runit (instead of 15 Runit) is accurate enough and save

components. The structure is:

R unit
R1 1
=1+ ⇒
R unit 1 R1
7+
3

Ki 44
 IC References: Books/Theses

Books / Book Chapters / Thesis:

[Gilbert 96] B. Gilbert, "Monolithic voltage and current references: Theme and Variations," in
[Huijsing 96], 1996.
[Gray 01] P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated
Circuits, 4th Ed., Wiley, 2001.
[Huijsing 96] J. H. Huijsing, R. van de Plassche and W. Sansen, Analog Circuit Design, Kulwer,
1996.
[Johns 97] D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.
[Lam 08] Y. H. Lam, Differential Common-Gate Techniques for High Performance Power
Management Integrated Circuits, PhD Thesis, HKUST, Jan. 14, 2008.
[Meijer 96] G. Meijer, "Concepts for bandgap references and voltage measurement systems," in
[Huijsing 96], 1996.
[Razavi 01] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.
[R-Mora 02] G. A. Rincon-Mora, Voltage References, IEEE Press, 2002.
[Sansen 06] W. Sansen, Analog Design Essentials, Springer, 2006.
[Sze 81] S. M. Sze, Physics of Semiconductor Devices, 2nd Ed., Wiley, 1981.

Ki 45
 IC References: Current Sources

Current Sources and Circuits:

[Frederiksen 72] T. M. Frederiksen, "Constant current source," US Patent 3,659,121, Apr. 25,
1972.
[Lam 07] Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and
applications therefor," US Patent 7,215,187, May 8, 2007.
[Lo 09] A. Lo, W. H. Ki and W. H. Mow, “A 20MHz switched-current sample-and-hold
circuit for current mode analog iterative decoders,” IEEE Int’l Symp. on IC, pp.
283-286, 2009.
[Kessel 71] T. van Kessel and R. van der Plaasche, "Integrated linear basic circuits," Philips
Tech. Rev., pp.1-12, 1971.
[Smith 68] K. C. Smith and A. Sedra, "The current conveyor: a new circuit building block,"
Proc. of the IEEE., pp.1368-1369, 1968.
[Widlar 65] R. J. Widlar, "Some circuit design techniques for linear integrated circuits," IEEE
Trans. Circ. Theory, pp.586-590, 1965.

Ki 46
 IC References: Current Sensors and Active Diodes

On-Chip Current Sensors:

[Ki 98] W. H. Ki, "Current sensing technique using MOS transistors scaling with matched
bipolar current sources," U.S. Patent 5,757,174, May 26, 1998.
[Lam 04a] H. Lam, W. H. Ki and D. Ma, "Loop gain analysis and development of high-speed
high-accuracy current sensors for switching converters," IEEE Int'l. Symp. on Circ.
& Sys., pp.V.828–V.831, May 2004.
[Lam 04b] H. Lam, W. H. Ki, C. Y. Tsui and D. Ma, "Integrated 0.9V charge-control switching
converter with self-biased current sensor," IEEE Int'l Midwest Symp. on Circ. & Sys.,
pp.II.305–II.308, July 2004.
[Lam 07] Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and
applications therefor," US Patent 7,215,187, May 8, 2007.

Active Diodes:
[Lam 06] Y. H. Lam, W. H. Ki and C. Y. Tsui, "An integrated 1.8V to 3.3V regulated voltage
doubler using active diodes and dual-loop voltage follower for switch-capacitive
load," VLSI Symp. on Tech. & Circ., pp.104-105, June 2006.
[Man 06] T. Y. Man, P. Mok and M. Chan, "A CMOS-control rectifier for discontinuous-
conduction mode switching DC-DC converters," IEEE Int'l Solid-State Circ. Conf.,
pp.358-359, Jan. 2006.
Ki 47
 Blank

Ki 48