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11/16/22, 3:48 PM OneNote

Second order effects 


27 November 2021  09:17 

What are second order effects 


Second order effects are the consequences of MOSFET scaling. 
 
These effects are due to MOSFET parameters, concentration of doping, oxide thickness
variation, channel length variation, high electric field intensity inside the device channel, oxide
breakdown, avalanche breakdown of the PN regions inside the MOS transistors comes under
second order effects. 
 
Which are the second order effects 
1. Subthreshold leakage current 
2. Body effect 
3. Channel length modulation 
4. Drain induced barrier lowering (DIBL) 
5. Hot carrier injection 
6. Impact ionization 
7. Avalanche breakdown 
8. Velocity saturation (mobility degradation) 
9. Surface scattering 
10. Punch through 
11. Gate induced drain leakage 
 
 
#1 - Subthreshold leakage current 
• The current between source and drain of a mosfet, when the transistor is in the weak
inversion region, i.e. for gate to source voltage is below the threshold voltage it is called
subthreshold leakage current. 
• In lower channel devices, due to space between source and drain is less, there is more
drift current (Drift current is the electric current caused by particles getting pulled by an
electric field) flows under the gate. Gradually this subthreshold current will increase. 
• And it is inversely proportional to the channel length and directly proportional to the
drain voltage and temperature. Increase in temperature causes increase in charge carriers
and  they are more energised as well which increases carriers collision hence drift
current. 
 

 
 
#2 - Body effect 
• Body effect refers to the change in the transistor threshold voltage (VT) resulting from a
voltage difference between the transistor source and body. Because, the voltage
difference between the source and body affects the VT, the body can be treated as a
second gate that helps determine how the transistor turns ON and OFF. 
• Body bias involves connecting the transistor bodies to a bias network in the circuit/layout
rather than to power or ground. The body bias can be supplied from an external (off-chip)
source or an internal (on-chip) source. 
 

 
 
#3 - Channel length modulation 

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11/16/22, 3:48 PM OneNote
• In mosfet, at pinch of region, drain current depends on more electrical field and also
depends on the depletion region where it opposes the drain current.  
• Since depletion region increases,  we should have a constant current if Vds increases.  
• But if we come to lower channel devices, where electric field due to drain voltage
dominates the depletion width opposition current, so more drain current flows. This we
called channel length modulation. 
• The channel length modulation factor is lambda and it is inversely proportional to channel
length. 
 

 
#4 - Drain induced barrier lowering (DIBL) 
• When drain voltage is more than bulk potential, due to its reverse biased depletion
region, it occupies some part of space in channel. So we need little less gate voltage
required to invert the remaining channel to turn mosfet ON. So Vt is decreased. 
• This effect can be reduced by changing doping concentration of either bulk or drain. And
by inserting a low doped n material before the drain. 
 

 
 
#5 - Hot carrier injection 
• This effect occurs when there is more drain voltage in short channel devices. More drain
voltage in short channel generates higher electric field so that it attracts more electrons
from the source and those electrons reach its maximum velocity and it gets more kinetic
energy(energy which a body possesses by virtue of being in motion). Electrons which get
more kinetic energy are called hot electrons.  
• These hot electrons collide at the edge of the drain or gate and reflect back and damage
thin gate oxide near the drain region. If gate oxide damages then current flows from gate
to substrate directly. This is called hot carrier injection. 
• This effect can be avoided by using thicker gate oxide or using high-k material(material
which has better dielectric constant K than poly gate) as gate. And inserting low doped
material before the drain.  
 

 
 
#6 - Impact ionization 
• This effect is related to hot carrier effect. The hot carrier electrons which are reflected
from the drain also breaks the covalent bonds in depletion region. If a covalent bond is
broken then an electron and a hole is generated. If more covalent bonds break then more
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11/16/22, 3:48 PM OneNote
free electrons will be collected by the drain. Therefore, extra unwanted Ids current flows
from source to drain through substrate. This is called impact ionization effect.  
• If we are able to control or decrease the hot carrier effect, ion impact ionization effect
also reduces. 
 
  

 
#7 - Avalanche breakdown 
• As the electric field in the channel is increased, avalanche breakdown occurs in the
channel at the drain. This avalanche breakdown increases the current as in a PN junction
diode. There is parasitic bipolar action taking place. Holes generated from the avalanche
breakdown move from drain to source underneath the inversion layer. This hole current
forward biases the source-bulk PN diodes so that now also electrons are injected as
minority carriers into the P-type substrate underneath the inversion layer. These electron-
hole pairs multiply through avalanche breakdown. The positive feedback between and
parasitic bipolar action results in breakdown at lower drain voltages. 
• If we control hot carrier effect the avalanche effect can be avoided. 
 
 
#8 - Velocity saturation and mobility degradation 
• This effect mainly occurs due to disproportionate scaling down of supply voltage
compared to device length and thin oxide of the gate. If supply voltage remains
significantly higher then this effect may be witnessed. 
• The electron velocity is related to the electric field through the mobility. For higher field
velocity doesn't increase with electric field, we have a degradation of mobility because
scattering by vertical field. This leads to earlier saturation of current i.e. before Vgs-Vth.
Nothing but reduction in drain current. 
• The velocity saturation reduces the transconductance (the ratio of the change in current
at the output terminal to the change in the voltage at the input terminal of an active
device) of short channel devices in the saturation condition. 
• By using high-k materials as gate this can be avoided. 
 

 
 
#9 - Surface scattering 
• When carriers travel along the channel, they are attracted to the surface by electric field
created by the gate voltage.  
• As a result, they keep crashing and bouncing against the surface, during their travel,
following a zig-zag path. This effectively reduces the mobility of the carriers. 
• This change in carrier mobility impacts the current-voltage relationship of the transistor. 
 

 
 

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#10 - Punch through 
• If Vds goes on increasing, due to reverse biased junction at drain, it will have a significant
widths of depletion region. 
• Since gap between the drain and source is very less, the depletion region of drain will
touch/overlap with the source depletion region. 
• If this happens once, the drain current between source and drain can't be controlled by
the gate. 
• By changing the doping concetration of drain or bulk punch through can be avoided. 
 

 
 
#11 - Gate induced drain leakage 
• This issues occur only when gate voltage is less than 0 (for NMOS) and more drain
voltage. 
• Basically there is reverse saturation current flows between the drain and bulk(P) and it is
very minor. 
• When -ve gate voltage is applied(assume due to noise), it attracts the holes (due to
accumulation) and forms the P channel (P+) between the source and drain. In this case,
the thinner depletion region will form between the generated P+ region and drain (N+).
So compare to PN+ reverse saturation current, P+N+ reverse saturation current is more
and it is considerable leakage current. This leakage is called as Gate Induced Drain
Leakage. 
 
 
Conclusion 
The second order effects complicates device operation and degrade device performance, these
effects can be eliminated or minimized in SOI and FINFET technology by its different
construction. 

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