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CPU Core the maximum resolution of -RGMII/MII
ARM1176 1280x1024@30fps, 1600x1200@20fps, and -Supporting 10 or 100 Mbit/s full-duplex and
I-cache 16 KB, D-cache 16 KB 2048x1536@10fps half-duplex modes
I-TCM 2 KB Output: -Supporting 1000 Mbit/s full-duplex mode
Built-in MMU, supporting multiple open -Multiple video output interfaces Supporting the RTC
operating systems such as VxWorks, Linux, -VGA/YPbPr x 1+CVBS x 2 External Memory Interfaces
WinCE, and PalmOS -VGA x 2 Two DDR2 SDRAM interfaces
Up to 600 MHz operating frequency -Supporting HD output with the maximum -32- or 16-bit data width
Video Encoding/Decoding resolution of 1920x1080p@30fps, -Each interface supports up to 256 MB
H.264 main profile encoding/decoding 1920x1080i@60fps NOR flash interface
H.264 baseline profile encoding/decoding -Supporting BT.656, BT.1120, and LCD digital -8-bit data width
JPEG/MJPEG baseline encoding/decoding outputs -Two CSs. Each supports up to 32 MB
Video Encoding/Decoding Performance Audio Interfaces NAND flash interface
Overall performance of real-time H.264 Three IIS interfaces. Each supports up to -8-bit data width
encoding/decoding: 8-channel D1 16-channel 8- or 16-bit audio cascade inputs -Supporting SLC, MLC, and 1-, 4-, and 8-bit
Optimal performance for H.264 Supporting multiple sampling frequencies such ECC
encoding/decoding: 1280x1024@30fps as 8 kHz, 16 kHz, 32 kHz, 44.1 kHz, and 48 -Supporting up to 8 GB capacity
The following are supported in H.264 kHz SDK
encoding and decoding: Supporting multiple sampling precisions such Providing the SDK based on Linux 2.6.24
-120fps D1 encoding + 120fps CIF encoding + as 8 bits, 16 bits, and 32 bits Providing high-performance H.264 PC
120fps D1 decoding@NTSC Peripheral Interfaces decoding library
-100fps D1 encoding + 100fps CIF encoding + PCI interface Physical Specifications
100fps D1 decoding@PAL -Complying with the PCI V2.3 communications Power
Supporting 1.3-mega pixels@30fps to 3-mega protocol -1600 mW typical power consumption
pixels@10fps -Compatible with miniPCI -Multiple-level power saving modes
Supporting 3-mega pixels@10fps JPEG -Supporting the master/slave mode and up to Operating voltage
snapshot five devices -Core voltage: 1.0 V
Supporting the CBR/VBR bit rate control mode. Four UART interfaces, one IR interface, one IIC -IO voltage: 3.3 V. The tolerance voltage is 5 V
The bit rate ranges from 16 kbit/s to 20 Mbit/s interface, one SPI master/slave interface, and -Voltage of the DDR2 SDRAM interface: 1.8 V
Graphics Processing one GPIO interface -Operating temperature: 0–70OC
Video input de-interlace (pre-processing) SDIO 2.0 interface, supporting up to 32 GB Package
Video output de-interlace (post-processing) Two USB 2.0 Host interfaces, supporting the -768-pin FPBGA package
Anti-flicker processing for video and graphics HUB function -0.8-mm ball pitch, 27 mm x 27 mm
outputs One GMAC interface
Video and graphics scaling
OSD overlay pre-processing for four areas
Hardware graphics overlay post-processing for Ｆｕｎｃｔｉｏｎａｌ　Ｂｌｏｃｋ　Ｄｉａｇｒａｍ
five layers (background layer, video layer,
graphics layer 1, graphics layer 2, and cursor Ethernet 10/100/1000 M bit/s PCI
The Hi3520 is a high-performance
A R M P rocessor communications media processor
layer) of videos PHY GMAC
Java A cc/V F P /M M U that is based on the ARM11
Video mask up to four areas B T .1120 S D IO processor core and the video
Video B T 656 hardware acceleration engine. The
Motion detection Decoder V ideo In X 4 G raphics E ngine V ideo C odec
frequency of the ARM11 processor is
(A/D) IIC up to 600 MHz, which meets the
Audio Encoding/Decoding D einerlace/S caler/O S D H .264/M JP E G
requirements of customers in
Encoding and decoding audios from multiple CMOS
S S P /S P I
increasing software applications. The
dual double data-rate (DDR)
Sensor
channels and protocols through dedicated architecture provides a wider
bandwidth, thus implementing a
processors TV CVBS V ideo O ut C V B S 0 S hared m em ory sw itch / D M A G P IO
more powerful capability for
Security Engine processing data. The Hi3520 supports
CVBS JT A G H.264 and MJPEG multi-protocol
Implementing various encryption and TV V ideo O ut C V B S 1 P re/P ost processing engine encoding/decoding, and the
encoding/decoding performance is
decryption algorithms such as AES, DES, and U A R T ×4 up to 240fps D1@NTSC. Therefore,
RGB
3DES through the hardware VGA V ideo O ut V G A Interrupt C ontrol T im ers/W D T the optimal multi-channel
encoding/decoding digital video
Supporting the digital watermark technology IR
B T .1120 recorder (DVR) solution can be
Video B T 656 S ecurity RTC provided. In addition, the Hi3520 has
Video Interfaces Encoder V ideo O ut U S B 2.0 ×2 various video input or output
(D/A) A E S /D E S /3D E S R eal-T im e C lock
Input: interfaces such as the composite
video broadcast signal (CVBS),
-Supporting 4-channel BT656/601 interfaces, Audio IIS × 3 N A N D F lash N O R F lash DDR2 SDRAM X 2 high-definition (HD) video graphics
Codec C ontroller C ontroller C ontroller array (VGA), and BT.1120 interfaces.
8 bits, 27/54/108 MHz With the maximum resolution of
-Supporting 2-channel standard SMPTE296M Hi3520 1920x1080p@30Hz, the Hi3520
brings customers an excellent video
and BT.1120 HD timings experience with better image quality.
NAND Flash Nor Flash DDR2 SDRAM
-Supporting the digital camera interface with
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SATA SATA SATA
…
HDD HDD HDD

TV VGA TV
or
P C I2S A T A

CVBS V G A /C V B S PCI
F lash

DDR2
Hi3520
DDR2 U S B 2.0 H ost

GMAC 16-channels CIF DVR with

PHY GMAC V I0
V I0 VV
I1I1 VVI2I2 VVI3I3
a single Hi3520
R outer − 1280 x 1024 VGA output
16 C h. A /V D ec. − 16-channels CIF video recording
− 16-channels QCIF network transfer
IP C am era
LA N
− 16-channels CIF decoding playback

SATA SATA SATA

…
HDD HDD HDD

P C I2S A T A
TV VGA or TV

CVBS V G A /C V B S PCI PCI

F lash （H ost） （T arget）

DDR2 Hi3520 Hi3520

DDR2 U S B 2.0 H ost

8-channels D1 DVR with
PHY GMAC
GMAC VVI0I2 V I1 V I3 V I2 V I3 two Hi3520s
R outer − 1280 x 1024 VGA output
4 C h. A /V D ec. 4 C h. A /V D ec.
− 8-channels D1 video recording
− 8-channels CIF network transfer
IP C am era
…
LA N
… … … − 8-channels D1 decoding playback

SATA SATA SATA

…
HDD HDD HDD

PCI2SATA
TV VGA or TV

CVBS VGA/CVBS PCI PCI PCI PCI

Flash （ Host） （Target） （Target） （Target）

DDR2 Hi3520 Hi3520 Hi3520 Hi3520

(Master) (Slave) (Slave) (Slave)
USB2.0
DDR2
Host 4-channels 720P/1080P DVR
PHY GMAC VI0
VI0 VI1 VI0 VI0 VI0
− 1280 x 1024 VGA output
− 4-channels 720P/1080P video
Router
SDI SDI SDI SDI
recording
− 4-channels CIF network transfer
IP
Camera − 4-channels 720P/1080P decoding
LA
N playback

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THIS DOCUMENT IS FOR INFORMATION PURPOSE ONLY,
AND DOSE NOT CONSTITUTE ANY KIND OF WARRANTIES.