CS 322

Computer Organization

Fall 2021
Chapter 5
BASIC COMPUTER ORGANIZATION
AND DESIGN
 s0 s1 s2
Back to our basic computer Bus
Memory Unit
4096x16
7
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic AC 4
LD INR CLR

INPR

IR 5
LD INR CLR
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus 3
Basic Computer Instructions
◼ Basic Computer has three types of instructions:

Memory-Reference Instructions

Register-Reference Instructions

Input-Output Instructions

4
Basic Computer Instructions
◼ In Basic Computer,

Memory-Reference Instructions

 Divided into two parts:

◼ An opcode (Operation Code) that specifies the operation for that instruction
◼ An address that specifies locations in memory to use for that operation
 Memory contains 4096 (= 212) words
◼ We needs 12 bits to specify which memory address this
instruction will use
 Bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing)

15 14 12 11 0
Addressing
mode I Opcode Address
5
Basic Computer Instructions
◼ In Basic Computer,

Memory-Reference Instructions

 Divided into two parts:

◼ An opcode (Operation Code) that specifies the operation for that instruction
◼ An address that specifies locations in memory to use for that operation
 Memory contains 4096 (= 212) words
◼ We needs 12 bits to specify which memory address this
instruction will use
 Bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing)

15 14 12 11 0
Addressing
mode I Opcode Address
6
Basic Computer Instructions
◼ In Basic Computer,

Memory-Reference Instructions

 Divided into two parts:

◼ An opcode (Operation Code) that specifies the operation for that instruction
◼ An address that specifies locations in memory to use for that operation
 Memory contains 4096 (= 212) words
◼ We needs 12 bits to specify which memory address this
instruction will use
 Bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing)
 Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode
15 14 12 11 0
Addressing
mode I Opcode Address
7
Basic Computer Instructions

Op-code
(3 bits)
000
001
010
011 Memory reference instruction
100
101
110
111 Register reference
instruction OR I/O instruction
Based on I (bit no. 15)
15 14 12 11 0
Addressing
mode I Opcode Address
8
Basic Computer Instructions
Op-code
(3 bits)
Memory-Reference Instructions (OP-code = 000 ~ 110) 000
15 14 12 11 0
001
I Opcode Address 010
011
Register-Reference Instructions (OP-code = 111, I = 0) 100
15
0 1 1 1
12 11
Register operation
0
101
110
Input-Output Instructions (OP-code =111, I = 1)
111
15 12 11 0
1 1 1 1 I/O operation

9
Basic Computer Instructions
Op-code
(3 bits)
Memory-Reference Instructions (OP-code = 000 ~ 110) 000
15 14 12 11 0
001
I Opcode Address 010
Op-code011
Register-Reference Instructions (OP-code = I=0 111,(Hex)
I = 0) I=1(Hex)
100
0000(0) 1000(8)
15
0 1 1 1
12 11
Register operation
0
0001(1) 101
1001(9)
0010(2) 110
1010(A)
0011(3) 1011(B)
111
Input-Output Instructions (OP-code =111, I = 1)
0100(4) 1100(C)
15 12 11 0 0101(5) 1101(D)
1 1 1 1 I/O operation
0110(6) 1110(E)

0111(7) 1111(F)

10
 Instructions

Basic Computer Instructions

Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC Memory-
LDA
STA
2xxx Axxx
3xxx Bxxx
Load AC from memory
Store content of AC into memory
reference
BUN 4xxx Cxxx Branch unconditionally instruction
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero (OP-code = 000 ~ 110)
I=0: 0xxx ~ 6xxx,
CLA 7800 Clear AC I=1: 8xxx ~ Exxx
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E Register-
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E reference
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive instruction
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero (OP-code = 111, I = 0)
SZE 7002 Skip next instr. if E is zero 7xxx
HLT 7001 Halt computer

INP F800 Input character to AC Input-

OUT F400 Output character from AC
SKI F200 Skip on input flag output
SKO F100 Skip on output flag instruction
ION F080 Interrupt on
IOF F040 Interrupt off (OP-code =111, I = 1)
Fxxx
11
Machine Instruction Cycle Memory Unit
s0 s1 s2
Bus

7
In Basic Computer 4096x16
Address
WRITE READ
AR 1

1. Fetch
an instruction from LD INR CLR
PC 2
memory = IRM[PC] LD INR CLR
➔AR  PC DR 3
LD INR CLR
(S0 S1 S2= 0 1 0) Adder E
AC 4
➔IR  M [AR], PC  PC + 1 & Logic
LD INR CLR

(S0 S1 S2= 1 1 1) INPR

IR 5
2. Decode the instruction LD
➔D0,…,D7  Decode IR(12-14), TR 6

AR  IR(0-11), I  IR(15)
LD INR CLR
OUTR
Clock
3. Execute the instruction LD
16-bit common bus
4.After an instruction is executed,
the cycle starts again at step 1,
for the next instruction
Control unit (CU) translates machine instructions to control signals
the microoperations that implement them
12
Instruction Set Completeness
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.
• Instruction Types In Basic Computer
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

13
Control Unit
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15

T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
14
Timing Signals
▪ Generated by 4-bit sequence counter and 416 decoder
▪ The SC can be incremented or cleared.

Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC
15
Control Unit
Start
SC  0
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0
16
Control Unit
Start
SC  0
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0
17
Control Unit
Start
SC  0
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)
• Fetch:
(Register or I/O) = 1 = 0 (Memory-reference)
T0: AR  PC D7 (S0S1S2=010)
(I/O) 1  M [AR],
T1:= IR PC  PC + 1 (indirect)
= 0 (register) (S0S1S2==111)
1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0 18
Control Unit
Start
SC  0
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0
19
Control Unit
Start
SC  0
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0
20
Control Unit
Start
SC  0
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0
21
Control Unit
Start
SC  0
T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0
22
Determine The Type Of Instruction
Start
SC  0

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

23
Register Reference Instructions
Register Reference Instructions are identified when:
- D7 = 1, I = 0, execution starts with timing signal T3
- r = D7 IT3
- Register Ref. Instr. is specified in B0 ~ B11 of IR s 0 s1 s2
- Bi = IR(i) , i=0,1,2,...,11 Bus
Memory Unit 7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR
E
ALU AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
24
16-bit common bus
Register Reference Instructions
Register Reference Instructions are identified when:
- D7 = 1, I = 0, execution starts with timing signal T3
- r = D7 IT3
- Register Ref. Instr. is specified in B0 ~ B11 of IR
- Bi = IR(i) , i=0,1,2,...,11

25
Register Reference Instructions
Register Reference Instructions are identified when:
- D7 = 1, I = 0, execution starts with timing signal T3
- r = D7 IT3
- Register Ref. Instr. is specified in B0 ~ B11 of IR
- Bi = IR(i) , i=0,1,2,...,11

r : SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9 : AC  AC’
CME rB8 : E  E’
CIR rB7 : AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6 : AC  shl AC, AC(0)  E, E  AC(15)
INC rB5 : AC  AC + 1
SPA rB4 : if (AC(15) = 0) then (PC  PC+1)
SNA rB3 : if (AC(15) = 1) then (PC  PC+1)
SZA rB2 : if (AC = 0) then (PC  PC+1)
SZE rB1 : if (E = 0) then (PC  PC+1)
HLT rB0 : S  0 (S is a start-stop flip-flop)
26
Memory Reference Instructions
Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
s0 s1 s2
Bus
Memory Unit
4096x16
7 - The effective address of the
Address
WRITE READ
1
instruction is in AR and was placed
AR
LD INR CLR there during
PC 2 timing signal T2 when I = 0, or
LD INR CLR
DR 3 during timing signal T3 when I = 1
LD INR CLR - Memory cycle is assumed to be short
ALU
E
AC 4 enough to complete in a CPU cycle
LD INR CLR - The execution of MR instruction
INPR
5
starts with T4
IR
LD
TR 6
LD INR CLR
OUTR
LD
Clock 27
16-bit common bus
 Memory Reference Instructions
Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
28
D4T4: PC  AR, SC  0
 Memory Reference Instructions
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
29
Flowchart For Memory Ref. Instructions
Memory-reference instruction
AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
30
EX 13.7
How many times does the processor need to refer to
memory when it fetches and executes an indirect-address-
mode instruction if the instruction is:
(a) a computation requiring a single operand;
 3 times: fetch instruction; fetch operand reference; fetch
operand.
(b) a branch?
 2 times: fetch instruction; fetch operand reference and load into
PC.
32
 CONTROL OF REGISTERS AND MEMORY
EX: Address Register AR
Scan all of the register
transfer statements that
change the content of AR:

R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4

33
 CONTROL OF REGISTERS AND MEMORY
EX: Address Register AR
Scan all of the register
transfer statements that
change the content of AR:

R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0 From bus
12
AR
12
To bus
INR(AR) = D5T4 D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D5
T4
34
 CONTROL OF COMMON BUS
T4
x1
D4 x2 S2
Multiplexer
T5 x3
Encoder S1 bus select
x4
D5 x5 inputs
x6 S0
x7

selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

For AR D4T4: PC  AR
D5T5: PC  AR

x1 = D4T4 + D5T5
35
 DESIGN OF ACCUMULATOR LOGIC
Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC

8 circuit To bus
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 : AC  0 Clear
rB5 : AC  AC + 1 Increment
36
 CONTROL OF AC REGISTER

Gate structures for controlling

the LD, INR, and CLR of AC

From Adder 16 16 To bus

and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR
D2 DR
T5
p INPR
B11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B11
37
What You Should Do
• Solve chapter 5 exercises

38
Thank you