UNIT III

DIGITAL LOGIC FAMILIES & PROGRAMMABLE LOGIC

DEVICES

Digital Logic Families

Discrete components such as diodes, transistors, and resistances were used to
create the basic logic gates outlined above. Hundreds of thousands of active
and passive components could be fabricated on a single silicon chip in the
recent past. Integrated circuits are the name for such constructed devices (ICs).
Integrated circuits can be divided into two categories: linear or analog ICs and
digital ICs. Amplifiers, operational amplifiers, audio and power amplifiers,
and other analogue ICs are among the most common. The digital ICs, on the
other hand, comprise logic gates and other components. Different technologies
are used to build logic gates in digital ICs.
The digital ICs may further be classified into following categories depending
upon their level of integration:
Small Scale Integrated Circuits (SSI): In SSI, each IC has twelve gates and
the total number of components per chip is less than 100.
Medium Scale Integrated Circuits (MSI): These integrated circuits (ICs)
have 12 to 100 gates and 100 to 1000 components.
Large Scale Integrated Circuits (LSI): Large-scale integrated circuits (ICs)
have 100 to 1000 gates per IC and 1000 to 10000 components per IC.
Very Large Scale Integrated Circuits (LSI): These integrated circuits have
between 1000 and 10,000 gates per chip, with a total number of components
ranging from 10,000 to 100,000.
Ultra Large Scale Integrated Circuits (LSI): More than 10000 gates per IC
are produced, with over 100000 total components per chip.
The logic families are divided into two categories based on the fabrication
processes employed.
Bipolar Logic Families
Uni-polar Logic Families
There are two sorts of bipolar logic families...
Saturated Logic Circuits: In which the transistors are driven into saturation.
Non-Saturated Logic: In non-saturated transistor logic circuits, the
transistors are avoided to go into saturation.
Saturated logic circuits can be further divided into the following groups:
Resistor – Transistor Logic (RTL)
Direct Coupled Transistor Logic (DCTL)
Integrated Injection Logic (IIL or I2L)
Diode – Transistor Logic (DTL)
High Threshold Logic (HTL)
Transistor – Transistor Logic (TTL)
The non-saturated logic families
are:
Schottky Transistor – Transistor Logic (STTL)
Emitter Coupled Logic (ECL)
The Uni-polar logic families contains MOS FETs, these are:
NMOS or PMOS Logic
CMOS (Complementary MOS) logic
Before going into the specifics of the above-mentioned logic families, it's
important to understand the following properties. These criteria will aid in
comparing the logic families' performances.
Fan – in: The maximum number of inputs that can be applied to a logic gate
is referred to as Fan – in. As a result, a three-input AND has three fan - in.
Fan – out: The number of gates that a logic gate can drive is known as its fan-
out. Thus, if a typical gate's fan-out is ten, it means that this gate can drive ten
other gates.
Propagation Delay Time: The time gap between applying inputs to a gate
and the appearance of the signal at the gate's output is known as the
propagation delay time of a gate.
In other words, it's the duration between a change in the gate's input state and
the resulting change in the gate's output state. This delay is a very small
quantity; it is of the order of few nano second say 20 nsec (20x10-9 sec) or 50
nsec (50x10-9 sec). The propagation delay of the gate also specifies the speed
of the logic gate.
Between 50 percent voltage levels of input and output waveforms, the delay
time is measured. An inverter's input and output waveforms are shown in
Figure 1. If tPHL is the delay time when the output goes from low state (logic
0) to high state (logic 1), and tPLH is the delay time when the output goes
from high state (logic 1) to low state (logic 0), then the propagation delay time
of the gate tpd is:

Fig 1.

Power Dissipation: It is the maximum amount of power that an IC can

dissipate. The product of the d.c. voltage provided to an IC and the current
drawn from the d.c. source is used to calculate it. A minimal power dissipation
per gate is usually desirable. The typical working power required per gate
ranges from a few microwatts to a few milliwatts. The figure of merit of the
logic family is the product of speed and power dissipation per gate. This
product's cheap value is desirable.
Operating Temperature: The operating temperature of the gate is the
temperature range in which an IC performs properly. The manufacturer has
specified it. For commercial applications, the ICs' allowable temperature range
is 0 to +700C, whereas for military applications, the range is –550C to 1250C.
Noise Margin: Due to stray electric and magnetic forces in the environment,
spurious signals called noise are occasionally created in the connecting leads
of logic circuits. As a result, the logic circuit's operation is unpredictable.
Noise immunity is a term used to describe the noise margin. The difference
between the maximum authorized low input and the maximum guaranteed low
output, as well as the lowest permitted high input and the minimum
guaranteed high output, is what it's called. The idea of noise margin is
illustrated in figure 2.

Figure 2
VOH (min) represents the minimum high voltage for logic 1 and VOL(max)
represents the highest low voltage for logic 0. The output should not go into
the forbidden range. Similarly, VIH (min) is the lowest high input voltage and
VIL (max) is the highest low input voltage, and the voltage level between VIH
(min) and VIL (max) is the uncertain range, which should not be supplied to
the logic gate's inputs.
The noise margin for the high state (VNH) and the noise margin for the low
state (VNL) are calculated as follows:
VNH = VOH (min) – VIH (min)
VNL = VOL (max) – VIL (max)
It is always preferable to have a high noise margin.
Resistor – Transistor Logic (RTL)
The most common type of logic circuit is the resistor–transistor logic. It's
called resistor transistor logic since it's made up of resistors and transistors.
The basic circuit for two - input RTL NOR gates are shown in Figure 3. This
circuit's operation can be stated as follows:
When both A and B are set to logic 0, the two transistors T1 and T2 are cutoff,
and no current flows through the transistors' collector emitter circuits. The
output will, therefore, be high (logic 1). When either of the two inputs is at
logic 1, the corresponding transistor will go into saturation and output will be
VCE, Sat of the transistor ( 2.0 ≈ V). The output is said to be logic 0 in nature.
If both inputs are at logic 0, the output will be low as both transistors will
saturate. It is concluded that it accomplishes the NOR gate's function.
Despite the fact that this is the simplest logic circuit, it has become obsolete.
RTL has the benefit of having low power dissipation per gate. This family's
shortcomings include a poor noise margin and a considerably longer
propagation delay.
 Fig. 3
Direct Coupled Transistor Logic (DCTL):
The direct coupled transistor logic circuit is similar to RTL, only it doesn't
have the base resistances. Figure 4 shows the DCTL circuit for a two-input
NOR gate. When one or both inputs are high (logic1), the matching transistor
or transistors will conduct, and current will flow through the resistance R,
resulting in a low output (logic 0).
When both inputs are low, however, it correlates to a high output voltage. This
logic is straightforward and only requires a few components, however it
suffers from a low noise margin.

Fig.4
Integrated Injection Logic (IIL or I2L): The simplest logic family, this
family of bipolar transistors has a high packing density, allowing a large
number of digital functions to be built on a single chip. Individual gates in the
SSI package are not available because the I2L family is available in the LSI
package for complicated digital functions such as microprocessors.
Figure 5 shows the logic diagram of three - input I2L NOR gate. The inverter,
which is depicted in the shaded box, is the circuit's fundamental component.
The PNP transistor T1 acts as a constant current source, injecting current into
the transistor T4's base. When the input is set to logic 0 (grounded), the
injected current is grounded, directing the current away from transistor T4's
base. As a result, this transistor enters cutoff, and the output is high. When the
inverter's input A is high, the injected current from the current source flows
into the base of the transistor T4, causing it to switch on. The output is low.
The circuit for three - input NOR gate is the combination of three inverters
and its operation may be explained in the similar fashion.
It has a low power requirement and reasonably good switching speeds.

Fig. 5
Diode – Transistor Logic (DTL)
After RTL, diode transistor logic (DTL) came next, with a high noise margin
but sluggish speed. The name diode transistor logic comes from the use of
diodes and transistors in DTL. The positive logic two input DTL NAND gate
is shown in Figure 6. The following is an explanation of how it works:
When both inputs are set to logic 0, the diodes D1 and D2 are in forward bias,
and the voltage at point P is equal to the diode's forward voltage drop of 7.0.≈
V). Through the diode D3, this voltage is delivered to the base of the transistor
T1, causing the transistor T1 to cutoff. As a result, the output voltage will be
high (logic1). The transistor T1 is ensured to be in cutoff by the diode D3. The
transistor may be in the active zone without this diode, and the output would
be insufficient. When one of the two inputs is set to logic 1, the associated
diode is reverse biased, while the other diode is forward biased, resulting in a
voltage at point P equal to the diode's forward voltage. This causes the
transistor T1 to cutoff, resulting in a high output voltage (logic 1). When both
inputs are set to logic 1, the diodes D1 and D2 will be in reverse bias, and the
voltage at point P will be high, causing the transistor T1 to become saturated.
The transistor's output will be VCE, Sat (2.0 V). The output is said to be logic
0 in nature.
When the transistor T1 is shut off from its saturated state, the resistance R2
connected between the transistor's base and ground removes the accumulated
base charge. The lower the value of this resistance, the shorter the gate's
propagation delay; however, the value of this resistance cannot be reduced
below a particular level, or the transistor T1 will never be saturated.
 Fig. 6

This logic has a long propagation latency of about 50 nanoseconds.

High – Threshold Logic (HTL)
A high threshold logic gate is a DTL gate that has been modified. It has a
broad noise buffer, making it ideal for industrial applications. The logic
diagram of a two-input HTL NAND gate is shown in Figure 7. This logic
circuit was created with a greater supply voltage in mind (15 V). It makes use
of a zener diode with a 6.9 V breakdown voltage.

Fig. 7
When the emitter of transistor T1 is at 7.5 V, the transistor T2 will conduct,
as the sum of the 6.9 V zener voltage and T2's VBE (0.6 V). The HTL gate's
low output level will be 0.2 V, and the high level will be around 15 V. When
one or both of the inputs are low, transistor T2 is turned off.
Transistor T2 saturates when both inputs are high.
The advantage of this gate is that it has a high noise margin, but it is slow.
Transistor – Transistor Logic (TTL)
TTL logic is the most extensively used IC technology and is the most popular
of all logic families. It's a truncated version of DTL. In TTL, the propagation
delay time is shortened by replacing diodes with multi-emitter transistors. The
schematic diagram of a basic TTL positive logic NAND gate is shown in
Figure 8. It is made up of a T1 multi-emitter transistor. As demonstrated in
Figure 9, a two emitter transistor is comparable to two transistors with a
common base and common collector.
The following is a description of how the TTL NAND gate works:
When one or both of the inputs A are at logic 0, the multi-emitter transistor's
emitter base junction is in forward bias, and base current is supplied by the
resistor R1. The transistor T1 saturates, and the voltage at the point equals the
transistor's VCE, Sat (2.0 V). The transistor T2 will be cutoff, resulting in a
high output voltage (logic 1).

Fig. 8 Fig. 9

When both inputs are set to logic 1 (+5 V), the emitter base junctions of
transistor T1 are reverse biased, and current flows via R1 and into the base of
transistor T2 via the forward biased base collector junction of transistor T1.
The transistor is considered to be inverted in this mode because the collector
of transistor T1 acts as an emitter and the emitter acts as a collector. The
voltage at point P will be enough to push the transistor T2 into saturation,
resulting in an output voltage of VCE,Sat (2.0 ˜͌ V) or logic 0.
This gate has a shorter propagation delay than a DTL NAND gate because
when the transistor T2 transitions from saturation to cutoff, the transistor T1
saturates and offers a low impedance path to ground. As a result, the transistor
T2's stored base charge is promptly released, lowering the propagation delay
time.
When the transistor T2 saturates or the output is low, the output resistance of
the basic TTL circuit (fig. 8) is low (logic 0). When the transistor is in cutoff
or the output is high, however, the output resistance of this circuit is nearly
equal to the resistance R. (logic 1). This will limit the fan's ability to get out of
the gate. The power dissipation in R and the gate would increase if the resistor
R was reduced. It would also be difficult to saturate the transistor T2 with a
lower R value. TTL gate with totem pole layout is utilized to overcome this
challenge.
TTL NAND Gate with Totem-pole Output
The standard form of a TTL circuit with an input NAND gate is shown in
Figure below. The following is how the circuit works:
The transistor T2 enters cutoff mode when either or both inputs are low (logic
0). Because the voltage drop across the resistor R3 is practically zero, the
transistor T4 will also be in cutoff. T3 is now conducting and acting as an
emitter follower. This transistor's emitter output voltage will be equal to the
collector voltage of the transistor T2, which is quite high (logic1). The emitter
follower, on the other hand, gives a low output resistance to the driven gate's
input.
Transistor T2 conducts and operates as an emitter follower when both inputs
are high (or at logic 1). The voltage across R3 will be enough to drive the
transistor T4 to saturation. Because the transistor T4 saturates, the output
voltage will, therefore, be equal to VCE, Sat ( 2.0 ≈ V) or logic 0. The low
output impedance is due to the fact that this output is taken at the collector of
the transistor T4, which is in saturation. When the transistor T4 saturates, the
diode D stops the transistor T3 from conducting. T4 has a potential of
approximately 0.8 V (VBE,Sat) across the emitter base junction, and T2 has a
collector emitter voltage of 0.2 V. (VCE,Sat). This means that the base of
transistor T3 receives a total of 1.0 V. This voltage would be sufficient for the
transistor T3 to conduct in the absence of the diode D. The diode D, on the
other hand, lowers the base emitter voltage of transistor T3 below 0.7 V,
which is required for transistor conduction. When T4 saturates, the diode D
drives the transistor T3 into cutoff.
When negative voltage spikes arise at the inputs, diodes D1 and D2 safeguard
the transistor T1 from damage. The diodes conduct and the spikes are
grounded when negative spikes emerge at the input terminals. The totem pole
output is formed by the transistors T3 and T4 and the diode D, which gives
low output impedance in all cases. TTL gates are faster, with a propagation
time of around 15 nanoseconds.
TTL Inverter
A TTL circuit for an inverter is shown in Figure 11. The operation principle is
the same as for the TTL NAND gate, with the exception that it only has one
input. As a result, if input A is logic 0, output will be high (logic 1), and if
input is logic 1, output will be low (logic 1). (logic 0). The totem-pole output
is also included in this circuit.
Fig. 11

TTL NOR Gate

A TTL circuit for two input NOR gates is shown in Figure 12. It is made up of
two input transistors T1 and T2, as well as two additional transistors T3 and
T4, which are coupled in parallel to form a phase splitter. The output is also
obtained using the totem pole circuit, which consists of transistors T3, T4, and
diode D. This circuit's operation can be stated as follows:
When both inputs are low, the input transistors' emitter base junctions are in
forward bias, and no current flows through the bases of transistors T3 and T4.
As a result, these transistors will be cutoff. As a result, transistor T5 will
conduct and transistor T6 will be in cutoff, resulting in a high (logic 1) output.
Transistor T3 is in cutoff and transistor T4 saturates when input A is low and
input B is high. As a result, transistor T6 will conduct and transistor T5 will be
in cutoff, resulting in a low (logic 0) output.
When input A is high and input B is low, the transistor T4 saturates, and the
transistor T3 enters cutoff mode. As a result, transistor T6 will conduct and
transistor T5 will be in cutoff, resulting in a low (logic 0) output.
When both inputs are high, the input transistors' emitter base junctions are
reverse biased, and current flows through the bases of transistors T3 and T4.
As a result, these transistors will be saturated. As a result, transistor T6 will
conduct and transistor T5 will be in cutoff, resulting in a high (logic 0) output.

Fig. 12
TTL AND Gate
A TTL two-input AND gate is shown in Figure 13. The AND function is
achieved by adding an extra inversion circuit before the TTL NAND gate's
totem output. The AND gate is created by converting the NAND gate to an
AND gate. The transistors T2 and T3 make up the extra inversion circuit.
 Fig. 13
TTL OR Gate
As shown in figure 14, the TTL OR gate is made by putting a common
emitter circuit before the TTL NOR gate's totem pole output. The inversion
provided by the common emitter circuit changes the NOR gate to an OR gate.
The common emitter circuit is made up of the transistor T5 and its
accompanying components.
Fig 14

Open Collector TTL Gates

The totem pole output circuit is connected in all TTL gates, as detailed in the
preceding sections. TTL gate integrated circuits with open collector output are
also available. A two-input TTL NAND gate with an open collector is shown
in Figure 15.
Other gates with open collector outputs are also available. The lowest
transistor of the totem pole circuit is employed with its collector open or
floating in the open collector output gates. Figure 16 shows how to connect an
external pull-up resistor between the collector and the positive supply to get
the desired output.

Fig. 15 Fig. 16
The open collector gates have the advantage of being able to link their outputs
together and connect them to a common pull-up resistor, removing the
requirement for an AND gate. As seen in figure 17, this can be shown by
connecting the open collectors of three NAND gates with a pull-up resistor R.
Figure 18 shows the equivalent circuit, in which the outputs of three NAND
gates (open collector) are linked to a pull-up resistor R.

Fig. 17 Fig. 18
The output voltage is brought down to a low value when any or all transistors
are saturated. The pull up resistor R, on the other hand, pulls the output
voltage to a high value if all the transistors are in cutoff. As a result, the
ANDing of the outputs is produced.
There are three gates. Wiring the outputs of open collector devices to a
common pull-up resistor to get the ANDing action is known as wire –AND.
With this strategy, any number of gates can be ANDed together. The output of
circuit shown in figure 18 is given by:

With TTL devices with totem pole outputs, the wire – AND is not possible.
When the outputs of two or more of these devices are coupled together and
one is low and the other is high, the final output is shorted, resulting in
excessive power dissipation. As a result, a separate AND gate is required to
AND the outputs of TTL devices.
The slow pace of open-collector gates is their principal problem.

Tri-state TTL Gates

The open collector gate has the capability for wire – AND – they are slow in
speed, as shown in the preceding discussion. The gates with totem pole
outputs, on the other hand, are faster, but wire –AND connections are not
possible. This resulted in the creation of a new gadget known as tri-state TTL
gates.
The output states of tri-state devices are High, Low, and High impedance,
respectively. The output terminal has a high impedance between it and ground
or positive supply in the high impedance mode. In this scenario, the output is
floating. Figure 19 depicts a simple tri-state TTL inverter circuit, whereas
Figure 20 depicts its logical symbol. In this circuit, input A is a standard logic
input, while the ENABLE E terminal is an enable input capable of producing
high impedance output.
 Fig.19 Fig. 20

When the ENABLE E terminal is set to high (logic 1), the diode D1 remains in
reverse bias, having no influence on the operation of transistors T3 and T4. As
a result, the circuit functions as a regular inverter. When the ENABLE E
terminal is low (logic 0), the diode D1 is in forward bias and drains the
transistor T3's base current. As a result, this transistor will be disabled. The
forward bias diode D1 also forward biases the transistor T1's emitter base
junction, which switches off transistor T2, which then turns off transistor T4.
When logic 0 is applied to the ENABLE E terminal, both the transistors T3
and T4 of the totem pole output are shutdown.
Other gates, as well as equivalent circuits, can be configured in a tri-state
design. The advantage of this setup is that wire –ANDing of tri-state IC
outputs is conceivable, and it is also quick.
More TTL Circuits: TTL circuits are divided into three groups:
High Speed TTL circuits
Medium Speed TTL Circuits Slow Speed TTL Circuits
Figure 21 shows the TTL NAND gate circuit with three values for each
resistor R1, R2, R3, and R4 for each of the three families. Low resistance
values are used for high speed, however the power dissipation is higher since
low resistance values take a lot of current from the supply. TTL gates in the
54H/74H family are available and designed for high speed. The letter H stands
for high speed. The typical propagation delay and power consumption for a
high-speed gate are 6 nsec and 22 mW, respectively. These resistances have
medium levels for medium speed. For medium-speed TTL gates, the 54/74
series is available. This is the standard series, with a propagation delay of 10
nanoseconds and a power usage of 10 milliwatts. The resistances utilized in
slow speed TTL gates are high, and the series available for slow speed is
54L/74L. Slow speed gates have a propagation delay of 33 nsec and a power
usage of 1 mW. The 54 series is the 74 series' counterpart, and the two are
interchangeable. The 54 series is mostly employed in the military since it can
work over a greater temperature range and voltage range.

Fig. 21

Schottky Transistor – Transistor Logic (STTL)

 Fig. 22 Fig. 23

The operation speed of Schottky TTL circuits is substantially faster than that
of high-speed TTL circuits. When transistors in TTL circuits go from
saturation to cutoff, they take a particular amount of time. This reduces the
time it takes for the gates to propagate. This latency can be minimized by
using Schottky transistors instead of transistors in TTL circuits. As shown in
Figure 22, a Schottky transistor is created by connecting a Schottky barrier
diode between the base and collector of a transistor. The circuit diagram of a
two-input Schottky TTL NAND gate is shown in Figure 23. It's worth noting
that the transistor T4 is a standard transistor.
Schottky Transistor – Transistor Logic (STTL) gates are available in the
54S/74S series. This logic family consumes less power than the 54H/74H
series and has a speed that is twice that of the 54/74 series. Schottky TTL in
the 54LS/74LS family is still accessible at low power. The resistances utilized
in the 54S/74S series were increased to create this series. As a result, the
switching speed of this logic gate family is the same as that of the normal TTL
family (54/74), and the power dissipation is one-fifth that of the 54/74 series.

Emitter Coupled Logic (ECL)

Emitter Coupled Logic (ECL) circuits belong to the non-saturated digital logic
family, which means that the transistors do not saturate. This reduces the
storage time delay, allowing this family to operate more quickly. This logic
family offers the fastest speed, with a propagation latency of about 1 nsec per
gate.
The fundamental circuit of a four-input ECL OR/NOR gate is shown in Figure
24. Both OR and NOR operations are available at the outputs. The differential
amplifier circuit is formed by transistors T1 through T5, the internal
temperature and voltage compensation bias network is formed by transistor
T6, and the emitter follower outputs for OR and NOR functions are formed by
transistors T7 and T8. Negative logic levels are expected for this family, with
– 0.9 V for logic 1 and − 1.75 V for logic 0. This circuit's operation can be
stated as follows:
Because the emitter base junctions are reverse biased, the transistors T1
through T4 are turned off when all the inputs are low (− 1.75 V). The
transistor T5 is not saturated and is conducting. The base of transistor T5
remains at – 1.29 V due to correct biasing of transistor T6. As a result, its
emitter voltage is - 2.09 V, which is 0.8 V lower than the base voltage. As a
result, the transistor T5 is turned on. The transistors T1 through T4 have a –
0.34 V differential voltage between their base and emitter, indicating that they
are cutoff. The outputs of the emitter follower transistors T7 and T8 are 1.75 V
(logic 0) and 0.9 V (logic 1), respectively.
When any or all of the inputs are at – 0.9 V (logic1), the appropriate transistor
or transistors will conduct in that situation. As a result, the voltage at the
emitters of T1 through T5 rises to − 2.09 V. The bias network keeps the base
of transistor T5 at – 1.29 V, causing it to go into cutoff. T7 and T8 emitter
follower transistors produce 0.9 V (logic 1) and 1.75 V (logic 0) outputs,
respectively. Figure 25 shows a symbolic illustration of the OR/NOR ECL
gate.
 Fig. 24 Fig. 25
As seen in figure 26, wired logic can be created by connecting the outputs of
two or more ECL gates. A wired –OR function is created by connecting two
NOR outputs outside. Some ECL ICs use an internal –wired connection of two
OR outputs to create a wired –AND logic.

Fig. 26

MOS Logic
Bipolar transistors were used in all of the logic families previously covered.
Their comparisons were done with respect to particular logic family
parameters. Another unipolar logic family, such as the Metal Oxide
Semiconductor Field Effect Transistor (MOS FET), will now be described.
The MOS logic family is the simplest to manufacture and takes up the least
amount of space. It just requires N channel MOS or P channel MOS field
effect transistors, as well as no extra resistors, diodes, or other components.
High packing density, low power dissipation, and high fan-out characterize
this logic family. NMOS (enhancement type N channel MOS FETs) or PMOS
(enhancement type P channel MOS FETs) logic circuits can be used. The
following properties of MOS FETs can be seen from their operations. When
the gate is at a positive potential with respect to the source, the NMOS
operates, while the PMOS operates when the gate is at a negative potential
with respect to the source. Neither of the two MOS FETs will conduct if the
gate is at zero voltage.
MOS inverter
Figure 27 depicts the circuit diagram for an NMOS inverter, while figure 28
depicts the circuit diagram for a PMOS inverter. The circuits all operate in the
same way. Because T1 is conducting while the gate is linked to the drain in
both circuits, it acts as a resistor.

Fig. 26 Fig. 27
When input A is set to logic 0 (ground potential), the MOS FET T2 is turned
off, resulting in a high voltage at the output (see figure 26). As a result, the
outcome is logic 1. When input A is set to logic 1 (VDD potential), the MOS
FET T2 is turned on, and the output is set to logic 0. This ensures that the
inverter is working properly. The operation of PMOS will be presented in the
same way, with the exception that it operates on negative logic.

MOS NOR gate:

The circuit diagrams for the NMOS positive logic three-did not input NOR
gate and the PMOS negative logic three-input NOR are gates shown in Figures
28 and 29, respectively. When all three inputs are at logic 0 (ground potential)
in an NMOS NOR gate (ref. fig. 28), MOSFETs T2 through T4 are turned off,
resulting in a high output (logic 1). If any (one or two) of the three inputs are
set to logic 1, the corresponding MOSFET or MOSFETs will conduct,
resulting in a low output (logic 0). The operation of the positive logic NOR
gate is verified in this way. The behavior of the PMOS NOR gate can be
explained in the same way that negative logic works. In both circuits, the
MOSFET T1 operates as a resistor.

Fig. 28 Fig. 29

MOS NAND gate

Figures 30 and 31 depict three input NAND gates using NMOS and PMOS
transistors, respectively. Positive logic is used by the NMOS NAND gate,
while negative logic is used by the PMOS NAND gate. The operation of the
NMOS NAND gate is as follows: (ref. Fig 28).
When all three inputs are at logic 1 (+ VDD), the NMOS FETs T2 through T4
will conduct, resulting in a low output (logic 0). When any (one or two) of the
three inputs is set to logic 0 (ground potential), the matching MOS FET or
MOS FETs will be turned off, resulting in a high output (logic1). This proves
the operation of a positive logic NAND gate; similarly, the operation of a
negative logic PMOS NAND gate may be explained.

Fig. 30 Fig. 31

Complementary MOS (CMOS) Logic

Both enhancement type P-channel and N-channel MOSFETs are arranged in a
complimentary connection in the complementary metal oxide semiconductor
(CMOS) logic family. Because neither P-channel nor N-channel MOSFETs
conduct simultaneously when no signal is applied to the logic's input
terminals, the CMOS logic family consumes relatively little power.
As a result, only the leakage current flows between the supply terminals. The
CMOS gate can work with a wide variety of supply voltages, from 3 to 15
volts. It has a better noise margin than TTL devices. This has a considerably
greater fan-out. CMOS logic has a speed equivalent to TTL circuits, however
it is faster than Schottky TTL circuits.

CMOS Inverter
Figure 32 depicts the circuit diagram of a CMOS inverter, which consists of a
complementary mode connection between a PMOS transistor T1 and an
NMOS transistor T2. Both transistors' drains are connected together, and the
output is obtained this way. The positive supply is connected to the source
terminal of the PMOS transistor T1, whereas the source of the NMOS
transistor T2 is grounded.
The gate of PMOS transistor T1 is at a negative potential with respect to its
source when the input A is grounded (logic 0), hence it is ON. T2 is turned off
because the gate of the NMOS transistor is at ground voltage. As a result, the
output is high (+VDD), logic 1.
When input A is high (logic 1), the gate of PMOS transistor T1 is at zero
potential with respect to its source, and the transistor is turned off. T2 is ON
because the gate of the NMOS transistor is at a positive potential with respect
to ground. As a result, the output is low logic 0.

Fig. 32
CMOS NAND Gate
Figure 33 depicts the CMOS NAND gate circuit diagram. Two PMOS
transistors T1 and T2 are connected in series with their sources connected
together, while two NMOS transistors T3 and T4 are connected in parallel
with their sources connected together.
The gates of T1 and T2 are at negative potentials with respect to their sources
when both inputs are at logic 0 (grounded); the gates of T3 and T4 are at zero
potential. T1 and T2 are both PMOS transistors, while T3 and T4 are NMOS
transistors. As a result, the output will be high (logic 1).
When input A is logic 0 (grounded) and input B is logic 1, the gate of T1 is at
negative potential in relation to its source, and the gate of T2 is zero; the gates
of T4 and T3 are at zero and VDD potential, respectively. T1 and T3 are
turned on, but T2 and T4 are turned off. As a result, the output will be high
(logic 1).

Fig. 33
T1 and T3 will be off and T2 and T4 will be ON when input A is logic 1 and
input B is logic 0 (grounded). As a result, the output will be high (logic 1).
The gates of T1 and T2 are at zero potential with respect to their sources when
both inputs are at logic 1 (+VDD); the gates of T3 and T4 are at negative
potentials with respect to their sources when both inputs are at logic 1
(+VDD). As a result, both PMOS transistors (T1 and T2) are turned off, while
NMOS transistors (T3 and T4) are switched on. As a result, the output will be
grounded (logic0).
CMOS NOR Gate
Figure 34 shows a circuit diagram for a CMOS NOR gate. T1 and T2 are two
PMOS transistors connected in series, and T3 and T4 are two NMOS
transistors connected in parallel.
The gates of T1 and T2 are at negative potentials when both inputs are at logic
0 (grounded); the gates of T3 and T4 are at zero potential. T1 and T2 are both
PMOS transistors, while T3 and T4 are NMOS transistors. As a result, the
output will be high (logic 1).
When input A is logic 0 (grounded) and input B is logic 1, T1's gate is at
negative potential with regard to its source, and T2's gate is zero; T3 and T4's
gates are at zero and VDD potential, respectively. T1 and T3 are turned on,
but T2 and T4 are turned off. As a result, the output will be low (logic 0).
T1 and T3 will be off and T2 and T4 will be ON when input A is logic 1 and
input B is logic 0 (grounded). There will be a low production (logic 0).
The gates of T1 and T2 are at zero potential when both inputs are at logic 1
(+VDD), whereas the gates of T3 and T4 are at VDD potential. As a result,
both PMOS transistors (T1 and T2) are turned off, while NMOS transistors
(T3 and T4) are switched on. As a result, the output will be grounded (logic0).

Fig. 34

Comparison of Logic Families

The comparison of important logic families are given in table 1 in respect
of logic parameters.
Table 1
Programmable logic devices

Types of Logic Devices

Logic devices are divided into two groups. Fixed logic devices and
programmable logic devices are the two types of logic devices. .
Fixed Logic Device
A fixed logic device performs a certain logic function that the user is aware of
at the time the device is built. A logic gate, a multiplexer, or a flip-flop are
examples of fixed logic devices. In terms of internal schematic arrangement,
the circuits or building blocks in a fixed logic device, as well as their
interconnections, are permanent and cannot be changed after the device is
created. The figure below shows a simple logic circuit consisting of four three-
input AND gates and an output OR gate. When looking at the circuit diagram
above, one can see that the circuit is a fixed logic device since the
interconnections between the various building blocks are fixed. This circuit
above will produce an output that is the sum output of a full adder and in such
a case, A and B are the two bits to be added together while input C is the
carry-in bit.

Programmable Logic Device

A user can programme a programmable logic device to perform a wide range
of logic functions. This logic device provides a broad variety of logic capacity
in the form of digital building blocks that the user can design to accomplish
the desired function or collection of functions. They also allow the user to
change or modify this configuration as many times as they want by
reprogramming the device instruction before it is executed. The first resistance
to an anti-fuse is extremely high. This means that any AND gate can yield the
three-variable product term that is requested. The function of an anti-fuse is
the polar opposite of that of a standard electrical fuse.
A simple programmable device is seen in the diagram below. A programmable
AND array at the input and a fixed OR gate at the output may be seen in the
logic circuit above. This form of programmable logic device architecture is
known as programmable array logic (PAL). The device contains an input array
of four six-input AND gates and an output array of four four-input OR gates,
each of which can handle three variables and so construct a three-variable
product term. Through anti-fuses, the three variables (A, B, and C) or their
complements can be programmed to appear at the inputs of any of the four
AND gates.
 Comparison between Fixed Logic and Programmable Logic devices:

1. When creating a fixed logic device to perform a specific function, the

time it takes from design to the final stage when the manufactured device is
actually ready for use can easily be several months to a year or more, whereas
programmable logic device (PLD)-based design takes much less time from
design to production run.
2. In fixed logic devices, the process of design validation followed by
change incorporation involves significant non-recurring engineering (NRE)
costs, resulting in an increased cost of the initial prototype device, whereas in
programmable logic device (PLD)-based design, inexpensive software tools
can be used for quick design validation. Because these devices are
programmable, changes may be made quickly and the device can be tested in
an actual application context quickly.
3. Fixed logic devices do not enable changes, whereas programmable
logic devices allow the user to change the circuit as many times as they want
until they achieve the desired design. PLDs provide significantly more
freedom to users during the design cycle, so design iterations are simply
changes to the programming file.
4. Fixed logic devices have an advantage in high-volume applications
because they can be mass-produced and are more cost-effective. They're also
the best option for applications that demand the highest level of performance.

Types of Programmable Logic Devices

Precisely what a programmable logic device is depends on the application.
They differ from one another in terms of architecture, logic capability,
programmability, and a few other special characteristics.
Programmable Read Only Memory (ROMs)
There are two types of programmable memories in this category:
(i) Programmable Read Only Memory- (PROM)
(ii) Erasable Programmable Read Only Memory - (EPROM)
The user can do hardware implementation utilizing any arbitrary
combinational function of a given number of inputs thanks to the
programmable ROM architecture. When a programmable ROM is utilized as a
memory device, the ROM's n inputs serve as address lines, while the ROM's m
outputs serve as data lines, allowing 2nm-bit words to be stored. In this
scenario, the PLD can be used to implement m multiple combinational
functions, each of which is selected from n separate variables. Any n-variable
Boolean function can be configured to display on any of the m output lines in
this state.
A generalized ROM device with n inputs and m outputs has 2n hard-wired
AND gates at the input and m programmable OR gates at the output. Each
AND gate has n inputs but each OR gate has 2n inputs. Each OR gate can be
utilized to create any n-variable Boolean function. This generalized ROM can
be used to generate m arbitrary n-variable Boolean functions, where each
AND array generates all conceivable minterms for a given number of input
variables, but a programmed OR array just allows the required minterms to
appear at their inputs. Shows in the figure below is the internal architecture of
a four input line PROM having a hard-wired array of 16 AND gates and a
programmable array of four OR gates. In this figure a cross (×) represents an
unprogrammed fusible link or interconnection while a dot (•) represents a
hard-wired interconnection PROMs, EPROMs and EEPROMs (Electrically
Erasable Programmable Read Only Memory) are programmed using
standard PROM programmers.
Because most PROMs inefficiently employ their logic capacity, they are not
cost-effective for all applications requiring merely a few minterms. Its
inefficiency also includes greater power consumption and the inability to offer
safe coverings for the majority of asynchronous logic transitions or operations.
Finally, it's worth noting that they're much slower than dedicated logic
circuits, and they can't be used to create sequential logic operations because
they lack flip-flops.
Programmable Logic Array (PLA)
A programmable logic array device is a device with a programmable AND
array at the input and a programmable OR array at the output in digital
electronics. As a result, they are one of the most adaptable PLDs, and their
internal architecture differs significantly from that of a conventional PROM in
many aspects. It is made up of a programmable AND array rather than a hard-
wired AND array; in an m-input PROM, the number of AND gates is always
equal to 2m.
In a PLA, the number of AND gates in the programmable AND type of array
for an m input variables is are always lower or much less than 2m while the
number of inputs of each of the OR gates are always equal to the number of
AND gates. Therefore each OR gate resent can generate a Boolean function
with maximum of minterms always equal to the number of AND gates in the
logic architecture. A PLA device with four input lines can also have an
internal architecture with a programmable array of eight AND gates at the
input and another programmable array of two OR gates at the output. A PLA
device uses logic capacity more efficiently than a PROM.

Programmable Array Logic

A programmable AND array is presented at the input of a Programmable array
logic architecture, and a fixed OR array is used at the output, though the
programmable AND array of a PAL device is almost identical to that of a PLA
device because the number of programmable AND gates is less than the
number required to generate all possible minterms of the given number of
input variables. The OR array is normally fixed in this situation, and the AND
outputs are distributed evenly among the OR gates in the design.
The device can contain eight input variables, 64 programmable AND gates,
and four fixed OR gates, each with 16 inputs, in many commercial PALs. This
means that 16 of the 64 AND outputs are sent into each OR gate. To introduce
readers to the arrangement of various building blocks inside a PAL device and
allow them to compare different programmable logic devices, the figure below
shows the internal architecture of a PAL device with four input lines, an array
of eight AND gates at the input, and two OR gates at the output.
Complex Programmable Logic Device (CPLD)
Because the term "complex" corresponds to more advanced and difficult-to-
perform functions, programmable logic devices such as PLAs, PALs, and
other PAL-like devices are grouped together as "simple programmable logic
devices" (SPLDs). This makes them stand out from the others, which are more
complicated in design and operation. A complex programmable logic device is
far more sophisticated than any of the other programmable logic devices since
it has circuitry comparable to many PAL devices cascaded or linked together
by programmable interconnections.
Because the term "complex" corresponds to more advanced and difficult-to-
perform functions, programmable logic devices such as PLAs, PALs, and
other PAL-like devices are grouped together as "simple programmable logic
devices" (SPLDs). This makes them stand out from the others, which are more
complicated in design and operation. A complex programmable logic device is
far more sophisticated than any of the other programmable logic devices since
it has circuitry comparable to many PAL devices cascaded or linked together
by programmable interconnections. The complexity of a CPLD can be
equivalent to tens of thousands or even millions of logic gates, resulting in
complex programmable logic circuitry. After connecting it on the PC board, a
CPLD can be programmed using a PAL programmer or by feeding it a serial
data stream from a PC. The data stream is decoded and configured by a circuit
on the CPLD to perform the intended logic function.

Due to their less flexible internal architecture than FPGAs, CPLDs have
predictable temporal characteristics. As a result, they are best suited for
critical control applications and other applications requiring a high level of
performance or complex processes. CPLDs also form a class of perfect
solution gadgets for battery-operated portable applications due to their
significantly lower power consumption and lower cost. As a result, they're
often found in electronic devices such as cell phones and personal digital
assistants.
Programmable ROMs
Memory is nothing more than a data storage device. A Read Only Memory
(ROM) is a type of memory that can only hold a specific set of binary data or
instructions. Depending on the type of fusible link used to store any user-
specified binary information in the device, specific links in the ROM can be
made or broken.
The underlying logic diagram of an unprogrammed 42 PROM using a fuse and
an antifuse to produce output-1 = AB is shown in the graphic above. An
unprogrammed interconnection is a ‘make' connection in the case of a fuse,
but a 'break' connection in the case of an antifuse. Once a pattern is
established, it does not change even if the power is turned on and off. In the
case of PROMs, the user can wipe the data from the ROM chip and replace it
with new data.
In general, a PROM with n input lines and m output lines is referred to as a
2n×m PROM. When you look at the inside of a PROM device, you'll notice
that it's a combinational circuit with AND gates connected as a decoder and
OR gates equivalent to the number of outputs. For example, a PROM with five
input lines and four output lines would have the equivalent of a 5×32 decoder
at the input, generating 32 different minterms or product terms. Each of these
four OR gates would have 32 inputs and be supplied from the decoder's 32
outputs through fusible connections.
A 32×4 PROM's above lying architecture contains a large number of AND
gates, with four OR gates on the output side and the input side hardwired to
produce all 32 product terms corresponding to five variables. Through
programmable linkages, all 32 product terms or minterms are available at the
inputs of each of the OR gates. This allows users to choose from four different
five-variable Boolean functions. PROMs can be used to create very
complicated combinational functions by appropriately forming or breaking
these links. To summarize, a 2n×m PROM is required to create an n-input or
n-variable, m-output combinational circuit. This PROM can be used to create
a Boolean function with two types of outputs, as seen below.
F1 (A, B, C) = ∑m (1, 2)
F2 (A, B, C) = ∑m (1, 4, 7)
This Boolean function would necessitate the use of an 8×2 PROM to
implement. In reality, a When employing PROMs to construct Boolean
functions, the procedure becomes more cost-effective when the number of
'don't care' conditions is big and each 'don't care' condition has either all 0s or
all 1s. PROM would not be utilized to create a Boolean function as simple as
the one shown above. The goal of this section is to show how a PROM
implements a Boolean function. PROMs would only be employed in the case
of extremely complex Boolean functions in practice.

Programmable Logic Array (PLA)

The sum-of-product forms of Boolean functions were discussed. A
programmable logic array is based on this, and it allows logic functions to be
stated in sum-of-products form and implemented directly. The resulting
product terms can be summed up in an array of programmable OR gates,
which is why the output has a programmable OR gate array. The input and
output gates are built as arrays, with input lines parallel to product lines and
product lines parallel to output lines. When examined closely, it resembles a
PROM in concept, however unlike a PROM, the PLA does not give complete
decoding of the input variables nor does it generate all conceivable minterms.
In a PROM, the input has a fixed AND gate array and the output has a
programmable OR gate array, but in a PLA device, the input has a
programmable AND gate array and the output has a programmable OR gate
array. Similarly, in a PLA device, an AND gate generates each of the product
terms of the provided Boolean function, which can also be programmed to
produce the AND of any subset of inputs or their complements.
The internal architecture of a programmable PLA device with AND gate array,

which has eight AND gates with four input lines, eight product lines, and four
output lines, is shown in the diagram above. Each AND gate has eight inputs,
one for each of the four input variables and their complements. In this
scenario, the AND gates' inputs are configured to accept any of the 16 possible
combinations of four input variables and their complements. This means that
four OR gates at the output can yield four different Boolean functions, each of
which can contain a maximum of eight minterms out of a total of 16 minterms
with four variables. PLAs use inverters at the outputs of OR gates to
implement a Boolean function in either AND-OR or AND-OR-INVERT
mode.
As a result, the picture below illustrates a generalized block schematic
depiction of a PLA device with n inputs, m outputs, and k product terms, with
n, m, and k denoting the number of input variables, OR gates, and AND gates,
respectively. As a result, each OR gate and each AND gate have k and 2n
inputs, respectively, as shown in the diagram.

In most circumstances, a PLA is specified in terms of the number of inputs,

product terms, and outputs, and as a result, a PLA will always contain a total
of 2Kn+Km programmable interconnections. This implies then a ROM with
the same number of input and output lines would have 2n×m p programmable
interconnections and therefore a PLA is either mask programmable or field
programmable. When ordering a mask programmable PLA, the customer
provides a programme table to the manufacturer, who then creates a custom
PLA with the desired internal routes between inputs and outputs. A field-
programmable logic array (FPLA) is programmed by the users using a
commercially available hardware programmer device.
When using a PLA to create a Boolean function, each expression is reduced to
the smallest number of product terms possible, reducing the number of AND
gates necessary. The simplification of Boolean functions reduces the amount
of literals in various product terms to become insignificant because all input
variables are available to different AND gates. Each of the Boolean functions
and their complements should be simplified, and the less product terms that
are shared by several functions is desired.
Programmable Array Logic (PAL)
Advanced Micro Devices Inc. owns the PAL device trademark. PAL devices,
on the other hand, are less adaptable than PLA devices. The decision to use a
fixed OR gate array at the output to simplify the device stemmed from the fact
that many applications did not fully leverage the PLA's product-term sharing
capability, resulting in wasted resources. Different output logic topologies,
such as the availability of both OR and NOR outputs, bidirectional pins that
can operate as both inputs and outputs, and clocked flip-flops at the outputs to
enable registered outputs, can increase the versatility of a PAL device. The
programmable array logic device (PLA) is a type of PLA. At the input, it has a
programmable AND gate array, and at the output, it has a fixed OR gate array.
The PLA's capabilities enable it to be employed in a broader range of
applications than a device with set input and output allocations. The HAL
(Hard Array Logic) device is the mask-programmed variant of PAL. A HAL
device and its PAL counterpart are pin-to-pin compatible.

PAL Architecture
The figure below depicts a PAL device with a generalized PLA architecture
and a programmable AND gate array that is fed with multiple input variables
and their complements. Any of the input variables or their complements can
appear at the inputs of any of the AND gates in the array thanks to
programmable input connections. Each AND gate produces a minterm from a
user-defined set of input variables and their complements. The outputs from
this programmable AND array are fed into an array of hard-wired OR gates in
the picture below, which shows an example of the creation of minterms from a
generic PAL device.
The outputs of the AND gates do not go directly into the inputs of the OR
gates; instead, each OR gate is fed from a subset of the AND gates in the
array, as indicated in the diagram below. This means that depending on the
number of AND gates from which it is fed, the sum-of-product Boolean
functions formed by each of the OR gates at the output will only have a
limited number of minterms. Both OR and complementing (or NOR) outputs
are provided from the PAL device. Different output logic layouts are available
in practical PAL devices. The availability of both OR and NOR outputs is one
of them. Many PAL devices also provide registered outputs, in which the OR
gate output drives the D-input of a D-type flip-flop, which is loaded with data
on the LOW-to-HIGH or HIGH-to-LOW edge of a clock signal.

Programmability of inputs in a PAL Devices

Another feature is the availability of bidirectional pins that may be used as

both outputs and inputs. This, combined with the other capabilities, allows the
user to feed a product term back into the programmable AND array. It's also
useful in multi-output function logic circuits that share some common
minimums when they're needed. At each output, some PAL devices have an
EX-OR gate after the OR gate. One of the EX-OR gate's inputs can be
programmed, allowing the user to utilize it as an inverter, a non-inverting
buffer, or a two-input EX-OR gate. This capability comes in handy while
performing parity and arithmetic procedures.

Complex Programmable Logic Devices (CPLDs)

The basic internal structure of complex programmable logic devices is the
same as that of SPLDs. CPLDs have a logic capability that is roughly equal to
50 SPLDs. Instead of just extending the notion of SPLDs, programmable logic
devices with significantly higher logic capacity would necessitate a different
approach. Because the size of the programmable plane grows too quickly with
the number of inputs to make it a practical device, the internal design of
simple programmable logic devices such as PLAs and PALs does not increase
in complexity beyond a certain point. This type of increase can only be
accomplished in a roundabout method. Integrating many SPLDs on a single
chip with a programmable link between them is one technique to expand the
logic capacity of simple programmable logic devices.

Internal Architecture of Programmable Logic Devices

A CPLD is a single-chip integration of numerous PLDs with a programmable

interconnect matrix and an I/O control block, where identical PLDs are used
as logic blocks or function blocks.
The programmable interconnect matrix can connect the input or output of any
logic block to any other logic block, as shown in the block design above. The
input and output pins are directly connected to the interconnect matrix as well
as logic blocks, which are further divided into smaller logic units known as
macro-cells, each of which is a subset of a PLD-like logic block.
Each macro-cell is made up of a set of product terms generated by a subset of
the programmable AND array and fed to a configurable output circuit. An OR
and EX-OR gate, as well as at least one flip-flop, make up the output logic. In
CPLDs, the flip-flop can be configured as a D-type, J-K, T, or R-S flip-flop.
Any or all of the product terms formed within the macro-cell are passed into
the OR gate.
Most modern CPLDs include an architecture that allows the OR gate to be fed
with extra product terms generated by other macro-cells in the same logic
block. This product-term versatility is provided by a logic block from the
MAX-7000 series of CPLDs, which allows each macrocell's OR gate to have
up to 15 extra product terms from other macrocells in the same logic block.
Devices from different manufacturers may have small differences. Xilinx's
XC-7000 series CPLDs, for example, feature two OR gates supplied from a
two-bit arithmetic logic unit (ALU), and the ALU's output feeds a
customizable flip-flop.

Applications of CPLDs
PLDs are widely used in a variety of applications, including the
implementation of random glue logic in prototyping small gate arrays,
implementing critical control designs such as graphics controllers, cache
control, UARTs, LAN controllers, and III CPLDs are rapidly replacing SPLDs
in complex designs due to their less flexible internal architecture, which leads
to predictable timing performance, high speed, and a range of logic capacities.
Complex designs involving a large number of SPLDs can be substituted by a
CPLD-based design involving a considerably smaller number of devices, such
as mobile phones and digital assistants. The CPLD architecture is especially
well suited to designs that make use of wide AND/OR gates and don't
necessitate a huge number of flip-flops. CPLDs' reprogramming function
makes it simple to incorporate design modifications. It is also feasible to alter
the hardware without turning it off, thanks to the existence of CPLDs with an
in-circuit programming function. One of the most important benefits of the
CPLD architecture is its simple SPLD-like structure, which allows the design
to organically partition into SPLD-like units.