ECE124

Digital Circuits and Systems

Prof. C. Gebotys

Final Exams Review

Spring 2011
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
 ECE124 Digital Circuits and Systems, Final Review, Spring 2011

[Q1] For the following clocked sequential circuit with one input (X) and one output (Z):

1. Drive a state table and draw a state diagram for the circuit.
2. Redesign this circuit by replacing the Q1 flip-flop (i.e. the D flip-flop holding Q1 state) with a JK flip-
flop, and the Q2 flip-flop with a T flip-flop. Only show the excitation equations (or state equations) for
J1, K1, and T2.

[Q2] Draw the state diagram for the table below that describes a finite-state machine which has one input x and
one output z.
Present Next State Output (z)
State x=0 x=1 x=0 x=1
A A E 1 0
B C F 0 0
C B H 0 1
D E F 0 0
E D A 0 1
F B F 1 1
G D H 0 1
H H G 1 0

[Q3] Consider the following state diagram for a synchronous circuit with one input X and one output Z. Analyze
this state diagram and draw its circuit implementation using JK flip-flop (state Q0) and T flip-flop (state Q1) and
MUX-4x1 for Z.

[Q4] Draw a circuit diagram for non-overlapped ‘101’ detector with “D” flip-flops as a Mealy and Moore machine.

[Q5] Given a 32x8 ROM chip with an enable input, show the block level required connections to construct a 128x8
ROM with above ROM chips and a decoder. How many data and address lines these ROMs have?

[Q6] Implement the circuit defined by equation F(a,b,c,d) = ∑ (0,5,6,7,11) using:

1. 4-to-1 multiplexers and logic gates.

2. 2-to-4 decoders with non-inverted outputs and logic gates.

Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
 ECE124 Digital Circuits and Systems, Final Review, Spring 2011

[Q7] Use a 3-bit binary counter with active-high load (L) and Increment (I) control inputs (load has higher priority
than increment) and implement a circuit (draw) to generate and repeat the following sequence at the output of the
counter. Initial counter value is “000”.

——— → 000 → 001 → 010 → 101 → 110 → 111 → 000 → ———

[Q8] Design a digital circuit that takes two 4-bit numbers A and B as input and generates output Z as follows:

• If A and B are odd numbers then Z=A-B

• If A and B are even numbers then Z=B-A
• If A is an even number and B is an odd number then Z=A+B
• If A is an odd number and B is an even number then Z=A-B-1

Assume that you have access to as many as you need of AND, OR, INV, XOR gates and only one FULL-ADDER,
DECODER and MULTIPLEXER of any size.

[Q9] For the following Programmable Logic Array (PLA), find the function expressions for all outputs and draw the
Karnaugh-Map for function "F".

[Q10] What are three different ways of representing a signed number? Assume 7 bit numbers and represent (-15)
in each of them, then find (B-A) and (A-C) for A = 1101010, B = 0110101 and C = 0010101 in all forms.

[Q11] Find:

a) The 7’s complement of base-8 number “45201”

b) Multiplication of base-12 numbers “541” and “3”
c) Base-10 unsigned number “214.45” to its base-2 representation
d) Base-6 number “513” to its base-10 and then base-5 representations
e) Hexadecimal number “AF6” to its base-2 and base-8 representations

Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
 ECE124 Digital Circuits and Systems, Final Review, Spring 2011

[Q12] For the following asynchronous sequential state table, find all possible critical/non-critical races and cycles
for states “a” and “c”.

Present Next State

State 00 01 11 10
a 00 00 11 01 11
b 01 11 01 01 10
c 11 10 11 01 10
d 10 11 10 01 10

[Q13] A crypto module which transforms a secret key bit stream, K, into two other bit streams, X and Y has to be
designed. This module must be designed as an asynchronous sequential Mealy state machine. It works as
follows: if the secret key bit stream contains ‘011’, then it’s replaced with ‘10(-1)’. This transformation reduces the
number of ‘1’ bits in the key (which has significant impact on subsequent processing times in elliptic curve
algorithms). However since we cannot represent 0, 1 and -1 with a one bit output, we use two output signals, X
and Y. Whenever a m-bit sequence of 1’s is detected (where m>1), X is set to 1 for the first K=‘1’ in the sequence
and when a K=‘0’ is detected after the mth ‘1’ bit both X and Y are set to ‘1’. Construct a sequential state table for
this module.

K:000100011011110001101000
X:000100010110001001011000
Y:000000000100001000010000

[Q14] For below sequential state table, perform a race-free state assignment and complete the entire state table:

Present Next State Output

State 00 01 11 10 00 01 11 10
a a a b d 0 1 - -
b a b b c - 0 1 -
c a - d c - - - 0
d a a d d - - 1 0

Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
 ECE124 Digital Circuits and Systerns, Final R.eview, Spring Z0ll

[Q1]Forthefollowing clocked sequential circuitwith one input (X)and one output (Z):

1. Drive a state table and draw a state diagram for the circuit.
2. Redesign this circuit by replacing the Qr flip-flop (i.e. the D flip-flop holding Q1 state) with a JK flip-
flop, and the Qz flip-flop with a T flip-flop. Only show ihe excitation equations (or state equations) for
J1, K1, and T2.

;i =, Xdd,y
14.
,{&l x&fx[i; &, ',.
-J il 'iil
n \-{j-* ('.
*.;
i r '")

il

af* xru* +xte[ f-. :F

*
1r I '-,*
\v2 -d*- :i {,;t-}
6rQs
/0
\-\
PS IN
Al
NS OUT
r'*u4 x,7
(r)r0
',clicl X a;ae z QtrQg
00 0 00 0
00 1 11 0
01 U 00 0
0'1 1 00 0 $)
10 0 00 0 N\ lA
E+A
-"

10 10
,{}
1 +.1

11
11
0
1
00
10
0
I 4/ /-- )
h$
t

-_:-n '$)
f Jr = -: r 'l * x Qr +Y(2
.l

\ Tg= )s@Qs= xoia; o Qz

D

Qr* tr &U&r+r<'R EL T#Q

D*Ftr )R*tr T-FF
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 ECE124lligital Circuits and Systems, Final Review, Spring 2011

[Q2] Draw the state diagram for the table below that describes a finite-state machine which has one input x and
one output z.

,:7,:rll]g) tt;!--*{
t(:'|*:::tv xiF$ .!$**as
A E 't U
:,:::iB,:::::,,:.,,:,::
C F 0 0
B H 0 1

,rlt.$t,l E F 0 0
:i.::ffiEl ri;11; D A 0 1
::::l:;YFl,:::
B F 1 1

:rlG:i:19,; D H 0 1

Fl,, H G 1 0

''flr,
l\,r' tr,
\\
.-ffitr'tr
'l^ ,^d-
Ll )"

\J1/n
* Ja
n LJ
L,/L;)

A/t*$ ilrcgrafr

fi- { (c"srx)

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 ECE124 Digital Circuits and Systems, Final Review, $pring 2011

[Q3] Consider the following state diagram for a circuit with one input X and one output Z. Analyze this state
diagram and draw its circuit implementation using JK flip-flop (state Q0) and T flip-flop (state Q1) and MUX-4x1
for Z.

f't--'-
{1,'0

1'ff
I (i
" -. 10[]
--
;
t\ '-. ,lK sR * rfl^ .*5R

DT 44F \

]om m w l4*
1

&n
,--| --l'!- ..,_\_,1
\',0
a0 0 Qr 16,'- rr1,--
\., J
ll
\.
\..,-.-,. <
I ro
I
\. /\.,.1...
I
0t &t ]6 I
tf I c; or -' l

t$ t8 l{ I

tr&.T r[=
PS
QrQo
00
IN
X
0
QrQo
NS

00
OUT
z
0
.iK-F{:

0
I g\R

X
Y"FT
)y

0
fl u \c-
00 01 0 X il
5R. FF
1

K&
charadrrffitt tabkJ 0'1

01
0 11
01
0
0
0
0 0
rlmruff*#k tahb:
1

10 0 00 0 0 X
10 1 01 0
11 U 00 0 X 1 I

1.1
'1
0'l 1 X 0 1

00 01 .11 10 00 01 11 10
0 0 X X U 0 X 0
1 X 0 0 X

J0: X Ko- 9,Xt

00 01 11 10
t€l
v ft
0
1
0
tt 0 il r[F r lqs
rt , Qn *{rXt ax( itttlinn f(th[w

00 01, 11 10
fi
QQ' JK 5K OT
-+-

]0
1
0
0
0
0
0
1
0
0
v./
r
w w 0x 6x &ffi
F(il. 0 0 X 0
X ffit tx t& ll
Z=X
(fr{o W xl @t 0f
il xQ x8 l8
Should you have any questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
 EcEl?4 Digltal circuits and systems, Final Review, spring z0L1

[Q4] Draw a logic diagram for non-overlapped '101'detector (Moore machine) with D-type flip{lops.

N,,9C

I
'18', & '(&lorl

7
h D2
PS IN \Nsrr OUT
/:P '|cf 9rQi x 9r'Q z
0uf r= (ruS; 00 U 00 0
rtfiL
Joon*, 00
01
01
1

0
01
10
0
tl
n
7* I Merlre1i)

orJT;= { G-SrlruJ
1 01

1*gl
10
10
0
1
00
11
0
1
1q, {r" 1's1s;,ffyiu
11 0 00 0
11 1 01 U
'i it't. ,

l1

00 01 11 10 00 01 11 i0
0 0 {1) 0 0 0 0 0 0 0
''L 1 n n n fi) 1 -lJ

Jl= q,u; ,x.Q{q*M$; u*=Qt'* x

,lr,l
t. ,..r,0,

tlx,'!it,y l,-t" '

,*i. , '\,*_*
N.= @etco!9t-e I ttil{gla
I

( Xt=eMe@MlN60tffi
)
? d.= @ffeoeffilhfuo0Wfu0
".,:,
1y,"1''1L'.;

Ds Qp
Jl-f I f LfL
nl
t{e

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 ECEIZI|. Digital Circuits and Systems, Final Review, $prlng 201L

showthe block level required connectionsto construct a 128x8

[Q5]Given a 32xg ROM chip with an enable input, lines these ROMs have?
hoV witfr ROM chips and a decoder. How many data and address

, 1lv',g::aia$,r.Ld,e'o t',;ir,-./{,

707
fr rr i
t=N Eit 0

R}Alt t28x8 . { - ,tlr / +,L

[:
1..11 ,l> I t:tV,; I r- 1-.ill '-i{)
,t

fla
wvlfl8 x
Rdvl2I xl"lO
o Nu'6
I
,1
)

(I

'31
(."f uMrxbful
*i>rze x @.{'bh hk)
76' -"- t I Ro/vt
= 2
[!a'x
:L nD h6
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 ECE124 Digital Circuits and Systernsn Final Review, $pring 2011

[Q6] lmplement the circuit defined by equation F(a,b,c,d) = I (0,5,6,7,11) using:

1. 4{o-'1 multiplexers and logic gates.

2. 2to-4 decoders with non-inverted outputs and logic gates.

:..Jlli.ir: :rati:fr:bl .el:;,l'.d Sr

rn= { tc,d)
0 00 00 \J
T 00 01 t L}

2 00 10 s Io
3
4
00
01
11
00 {\s 1
;1
I c,dt qM

5 01
6 01
01 \v \
10 (1) c-f d
I 0t
1 01
I 10
11 F}
00
f Ia.
9 10 01 i"! *cd Tb
10 IU 10
11 10 1'l t!t! ffi lt
12 11 00 * I F€

13 11 01 i\ \ -4*-'--
14 11 10 $
15 1'1 '1 1

trGtb,cds : o'%;d iaff{d +u'k:d'" o'|;C # W'C

LIJ

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 ECEl2rl Digital Circuits and Systems, Final Review, Spring 2011

(L) and lncrement (l) control inputs (load has higher priority
[e7] Use a 3-bit binary counter with active-high load
ihun in"r"r"nt) and implement a circuit (drawJ to generate and repeat the following sequence at the output of the
aar rn*nr lnilicl
counter. lnitial nnr rntor rraltro
counter value ic "000".
is "OOO" qg-qu.T
^ -+
, +.
...-oo0*io"'i010-101
,OO0-001 -000-"'..
-110--1'11 -000-"'-* Afztd
I I II &L
-010*101 -110-111 LI
,Iittflu, cl,wfafuShCffi
*r',
p$ l,fs, {^,fri,tafa(*yuT
ffiu\ { H*'
lxl P
qfl&q#il Lr PrfrPa @nbp

004 sao a I xxx TL

@0t bto @ I xxx
Al0 tat I X I8I PA ea
10, u@ g I xxx c{ dr
n@ ln 0 I xxx &ao
lllo@ a t xxx

I) OII XXX K X XXX

unu]/cJ l@@ Xxx X X XXX'
*d* (

L = qLT, T=1

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 ECE124 Digital Circuits and Systerns, Final Review, $pring 2011

generates output Z as follows:

[e8] Design a digital circuit that takes two 4-bit numbers A and B as input and
. lf A and B are odd numbers then Z=A-B
. lf A and B are even numbers then Z=B-A
. lf A is an even number and B is an odd number then Z=A+B
. lf A is an odd number and B is an even number then Z=A-B-1

Assume that you have access to as many as you need of AND, OR, lNV, XOR gates and FULL-ADDER,
DECODER and MULTIPLEXER of any size.

CIid -[unCior :-antrcl ,

Z L*"rrnnqJilJi

{frs 0a B*fr ,*R BI Qn = ftfuapYYt3

lllt 0t ft+B ft B(0 L r
,''8 6 Cga= Wg
ut'w.,ii{ (r rkttL'
f'ns t0 ft-iP,"-' {4 I Q *l,it
m3 il A*B ft e6.- rTlgtffiS {y ) ' i,,r,,rl'

As
bo

cx
w*ws
Xs Xo

X1 Xl

Kz X2
."-
& Xs

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 ECE124 Digital Circuits and Systems, Final Review, Spring ZOL,-

programmable Logic Array (PLA), find the function expressions for all outputs and draw the
[e9] For the following
Karnaugh-Maps for function "F".

a n'*d cd

fr'6c
G.- ft/B'-r ftB!C'+&!6'+
H = fr18+8c+6C'
ts
-,--t-.2\----S

o{ rt t0

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 ECE124 Digital circuits and Systerns, Final Review, $pring 2011

number? Assume 7 bit numbers and represent (-15)

[al o] What are three different ways of representing a signed inallforrns"
in"ub6of them,thenfind(B-A) and(A-cjforA=1i01010,8=0110'101 andc=0010101
*trs

I
IWIIU
NIWffi
lttM
1 : -1-
f'r4,.i, ,r:tr,, l; I .: .l-i?16^f,rtt";''i{
|i{:. t,ori',
,/{ ,i
6'lr,*u;,,1"

11+ @ n @[01 ffitetEl 0,t ffitCIl

*fr 0t6l@t& & l0l 0m@tt@

^ffi(
nat slffi ll
'.' l',{t*il,O I illl t
{*i L *tgot@
i., I ,",
oveP'{16'\) uirr;t*
{1r I tTtat @ l16l0l0 t t@t&10

.* i- "
l0lm0l tl$ I@ l@ It0t0ll
tll@ .tl
4-lerr I
(rl t o t@tCIt
fi
'-"
r"':tr:Wtt
i ,a,{i ,'tff{li[J v!
| " ..
t_lrt:j
1

l:1i i fl .,i, l/, J

il:+trt;'i
'I {'{
a,l .?
,,,{ , Jl
tTtfrt tryt ,J

Should yo, har€ .ny questions on this review, please contact Arash. [aTabibiazar@uwaterloo.ca]
 ECELz4 Sigital circuits and Systerns, Final Review, spring 2911

[Q11] Find:

a) The 7's complement of base-8 number "45201"

b) Multiplication of base-12 numbers "541" and "3"
.j Base-10 unsigned number "214.45" to its base-2 representation
d) Base-6 number "513" to its base-10 and then base-S representations
Hexadecimal number "AF6" to its base-2 and base-8 representations
"l
I

a) *71+T+ bl x 5ql
qSLot L,r'

jg7+6 tq 03

c), uq"q5 G
-m \
@\ sb) )a'9+0{r'iib)
WT+AQ Or2
+( 53fl ^29 aff +l dl$r3)5 =3x6 + tx6'15x6
/'240.6 +l
ir( L6 +l Y'2uo'2+r \
R
= tKQ

;L{
t3 +@
-'l 3r +tt Wb;
.^{

^21a"4+@ lnt
+r-(
6 +l ^2 u @-t +@/
' \ + +9-
,a /
-) I

,s( 3+@ r\
-_/
'(-

I +2
I

:2( f +f is( o +t on*)

(
-.2-
.V
0 +t@sb|
- (tn-zuS =
e) nF6= wl@ tfil0tlCI \_-'r\.--. *z
'v-

btqqil{ (wntw'CI{ttro)t 53 6 6
(rssa)r
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 gcg124 sigital circuits and Systems, Final R.eview, Spring 2911

state table, find all possible critical/non-critical races and cycles

[a12] For the following asynchronous sequential
for states "a" and "c".

nndawntLt( tUde
Pres6ht Ndxt State
,Stat6' 00 01 11 1.0
a .'00 00] 11 01 11

rb'., .r,ri:01r, :
11 01 01 10
C.: ':l 1 10 tr 01 10
d 10 11 10 01 10
,t
t, t I
)t{l,t 'f{^, I
:,f11 &.
"

6i '-*&l -.t.
.' ir{^*;lC
$,.q 2

o,l

ffil *#*@
tO ----*@)
ffi+t8
Q2
tt --*= t@-+6,9
t@4@

cr @YJ-Yot -*4*@
6S*-*tr1
ol
Qs @*-->

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 ECE124 Digital circuits and Systerns, Final Review, Spring 2011

a secret key bit stream, K, into two other bit streams, X and Y has to be
[O13] Acrypto module which transforms lt works as follows: i{
iesiinea. This module must be designed as a synchronous sequential Mealy state machine.
the secret key bit stream contains'0J1" then it's replaced with
'i0(-1)'. This transform.ation reduces the number of
,1,bits in the key (wfrilfr has significant impact on subsequent processing times in elliptic curue algorithms).
However since we cannot repreient 0, 1 and -1 with a one bit output, we
use two output signals, X and Y'
Whenever a m-bit sequence of 1's is detected (where m>1), X is set to 1 for the first K='f in the sequence and
Y are set to '1'. Construct a flow table for this module.
when a K=,0' is oetected atter1t," rt6 '1' bit both X and

K : 000100011011110001101000
X : 000100010110001001011000

b,,h6
*'*
Y : 000000000100001000010000

0 +l
+
-f
Irffi

,;P

0/tl
{lri
,,'-KrxY\
ilv
XY {,i"J f

00
0a
@@

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 ECE1?4 Digital circuits and systems, Final Review, spring 2011

perform a race-free state assignment and complete the entire state table:
[e14] For below Mealy flow table,

Pfesertt, Next State *wtxrts{

,,,Steitg.,. '' ,r00 01',, 11 101 *ffi r*l$ tt x,{3

b d 0 j &
O,;':: @r 6)q
b a fr) c D 0 1 $f,
c by d @ 0t, 0
d a a 6, I 1 CI

|; to pflwff stst?b-r nond

avTtc tr*ief*'tPif
I 0, to'P,qC
Pl* ' t# /t: l'l r-r,'l-i
$0

.; *

{* @* @ lransficn lf
rxdz, Fr* Ta fransft c -*P h -P a'

4b: @J:'ffi-
c @ 2b:@?t*'t*b-u6)
o-il$, I* | -* o

v ,90
Na h&vetr*niref to avoid t"rrrsafffi
frw W. 5:{f o CIr' { 61A d,ss ]FTW 1
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