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  • Vlsi Lab Outputs

    Uploaded by

    Uma Sankar
    5 views21 pages
    The document contains simulation results from four different schematic circuits - a CMOS inverter, half adder, operational amplifier symbol, and AND gate. The results include transient response graphs showing how the output voltages change over time in response to changes in input voltages, as well as DC response graphs showing the static input-output voltage relationships.

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    Original Title

    VLSI LAB OUTPUTS

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    The document contains simulation results from four different schematic circuits - a CMOS inverter, half adder, operational amplifier symbol, and AND gate. The results include transient response graphs showing how the output voltages change over time in response to changes in input voltages, as well as DC response graphs showing the static input-output voltage relationships.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    5 views21 pages

    Vlsi Lab Outputs

    Uploaded by

    Uma Sankar
    The document contains simulation results from four different schematic circuits - a CMOS inverter, half adder, operational amplifier symbol, and AND gate. The results include transient response graphs showing how the output voltages change over time in response to changes in input voltages, as well as DC response graphs showing the static input-output voltage relationships.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 21

    gpdk180 cmos_inverter1 schematic 12:23:54 Thu Sep 22 2022

    Transient Response Thu Sep 1 11:10:41 2022


    Name Vis

    /V_OUT 1.9

    1.7

    1.5

    1.3

    1.1
    V (V)

    0.9

    0.7

    0.5

    0.3

    0.1

    -0.1
    /V_IN 1.9

    1.7

    1.5

    1.3

    1.1
    V (V)

    0.9

    0.7

    0.5

    0.3

    0.1

    -0.1

    0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100
    time (ns)

    Printed on Page 1 of 2
    by student
    gpdk180 cmos_inverter1 schematic 12:23:54 Thu Sep 22 2022

    DC Response Thu Sep 1 11:10:41 2022


    Name Vis

    /V_IN 1.9

    1.7

    1.5

    1.3

    1.1
    V (V)

    0.9

    0.7

    0.5

    0.3

    0.1

    -0.1
    /V_OUT 1.9

    1.7

    1.5

    1.3

    1.1
    V (V)

    0.9

    0.7

    0.5

    0.3

    0.1

    -0.1

    0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
    dc (V)

    Printed on Page 2 of 2
    by student
    gpdk180 Tgates_half_adder schematic 11:26:19 Thu Sep 22 2022

    Transient Response Thu Sep 22 11:18:06 2022


    Name Vis

    /Carry 1.9

    1.5

    V (V) 1.1

    0.7

    0.3

    -0.1
    /Sum 1.9

    1.5

    1.1
    V (V)

    0.7

    0.3

    -0.1
    /B 1.9

    1.5

    1.1
    V (V)

    0.7

    0.3

    -0.1
    /A 1.9

    1.5

    1.1
    V (V)

    0.7

    0.3

    -0.1

    0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100
    time (ns)

    Printed on Page 1 of 1
    by student
    gpdk180 CS_R_AMP_SYMBOL schematic 11:35:38 Thu Oct 13 2022

    Transient Response Thu Oct 13 11:31:47 2022


    Name Vis

    /net2 1.8

    1.6

    1.4

    1.2

    1.0

    0.8
    V (V)

    0.6

    0.4

    0.2

    0.0

    -0.2

    -0.4
    /v_out 5.1

    5.0

    4.9

    4.8

    4.7

    4.6

    4.5

    4.4
    V (V)

    4.3

    4.2

    4.1

    4.0

    3.9

    3.8

    3.7

    3.6

    0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0
    time (ns)

    Printed on Page 1 of 1
    by student
    gpdk180 pass_AND_1 schematic 10:30:57 Thu Sep 22 2022

    Transient Response Thu Sep 22 10:24:48 2022


    Name Vis

    /V_OUT 1.3

    1.1

    0.9
    V (V) 0.7

    0.5

    0.3

    0.1

    -0.1
    /SUM 1.3

    1.1

    0.9

    0.7
    V (V)

    0.5

    0.3

    0.1

    -0.1
    /B 1.9

    1.5

    1.1
    V (V)

    0.7

    0.3

    -0.1
    /A 1.9

    1.5

    1.1
    V (V)

    0.7

    0.3

    -0.1

    0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100
    time (ns)

    Printed on Page 1 of 1
    by student

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