Basic Electronic Circuits

K.
Vasudevan
Basic Electronic
Circuits
Problems and Solutions
Basic Electronic Circuits
K. Vasudevan
Basic Electronic Circuits

Problems and Solutions
K. Vasudevan
Department of Electrical Engineering
Indian Institute of Technology Kanpur
Kanpur, India
ISBN 978-3-031-09362-3 ISBN 978-3-031-09363-0 (eBook)

https://doi.org/10.1007/978-3-031-09363-0
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To my family
Preface
Basic Electronic Circuits: Problems & Solutions covers a large variety of topics that are
taught to first and second year undergraduates. The book is richly illustrated with figures
and easy to read. It is a good supplement for many standard texts on electrical circuits
and basic electronics. This book has evolved out of the tutorials conducted for the course
Introduction to Electronics, at IIT Kanpur.
Chapter 1 covers dc circuits. The DC R L and RC transients are presented in Chap. 2.
The steady-state analysis of AC circuits is covered in Chap. 3. Two-port networks, reso-
nance and Bode plots are discussed in Chap. 4. Chapter 5 deals with the analysis of diode
circuits. Problems on Bipolar Junction Transistors (BJTs) are given in Chap. 6. Op amp
circuits are discussed in Chap. 7. Combinational and sequential circuits are presented in
Chaps. 8 and 9, respectively.
I would like to express my gratitude to some of my instructors at IIT Kharagpur
(where I had completed my undergraduate)—Dr. S. L. Maskara (Emeritus faculty), Dr. T.
S. Lamba (Emeritus faculty), Dr. R. V. Rajkumar and Dr. S. Shanmugavel, Dr. D. Dutta
and Dr. C. K. Maiti.
During the early stages of my career (1991–1992), I was associated with the CAD-
VLSI Group, Indian Telephone Industries Ltd., at Bangalore. I would like to express my
gratitude to Mr. K. S. Raghunathan (formerly a Deputy Chief Engineer at the CAD-VLSI
Group), for his supervision of the implementation of a statistical fault analyzer for digital
circuits. It was from him that I learnt the concepts of good programming, which I cherish
and use to this day.
During the course of my master’s degree and Ph.D. at IIT Madras, I had the oppor-
tunity to learn the fundamental concepts of digital communications from my instructors,
Dr. V. G. K. Murthy, Dr. V. V. Rao, Dr. K. Radhakrishna Rao, Dr. Bhaskar Ramamurthi
and Dr. Ashok Jhunjhunwalla. It is a pleasure to acknowledge their teaching. I also grate-
fully acknowledge the guidance of Dr. K. Giridhar and Dr. Bhaskar Ramamurthi who
were jointly my Doctoral supervisors. I also wish to thank Dr. Devendra Jalihal for intro-
ducing me to the LATEX document processing system without which this book would not
have been complete.
vii
viii Preface
Special mention is also due to Dr. Bixio Rimoldi of the Mobile Communications Lab,
EPFL Switzerland and Dr. Raymond Knopp, now with Institute Eurecom, Sophia Antipo-
lis France, for providing me the opportunity to implement some of the signal processing
algorithms in real time, for their software radio platform.
I would like to thank many of my students for their valuable feedback. I thank my col-
leagues at IIT Kanpur, in particular Dr. S. C. Srivastava, Dr. V. Sinha (Emeritus faculty),
Dr. Govind Sharma, Dr. Pradip Sircar, Dr. R. K. Bansal, Dr. K. S. Venkatesh, Dr. Adrish
Banerjee, Dr. A. K. Chaturvedi, Dr. Y. N. Singh, Dr. Ketan Rajawat, Dr. Abhishek Gupta
and Dr. Rohit Budhiraja for their support and encouragement.
I would also like to thank the following people for encouraging me to write this book:
• Dr. Surendra Prasad, IIT Delhi, India

• Dr. P. Y. Kam, NUS Singapore
• Dr. John M Cioffi, Emeritus faculty, Stanford University, USA
• Dr. Lazos Hanzo, University of Southampton, UK
• Dr. Prakash Narayan, University of Maryland, College Park, USA
• Dr. P. P. Vaidyanathan, Caltech, USA
• Dr. Vincent Poor, Princeton, USA
• Dr. W. C. Lindsey, University of Southern California, USA
• Dr. Bella Bose, Oregon State University, USA
• Dr. S. Pal, former President IETE, India
• Dr. G. Panda, IIT Bhubaneswar, India
• Dr. Arne Svensson, Chalmers University of Technology, Sweden
• Dr. Lev B. Levitin, Boston University, USA
• Dr. Lillikutty Jacob, NIT Calicut, India
• Dr. Khoa N. Le, University of Western Sydney, Australia
• Dr. Hamid Jafarkhani, University of California Irvine, USA
• Dr. Aarne Mämmelä, VTT Technical Research Centre, Finland
• Dr. Behnaam Aazhang, Rice University, USA
• Dr. Thomas Kailath, Emeritus faculty, Stanford University, USA
• Dr. Stephen Boyd, Stanford University, USA
• Dr. Rama Chellappa, University of Maryland, College Park, USA
Thanks are also due to the open source community for providing operating systems like
Linux and software like Scilab, LATEX, Xfig and Gnuplot, without which this book would
not have been complete. I also wish to thank the publisher, Mr. Jai Raj Kapoor and his
team for their skill and dedication in bringing out this book.
Preface ix
In spite of my best efforts, some errors might have gone unnoticed. Suggestions for
improving the book are welcome.
Kanpur, India K. Vasudevan

Contents
1 DC Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 RL and RC Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3 AC Circuits—Steady-State Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4 Resonance, Bode Plots and Two-Port Networks . . . . . . . . . . . . . . . . . . . . . . . . . 111
5 Diode Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6 Bipolar Junction Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7 Op Amp Circuits and Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8 Combinational Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9 Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Appendix: Two-Port Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
xi
About the Author
K. Vasudevan completed his Bachelor of Technology (Honours) from the department of

Electronics and Electrical Communication Engineering, IIT Kharagpur, India, in 1991,
and his M.S. and Ph.D. from the department of Electrical Engineering, IIT Madras, in
1996 and 2000, respectively. During 1991–1992, he was employed with Indian Telephone
Industries Ltd, Bangalore, India. He was a Post Doctoral Fellow at the Mobile Commu-
nications Lab, EPFL, Switzerland, between December 1999 and December 2000, and an
engineer at Texas Instruments, Bangalore, between January 2001 and June 2001. Since
July 2001, he has been a faculty at the Electrical Department at IIT Kanpur, where he is
now a Professor. His interests lie in the area of communication.
xiii
Notation
I Real-valued, constant current

V Real-valued, constant voltage
R Resistance
i, i(t) Real-valued, time varying current
v, v(t) Real-valued, time varying voltage
−
→
I Phasor current (complex quantity)
−
→
V Phasor voltage (complex quantity)
−
→
Z Phasor impedance (complex quantity)
−
→
Y Phasor admittance (complex quantity)
a∧b Logical AND of a and b
a∨b Logical OR of a and b
x Largest integer less than or equal to x
x Smallest integer greater than or equal to x
√
j −1
Equal to by definition
Convolution
[x1 , x2 ] Closed interval, inclusive of x 1 and x 2
[x1 , x2 ) Open interval, inclusive of x 1 and exclusive of x 2
(x1 , x2 ) Open interval, exclusive of x 1 and x 2
Hz Frequency in Hertz
wrt With respect to
xv
Symbols
+
Battery
−
Constant independent voltage source
Constant independent current source
Sinusoidal or time-varying independent voltage source.

− The instantaneous polarity of the voltage is shown
Sinusoidal or time-varying independent current source.

The instantaneous direction of the current is shown
+
Constant or time-varying dependent voltage source

−
Constant or time-varying dependent current source
Basic Electronics: Problems and Solutions
Non-polar capacitor
xvii
xviii Symbols
Electrolytic or polar capacitor

−
Resistor
Potentiometer or variable resistor
Inductor
Ground
Diode
Zener diode
An npn bipolar junction transistor
A pnp bipolar junction transistor
−
Op amp
+
2-input AND
2-input OR
NOT or inverter
2-input NAND
2-input NOR
2-input XOR
DC Circuit Analysis
1
1. In Fig. 1.1, find I1 , I2 and V1 .
– Solution: Refer to Fig. 1.1. Assuming that a voltage drop is negative and a voltage
rise is positive, we have
I2 − I1 = 3Vx
Vx = 3I2
12 − I1 − 4(I1 − I2 ) + V1 = 0
−5I2 − V1 − 4(I2 − I1 ) = 0 (1.1)
where we have used Kirchoff’s voltage law in the two loops indicated in Fig. 1.1.
After simplification, we get
V1 + 44I2 + 12 = 0
V1 + 41I2 = 0. (1.2)
Solving (1.2), we get
I1 = 32 A
I2 = −4 A
V1 = 164 V. (1.3)
2. In Fig. 1.2, find I1 , I2 and the voltage across the independent current source.
© The Author(s) 2023 1

K. Vasudevan, Basic Electronic Circuits,
https://doi.org/10.1007/978-3-031-09363-0_1
2 1 DC Circuit Analysis
Fig. 1.1 A circuit 1Ω
4Ω 2Ω
12 V
+ − +
I1 I2
−
3Ω
V1 Vx
3 Vx A +
−
2Ω 4Ω
−
+ +
10 A
I1 I2
V1
1Ω
+ Vx
2Vx V
− −
I1 = 10 A
Vx = I2
2Vx − 2(I2 − I1 ) − 5I2 = 0. (1.4)
I2 = 4 A
Vx = 4 V. (1.5)
Also
− V1 − 3I1 − 2(I1 − I2 ) − 2Vx = 0

⇒ V1 = −50V . (1.6)
3. In Fig. 1.3, find I1 , I2 and I3 using mesh analysis (KVL). Also, find V1 and the power
dissipated in the 3 A current source.
1 DC Circuit Analysis 3
2A
5Ω
I3
3Ω
+ 4Ω
10 V
I1 2Ω I2 3Ω
1Ω
V1 3A
−
Fig. 1.3 A circuit
I3 = −2 A
I1 − I2 = 3 A
−10 − 2 × 3 − V1 − I1 − 3(I1 − I3 ) = 0
−3I2 + V1 + 2 × 3 + 10 − 4(I2 − I3 ) = 0. (1.7)
I1 = 7/11 A
I2 = −26/11 A
V1 = −270/11. (1.8)
The power dissipated in the 3 A current source is
3V1 = −810/11 watts. (1.9)
4. In Fig. 1.4, find the voltages at nodes a and b using nodal analysis (Kirchoff’s current
law (KCL)). Assume voltage at node c is Vc = 0. Also, find V1 and the power supplied
by the 6 A current source.
– Solution: Refer to Fig. 1.4. Note that Vd = 4 V. At node b, we have

Vb − 4 Vb
+ +6 = 0
4 1
⇒ Vb = −4 V. (1.10)
4V
−
b
d c
4Ω
+ 1Ω
3V
5Ω 6Ω
2Ω
V1 6A
−
Fig. 1.4 A circuit
At node a
Va − 4 Va
+ =6
2 6
⇒ Va = 12 V. (1.11)
Moreover, assuming voltage drop is negative and voltage rise is positive
Vb − 3 − 5 × 6 − V1 = Va
⇒ V1 = −49 V. (1.12)
Therefore, the power supplied by the 6 A current source is 49 × 6 = 294 W.
5. In Fig. 1.5, write down the KVL equation for the supermesh cde f c. Hence, find the
currents I1 , I2 and I3 using mesh analysis.
Using the mesh currents computed above, find the voltages at nodes b and d. Assume
voltage at node c is Vc = 0.
– Solution: Refer to Fig. 1.5. The “voltage source” can be replaced by a 10 V ideal
source (positive terminal pointing upwards) in series with a 5 resistor. Note that:
1Ω a
e
I
+
a
3Ω I2 3Ix V voltage
source
voltage
−
source d b
I1 f
b
Ix Vab = Va − Vb (volt)
2A
10
4A
I3
4Ω 6Ω
I (amp)
c 2
Fig. 1.5 A circuit
I1 = 4 A
I x = I3
I2 − I3 = 2 A. (1.13)
The KVL equation for the supermesh cde f c is
− 4(I3 − I1 ) − 3(I2 − I1 ) − 3I x − 6I3 = 0. (1.14)
From (1.13) and (1.14), we get
I2 = 54/16
I3 = 22/16. (1.15)
The KVL for mesh 1 is
Vb + 10 − 4(5 + 1) − 3(I1 − I2 ) − 4(I1 − I3 ) = 0

⇒ Vb = 211/8. (1.16)
Finally
Vd = 4(I1 − I3 )
= 21/2 V. (1.17)
6. In Fig. 1.6, write down the KCL equation for the supernode consisting of nodes d, f
and the 6 V independent voltage source. Hence, find the node voltages at c, d and f
using nodal analysis.
Using the node voltages computed above, find the mesh currents I1 and I2 . Assume
voltage at node e is Ve = 0.
a
5Ω I
c
current
a I2
2Ω 4Ix A source
current b
source d + −
I1 f
Vab = Va − Vb (volt)
b
− 6V
6
Ix
4V I (amp)
+ 3Ω 1Ω
2
e
Fig. 1.6 A circuit
– Solution: Refer to Fig. 1.6. The “current source” can be replaced by a 6 V source
(positive terminal pointing upwards) in series with a 3 resistor. Moreover
I x = Vd /3
Vd − V f = 6 V. (1.18)
Applying KCL to the supernode d, f and the 6 V source, we obtain
Vd − Vc Vd Vf
+ + = 4I x
2 3 1
Vd − Vc Vd 4Vd
⇒ + + Vf = . (1.19)
2 3 3
Applying KCL at node c, we have
Vc − 2 Vc − Vd
+ + 4I x = 0
8 2
Vc − 2 Vc − Vd 4Vd
⇒ + + = 0. (1.20)
8 2 3
From (1.18), (1.19) and (1.20), we get
Vd = 186/35 V
Vc = −234/35. (1.21)
The mesh currents can be computed as follows:

Vc − 2
I1 = − = 1.0857 A
8
I2 = 4I x = 4Vd /3 = 7.0857 A. (1.22)
Fig. 1.7 A circuit IB
+
VL
Linear IL
VA network RL
−
−
7. In Fig. 1.7, when V A = 2 V and I B = 3 A, I L = 6 A. Similarly, when V A = 1 V and

I B = 5 A, I L = 4 A. Find I L when V A = 3 V and I B = 4 A.
It is given that the voltage across R L (VL ) and the current through R L (I L ) do not control
any dependent source in the linear network. There are also no independent sources,
other than V A and I B , in Fig. 1.7.
– Solution: Due to linearity and superposition we have
K1 VA + K2 I B = IL (1.23)
where K 1 and K 2 are constants to be found out. Using the given parameters, we get
2K 1 + 3K 2 = 5
K 1 + 5K 2 = 6. (1.24)
Solving we get K 1 = 18/7 and K 2 = 2/7. When V A = 3 V and I B = 4 A, we

get I L = 62/7 A.
8. In Fig. 1.8, when V A = 3 V and I B = 5 A, VL = 4 V. Similarly, when V A = 2 V and

I B = 7 A, VL = 8 V. Find VL when V A = 3 V and I B = 4 A.
It is given that the voltage across R L (VL ) and the current through R L (I L ) do not
control any dependent source in the linear network. There are also no independent
sources, other than V A and I B , in Fig. 1.8.
– Solution: Due to linearity and superposition, we have
K1 VA + K2 I B = IL (1.25)
where K 1 and K 2 are constants to be found out. Using the given parameters, we get
IB
+
VL
Linear IL
VA network RL
−
−
Fig. 1.8 A circuit
3K 1 + 5K 2 = 4
2K 1 + 7K 2 = 8. (1.26)
Solving we get K 1 = −12/11 and K 2 = 16/11 . When V A = 3 V and I B = 4 A,

we get VL = 18/11 V.
9. In Fig. 1.9, find the Thevenin equivalent across terminal X Y , as seen by R L , using
superposition (considering one independent source at a time). For each independent
source, verify that the Thevenin resistance across X Y is the same.
– Solution: Consider the circuit in Fig. 1.9. The modified circuit to compute the
Thevenin voltage across X Y , considering V A alone, is shown in Fig. 1.10. We
have
4Ix V
Ix
+ −
X
+ 1Ω
VA V
−
IB A
4Ω RL = 6 Ω
3Ω
Fig. 1.9 A circuit

4Ix1 V
Ix1
+ −
X
+
+ 1Ω
VA V
− ISC, 1
4Ω
VTH, 1
−
Y
Fig. 1.10 To compute Thevenin equivalent of Fig. 1.9 across X Y , considering V A alone
V A − I x1 − 4I x1 − 4I x1 = 0
⇒ I x1 = V A /9
⇒ VTH, 1 = 4I x1 = 4V A /9 V. (1.27)
The short-circuit current ISC, 1 through X Y is given by
V A − ISC, 1 − 4ISC, 1 = 0
⇒ ISC, 1 = V A /5
⇒ RTH, 1 = VTH, 1 /ISC, 1 = 20/9 . (1.28)
The modified circuit to compute the Thevenin voltage across X Y , considering I B

alone, is shown in Fig. 1.11. We have
Fig. 1.11 To compute 4Ix2 V

Ix2
Thevenin equivalent of Fig. 1.9 + −
b c d X
across X Y , considering I B
+
alone 1Ω
4Ω
ISC, 2
IB A
I1 I2 VTH, 2
3Ω
−
a e Y
I x2 = I1
I1 − I2 = I B . (1.29)
Applying KVL in the supermesh abcdea in Fig. 1.11 and using (1.29), we get
− I1 − 4I1 − 4I2 = 0
⇒ I1 = 4I B /9
I2 = −5I B /9
⇒ VTH, 2 = 4I2 = −20I B /9 V. (1.30)
To compute the short-circuit current ISC, 2 through X Y , we apply KVL on the super-
mesh abcdea in Fig. 1.11 and use (1.29) to get
− I1 − 4I1 = 0
⇒ I1 = 0
I2 = −I B = ISC, 2
⇒ RTH, 2 = VTH, 2 /ISC, 2 = 20/9 . (1.31)
Using superposition, the overall Thevenin voltage across X Y is
VTH = VTH, 1 + VTH, 2

= 4V A /9 − 20I B /9 V. (1.32)
The Thevenin resistance across X Y is
RTH = RTH, 1 = RTH, 2

= 20/9 . (1.33)
10. In Fig. 1.12, find the Thevenin equivalent across terminal X Y , as seen by R L , using
superposition (considering one independent source at a time). For each independent
source, verify that the Thevenin resistance across X Y is the same.
– Solution: Consider the circuit in Fig. 1.12. The modified circuit to compute the
Thevenin voltage across X Y , considering V A alone, is shown in Fig. 1.13. Applying
KCL at node a in Fig. 1.13, we have
3I x + I x = 0
⇒ Ix = 0
⇒ VTH, 1 = −V A V. (1.34)
In order to compute ISC, 1 , we apply KCL in node b in Fig. 1.13 to obtain

4Ω
3Ix A
5Ω
Ix
IB A
RL = 6 Ω
−
6Ω
VA V
+
Fig. 1.12 A circuit
b X c
+
4Ω
3Ix A
5Ω ISC, 1
Ix
VTH, 1
−
VA V
+
−
a Y d
Fig. 1.13 To compute Thevenin equivalent of Fig. 1.12 across X Y , considering V A alone
ISC, 1 = −4I x . (1.35)
Applying KVL in the loop abcda of Fig. 1.13, we get
− V A + 5I x = 0
⇒ I x = V A /5 A
⇒ ISC, 1 = −4V A /5. (1.36)
Therefore
RTH, 1 = VT H , 1 /I SC, 1 = 5/4 . (1.37)
The modified circuit to compute the Thevenin voltage across X Y , considering I B

alone, is shown in Fig. 1.14. Applying KCL at node b in Fig. 1.14, we have
b X
+
4Ω
3Ix A
5Ω ISC, 2
Ix
IB A
VTH, 2
6Ω
−
Y
Fig. 1.14 To compute Thevenin equivalent of Fig. 1.12 across X Y , considering I B alone
I B = I x + 3I x
⇒ I x = I B /4
⇒ VTH, 2 = 5I x = 5I B /4 V. (1.38)
Similarly it is clear that
ISC, 2 = I B A. (1.39)
Therefore
RTH, 2 = VTH, 2 /ISC, 2 = 5/4 . (1.40)
Using superposition, the overall Thevenin voltage across X Y is
VTH = VTH, 1 + VTH, 2

= −V A + 5I B /4 V. (1.41)
The Thevenin resistance across X Y is
RTH = RTH, 1 = RTH, 2

= 5/4 . (1.42)
11. In Fig. 1.15, find I1 , Vz , I x and I y .
– Solution: Consider Fig. 1.15. Define
R = 3 × 7/10 = 21/10 . (1.43)
Therefore, applying current division at node a

5Iy V
2Ω 5A
f g h + − a
+
+ Ix 4Ix V I2
10 V
− −
8Ω 3Ω 6Ω 7Ω
Iy 1Ω
I1
4Ω
− +
e d c b
Vz
Fig. 1.15 A circuit
I1 = −5 × R/(R + 6) = −35/27 A. (1.44)
The current flowing from node b to node c is 5 A. Hence
Vz = 4 × 5 = 20 V. (1.45)
Applying KVL in the loop de f gd, we get
10 − 2I x − 4I x − I y = 0
⇒ 6I x + I y = 10. (1.46)
Moreover
I2 = (4I x + I y )/8 A. (1.47)
Applying KCL at node d, we have
I x = I y + I2 + 5
⇒ 4I x − 9I y = 40. (1.48)
I x = 65/29 A
I y = −100/29 A. (1.49)
12. In Fig. 1.16, find I1 , I2 , I x and I y .
– Solution: Consider the circuit in Fig. 1.16. Define

2Iy V
6Ω
d e + − a
+ Ix 5Ix A
+ 10 V
5V
− 10 Ω
−
5Ω 4Ω
b
Iy 3Ω
I1
6Ω
c I2
Fig. 1.16 A circuit
R = 5 × 4/(5 + 4) = 20/9 . (1.50)
Then
I2 = 10/(R + 6) = 45/37 A
⇒ I1 = −I2 × 4/9
= −20/37 A. (1.51)
Note that:
I y = 5I x . (1.52)
Applying KVL in the loop abcdea, we get
5 − 6I x − 2I y − 10 = 0
⇒ I x = −5/16 A
⇒ I y = −25/16 A. (1.53)
13. A 10 V battery having a (series) internal resistance of 2 is connected across a resistor

whose value is x . Next, an additional 5 resistor is connected across the battery. Find
x such that the overall power supplied by the battery (including the power dissipated
in the internal resistance) is the same in both cases.
– Solution: When x alone is connected, let the current through the battery be I1 A.
Then
I1 = 10/(x + 2) A. (1.54)
Hence, the overall power delivered by the battery is
P1 = 10I1 − 2I12 . (1.55)
When an additional 5 resistance is connected across the battery, let the current
through the battery be I2 A. Then
I2 = 10/(2 + R) A (1.56)
where
R = 5x/(5 + x) . (1.57)
The overall power delivered by the battery is
P2 = 10I2 − 2I22 . (1.58)
Since
10I1 − 2I12 = 10I2 − 2I22

⇒ (I1 − I2 )(10 − 2(I1 + I2 )) = 0 (1.59)
we get two solutions. The first solution is
I1 = I2
⇒x=0 (1.60)
which is a trivial solution. The second solution is
I1 + I2 = 5
⇒ 5x − 4x − 20 = 0
2
√
⇒ x = (4 ± 416)/10. (1.61)
Since x has to be positive, we get

√
x = (4 + 416)/10 . (1.62)
14. A 10 A current source having a (parallel) internal resistance of 2 is connected across

a resistor whose value is x . Next, a series combination of 2 and x resistors, is
connected across the current source. Find x such that the overall power supplied by the
current source (including the power dissipated in the internal resistance) is the same in
both cases.
– Solution: When x alone is connected, the resultant resistance is

R1 = 2x/(2 + x) . (1.63)
The current through the internal resistance is
I1 = 10x/(2 + x) = 5R1 . (1.64)
Hence, the overall power supplied by the current source is
P1 = 100R1 − 2I12 = 100R1 − 50R12 . (1.65)
In the second case, the overall resistance is
R2 = 2(2 + x)/(4 + x) . (1.66)
The current through the internal resistance is
I2 = 10(2 + x)/(4 + x) = 5R2 . (1.67)
Hence, the overall power supplied by the current source is
P2 = 100R2 − 2I22 = 100R2 − 50R22 . (1.68)
Since
100R1 − 50R12 = 100R2 − 50R22

⇒ 50(R1 − R2 )[2 − (R1 + R2 )] = 0 (1.69)
we get two solutions. The first solution is
R1 = R2
⇒x→∞ (1.70)
which is a trivial solution. The second solution is
R1 + R2 = 2
⇒ x + 2x − 4 = 0
2
√
⇒ x = (−2 ± 20)/2. (1.71)
Since x must be positive, we get

√
x = −1 + 5 . (1.72)
15. In Fig. 1.17, find I using KVL. Again, find I by applying Thevenin’s theorem across
terminals X Y , as seen by R L .
4I
1Ω − +
I X
3V
+
RL = 2 Ω
−
Fig. 1.17 A circuit
– Solution: Applying KVL in Fig. 1.17, we get
3 − I + 4I − 2I = 0
⇒ I = −3 A. (1.73)
Now, let us compute I using Thevenin’s theorem. Consider Fig. 1.18. Clearly
VTH = 3 V. (1.74)
To compute ISC , we apply KVL in Fig. 1.18 to obtain
3 − ISC + 4ISC = 0
⇒ ISC = −1 A. (1.75)
Therefore
VTH
RTH =
ISC
= −3 . (1.76)
4I
1Ω − +
I X
+
ISC
3V
+
VTH
−
−
Fig. 1.18 To compute Thevenin equivalent of Fig. 1.17 across X Y , as seen by R L

RTH = −3 Ω
I X
VTH = 3 V
+
RL = 2 Ω
−
Fig. 1.19 Thevenin equivalent of Fig. 1.17 across X Y , as seen by R L
Note that a negative resistance is a device that generates power (instead of absorbing
or dissipating power). The resulting circuit is shown in Fig. 1.19. Applying KVL in
Fig. 1.19, we get
VTH − I RTH − 2I = 0
⇒ I = −3 A (1.77)
which is identical to (1.73).
16. In Fig. 1.20, find I using KVL. Again, find I by applying Thevenin’s theorem across
terminals X Y , as seen by R L .
– Solution: Applying KVL in Fig. 1.20, we get
10 − 2I − 3I − 4I = 0
⇒ I = 10/9 A. (1.78)
Now, let us compute I using Thevenin’s theorem. Consider Fig. 1.21. Clearly
3I
2Ω + −
I X
10 V
+
RL = 4 Ω
−
Fig. 1.20 A circuit

3I
2Ω + −
I X
+
ISC
10 V
+
VTH
−
−
RTH = 5 Ω
I X
VTH = 10 V
+
RL = 4 Ω
−
VTH = 10 V. (1.79)
To compute ISC , we apply KVL in Fig. 1.21 to obtain
10 − 2ISC − 3ISC = 0
⇒ ISC = 2 A. (1.80)
Therefore
VTH
RTH =
ISC
= 5 . (1.81)
The resulting circuit is shown in Fig. 1.22. Applying KVL in Fig. 1.22, we get
VTH − I RTH − 4I = 0
⇒ I = 10/9 A (1.82)

+ X
IL
3Vx
8A
4Ω RL = 6 Ω
Vx
− Y
Fig. 1.23 A circuit
17. In Fig. 1.23, find I L using KCL at node X . Again, find I L by applying Thevenin’s
theorem across terminals X Y , as seen by R L .
– Solution: Applying KCL at node X in Fig. 1.23, we get
3Vx + Vx /4 + Vx /6 = 8
⇒ Vx = 96/41 A
⇒ I L = Vx /R L
= 16/41 A. (1.83)
Now, let us compute I L using Thevenin’s theorem. Consider Fig. 1.24. Applying
KCL at node X , we get
Vx /4 + 3Vx = 8
⇒ Vx = 32/13 V
= VTH . (1.84)
X+
ISC
3Vx
8A
4Ω
Vx = VTH
Y −

RTH = 4/13 Ω
IL X
VTH = 32/13 V
+
RL = 6 Ω
−
Clearly
ISC = 8 A. (1.85)
Therefore
VTH
RTH =
ISC
= 4/13 . (1.86)
The resulting circuit is shown in Fig. 1.25. Applying KVL in Fig. 1.25, we get
VTH − I L RTH − 6I L = 0
⇒ I L = 16/41 A (1.87)
18. In Fig. 1.26, find the voltage drop across the current source. Clearly indicate the polarity.
– Solution: Refer to Fig. 1.27. Note that
I = −3 A. (1.88)
Applying KVL, we get
Fig. 1.26 A circuit 3A
20 V
+
4Ω
−
Fig. 1.27 A circuit V3
3A
+ −
20 V
+ I
4Ω
−
20 − V3 − 4I = 0
⇒ V3 = 32 V. (1.89)
19. In Fig. 1.28, find I1 and I2 using the supermesh concept. Clearly identify the supermesh.
Also, find the voltage across the 2 A current source. Clearly indicate the polarity.
– Solution: Consider Fig. 1.28. Note that
Vx = 3(I1 − I3 )
I3 = 4. (1.90)
Consider the supermesh abcda. Applying KVL in the supermesh, we get
4 − 3(I1 − I3 ) − 5(I2 − I3 ) − 3Vx = 0

⇒ 12I1 + 5I2 = 72 (1.91)
where we have used (1.90). We also have
I2 − I1 = 2. (1.92)
1Ω I3 4A
+ Vx −
c
b d
4V
+ 3Ω 5Ω
+
2A
3Vx
− I1 I2
−
a
Fig. 1.28 A circuit

1Ω I3 4A
+ Vx −
c +
b d
4V
+ 3Ω 5Ω
+
2A V2
3Vx
− I1 I2
−
a −
Fig. 1.29 A circuit
2Ω I3 1A
6Ω 7Ω
c
b d
− Vx +
+
3A
+
I1 I2 5V
2Vx
−
−
a
Fig. 1.30 A circuit
I1 = 62/17 A
I2 = 96/17 A. (1.93)
In order to compute the voltage across the current source, consider Fig. 1.29. Apply-
ing KVL in mesh 1, we get
4 − 3(I1 − I3 ) − V2 = 0
⇒ V2 = 86/17 V. (1.94)
20. In Fig. 1.30, find I1 and I2 using the supermesh concept. Clearly identify the supermesh.
Also, find the voltage across the 3 A current source. Clearly indicate the polarity.

Vx = −7(I2 − I3 )
I3 = −1. (1.95)
Consider the supermesh abcda. Applying KVL in the supermesh, we get
2Vx − 6(I1 − I3 ) + Vx − 5 = 0
⇒ 6I1 + 21I2 = −32. (1.96)
where we have used (1.95). We also have
I1 − I2 = 3. (1.97)
I1 = 31/27 A
I2 = −50/27 A. (1.98)
In order to compute the voltage across the current source, consider Fig. 1.31. Apply-
ing KVL in mesh 2, we get
V3 + Vx − 5 = 0
⇒ V3 = −26/27 V. (1.99)
21. In Fig. 1.32, find the power delivered by each of the three circuit elements, using the
passive sign convention.
– Solution: Consider Fig. 1.33. Applying KVL in the loop, we get
2Ω I3 1A
6Ω 7Ω
c +
b d
− Vx +
+
3A
+
I1 I2 5V
2Vx
V3 −
−
a −
Fig. 1.31 A circuit

8V
− +
−
2 3
12 V
1
5A
+
Fig. 1.32 A circuit
8V V3
− + − +
−
2 3
12 V
1
5A
+
Fig. 1.33 A circuit
− 12 + 8 + V3 = 0
⇒ V3 = 4 V. (1.100)
Hence
P1 = −60 W
P2 = 40 W
P3 = 20 W. (1.101)
22. For the circuit in Fig. 1.34, find I1 , I2 , I3 and the power dissipated in the 5 V source.
Assume that the voltage at node b is Vb = 0 V.
– Solution: Consider Fig. 1.34. We have
Vb = Ve = 0 V
Va = Vc = V f = 5 V
Vd = Vg
= Vc + 3I x . (1.102)
Now
I3
5V 3Ix 2Iy
2Ω 1Ω 6Ω
− +
b e f g
a c d
+
Ix Iy I1
I2
Fig. 1.34 A circuit
Vb − Vc
Ix =
2
0−5
= A
2
⇒ Vd = Vc + 3I x
= −5/2 V
= Vg . (1.103)
We also have
Vg − V f
I1 =
6
= −5/4 A
Ve − Vd
Iy =
1
= 5/2 A. (1.104)
Applying KCL at node e, we get
I2 = I y = 5/2 A. (1.105)
Applying KCL at node b, we get
I2 = I3 + I x = 5/2 A
⇒ I3 = 5 A. (1.106)
Power dissipated in the 5 V source is
− 5I3 = −25 W. (1.107)

23. For the circuit in Fig. 1.35, find I1 , I2 , I3 and the power supplied by the 4 V source.
Assume that the voltage at node b is Vb = 0 V.
Vb = Ve = 0 V
Va = Vc = V f = −4 V
Vd = Vg
= Vc + 3I x . (1.108)
Now
Vb − Vc
Ix =
7
4
= A
7
⇒ Vd = Vc + 3I x
= −16/7 V
= Vg . (1.109)
We also have
Vg − V f
I1 =
1
= 12/7 A
Ve − Vd
Iy =
6
= 8/21 A. (1.110)
I3
4V 3Ix 5Iy
7Ω 6Ω 1Ω
− +
−
b e f g
a c d
Ix Iy I1
I2
Fig. 1.35 A circuit

5Vx 4Iy
2Ω 6Ω
− +
− +
Iy +
+
+ Vz
7Vz
3Ω 5Ω Vx
− 4V
−
I1 I2 I3
−
Fig. 1.36 A circuit
Applying KCL at node e, we get
I y + 5I y + I2 = 0
⇒ I2 = −16/7 A. (1.111)
Applying KCL at node b, we get
I2 = I3 + I x = 5/2 A
⇒ I3 = −20/7 A. (1.112)
Power supplied by the 4 V source is
− 4I3 = 80/7 W. (1.113)
24. For the circuit in Fig. 1.36, find I1 , I2 and I3 .
Vz = −2I1
I y = I1 − I2
Vx = 5(I2 − I3 )
I1 = 5Vx
= 25(I2 − I3 ). (1.114)
Applying KCL in loop 2, we get
− 3(I2 − I1 ) + 4I y − Vx = 0
⇒ 7I1 − 12I2 + 5I3 = 0. (1.115)
Substituting for I1 from (1.114), we get

163I2 − 170I3 = 0. (1.116)
Vx − 6I3 − 7Vz = 0
⇒ 14I1 + 5I2 − 11I3 = 0. (1.117)
355I2 − 361I3 = 0. (1.118)
The only solution to (1.116) and (1.118) is
I2 = I3 = 0
⇒ I1 = 0. (1.119)
25. For the circuit in Fig. 1.37, find I1 , I2 and I3 .
Vz = 3I1
I y = I1 − I2
Vx = 6(I2 − I3 )
I1 = 2Vx
= 12(I2 − I3 ). (1.120)
− 2(I2 − I1 ) − 4I y − Vx = 0
⇒ 2I1 + 4I2 − 6I3 = 0. (1.121)
2Vx 4Iy
3Ω 5Ω
+ −
+ −
Iy +
−
+ Vz
8Vz
2Ω 6Ω Vx
− 6V
+
I1 I2 I3
−
Fig. 1.37 A circuit

28I2 − 30I3 = 0. (1.122)
Vx − 5I3 + 8Vz = 0
⇒ 24I1 + 6I2 − 11I3 = 0. (1.123)
294I2 − 299I3 = 0. (1.124)
The only solution to (1.122) and (1.124) is
I2 = I3 = 0
⇒ I1 = 0. (1.125)
26. For the circuit in Fig. 1.38, find I1 , I2 and I3 using mesh/supermesh analysis. The
supermesh (if required) should not contain the 10 V source.
I1 − I2 = 2 A. (1.126)
Applying KCL in loop 3, we obtain
−
10 V
4Ω 3Ω
a b c
+
2A
+
3V I1 I2 8Ω 9Ω
I3
− 1Ω
f e d
Fig. 1.38 A circuit

− 8(I3 − I2 ) − 10 − 9I3 = 0
⇒ −8I2 + 17I3 + 10 = 0. (1.127)
8V
7Ω 5Ω
+
a b c
3A
+
6V I1 I2 10 Ω 3Ω
I3
− 1Ω
f e d
Fig. 1.39 A circuit
Applying KCL in the supermesh abcde f a results in
3 − 4I1 − 3I2 − 8(I2 − I3 ) = 0

⇒ −4I1 − 11I2 + 8I3 + 3 = 0. (1.128)
From (1.126), (1.127) and (1.128), we get
I1 = 1.1361257 A
I2 = −0.8638743 A
I3 = −0.9947644 A. (1.129)
27. For the circuit in Fig. 1.39, find I1 , I2 and I3 using mesh/supermesh analysis. The
supermesh (if required) should not contain the 8 V source.
I1 − I2 = −3 A. (1.130)
Applying KCL in loop 3, we obtain
− 10(I3 − I2 ) + 8 − 3I3 = 0
⇒ 10I2 − 13I3 + 8 = 0. (1.131)
Applying KCL in the supermesh abcde f a results in

6 − 7I1 − 5I2 − 10(I2 − I3 ) = 0

⇒ −7I1 − 15I2 + 10I3 + 6 = 0. (1.132)
From (1.130), (1.131) and (1.132), we get
I1 = −0.6827957 A
I2 = 2.3172043 A
I3 = 2.3978495 A. (1.133)
28. For the circuit in Fig. 1.40, find Va , Vb and Vz using nodal analysis. Assume that the
voltage at node c is Vc = 0 V. The power supplied by the 2 resistor is −8 W. The
potential at node b is higher than that of d.
Vx = Vb − Va . (1.134)
The power dissipated in the 2 resistor is 8 W. Therefore
I =2 A (1.135)
in the direction indicated in Fig. 1.41. Applying KCL at node a and using (1.134)
yields
Vb − Va Va − 3Vx
1+ =
4 3
19Va 5Vb
⇒ − − 1 = 0. (1.136)
12 4
1V Vx
− +
5Ω
−
a b
+
4Ω
3Ω 1Ω 2Ω
1A
−
Iy d
+ −
+
3Vx Vz 6Iy
− − +
Fig. 1.40 A circuit

1V Vx
− +
5Ω
+
a b I
+
4Ω
3Ω 1Ω 2Ω
1A
−
Iy d
+ −
+
3Vx Vz 6Iy
− − +
Fig. 1.41 A circuit
Applying KCL at node b gives

Vb − Va Vb − Vz
2+ + = 0. (1.137)
4 1
Now
Vb − Vz
Iy = . (1.138)
1
Along path bdc, we have
Vb − (−6I y )
I = =2
2
4 − Vb
⇒ Iy = . (1.139)
6
From (1.138) and (1.139), we get
7Vb − 4
Vz = . (1.140)
6
Substituting (1.140) in (1.137) gives
−Va Vb 8
+ + = 0. (1.141)
4 12 3
From (1.136) and (1.141), we obtain
Va = 18 V
Vb = 22 V. (1.142)
3V Vx
+ −
4Ω
a b
+
−
5Ω
3Ω 2Ω 1Ω
7A
−
Iy d
+ − −
4Vx Vz 4Iy
−
+ +
Fig. 1.42 A circuit
Substituting (1.142) and (1.140), we get
Vz = 25 V. (1.143)
29. For the circuit in Fig. 1.42, find Va , Vb and Vz using nodal analysis. Assume that the
voltage at node c is Vc = 0 V. The power supplied by the 1 resistor is −9 W. The
potential at node b is higher than that of d.
Vx = Va − Vb . (1.144)
The power dissipated in the 1 resistor is 9 W. Therefore
I =3 A (1.145)
in the direction indicated in Fig. 1.43. Applying KCL at node a and using (1.144)
yields
Va − Vb Va − 4Vx
+ =7
5 3
⇒ −12Va + 17Vb − 105 = 0. (1.146)

Vb − Va Vb + Vz
2+ + = 0. (1.147)
5 1
Now
3V Vx
+ −
4Ω
a b I=3A
+
−
5Ω
3Ω 2Ω 1Ω
7A
−
Iy d
+ − −
4Vx Vz 4Iy
−
+ +
Fig. 1.43 A circuit
Vb + Vz
Iy = . (1.148)
2
Along path bdc, we have
Vb − (−4I y )
I = =3
1
3 − Vb
⇒ Iy = . (1.149)
4
From (1.148) and (1.149), we get
3 − 3Vb
Vz = . (1.150)
2
Substituting (1.150) in (1.147) gives
− 4Va − Vb + 75 = 0. (1.151)
From (1.146) and (1.151), we obtain
Va = 14.625 V
Vb = 16.5 V. (1.152)
Substituting (1.152) and (1.150), we get
Vz = −23.25 V. (1.153)
30. For the circuit in Fig. 1.44, find the power delivered by each of the circuit elements.
+ −
+
+ Vx
2Vx
10 V
− −
+ −
+
+ Vx
2Vx
10 V
− I
−
– Solution: Consider Fig. 1.45. Applying KVL in the loop, we obtain
10 − Vx − 2Vx = 0
⇒ Vx = 10/3 V. (1.154)
Therefore
I = Vx /5 = 2/3 A. (1.155)
The power delivered by each of the circuit elements is
P10 V = 10I
= 20/3 W
P5 ¨ = −5I 2
= −20/9 W
P2Vx = −2Vx I
= −40/9 W. (1.156)
31. The dc network in Fig. 1.46, consisting of two independent sources, some dependent
sources and resistors, is connected to a 5 resistor (R). With one independent source
acting alone, the power dissipated in R is 125 W and the current through R is in
the downward direction. With the other independent source acting alone, the power
dissipated in R is 20 W and the current through R is in the upward direction. Find the
power dissipated in R when both the independent sources are connected to the network.
Fig. 1.46 A circuit
A dc
R=5Ω
network
Fig. 1.47 A circuit
A dc
R=6Ω
network
– Solution: The current through R when the first independent source alone is connected
to the network

125/5 = 5 A (1.157)
in the downward direction. The current through R when the second independent
source alone is connected to the network

20/5 = 2 A (1.158)
in the upward direction. The current through R when both sources are connected is
5−2=3 A (1.159)
in the downward direction. Therefore, the power dissipated in R when both sources
are connected is
32 × 5 = 45 W. (1.160)
32. The dc network in Fig. 1.47, consisting of two independent sources, some dependent
sources and resistors, is connected to a 6 resistor (R). With one independent source
acting alone, the power dissipated in R is 24 W and the current through R is in the
upward direction. With the other independent source acting alone, the power dissipated
in R is 96 W and the current through R is in the upward direction. Find the power
dissipated in R when both the independent sources are connected to the network.
– Solution: The current through R when the first independent source alone is connected
to the network

24/6 = 2 A (1.161)
in the upward direction. The current through R when the second independent source
alone is connected to the network

96/6 = 4 A (1.162)
in the upward direction. The current through R when both sources are connected is
4+2=6 A (1.163)
in the upward direction. Therefore, the power dissipated in R when both sources are
connected is
62 × 6 = 216 W. (1.164)
RL and RC Transients
2
1. In Fig. 2.1, the switch S1 is closed for 0 ≤ t < ∞ and S2 is closed for 0 ≤ t ≤ 1 s. S2
is opened at t = 1 s. Find i(t) for 0 ≤ t < ∞. It is given that i(0) = 0 A.
– Solution: Consider Fig. 2.1. Let v L (t) denote the voltage across the inductor. Then
v L (t) = Ldi(t)/dt. (2.1)
Clearly
i(t) = 4t A for 0 ≤ t ≤ 1 s
⇒ i(1) = 4 A. (2.2)
After the switch is opened
i(t) = i(∞) − (i(∞) − i(1))e−R(t−1)/L for 1 ≤ t < ∞ (2.3)
where
i(∞) = 4/2 = 2 A
i(1) = 4 A
R=2
L = 1 H. (2.4)
Substituting (2.4) in (2.3), we get
i(t) = 2 + 2e−2(t−1) A for 1 ≤ t < ∞. (2.5)

https://doi.org/10.1007/978-3-031-09363-0_2
40 2 RL and RC Transients
Fig. 2.1 RL transient
Fig. 2.2 RC transient
2. In Fig. 2.2, the switch is open for 0 ≤ t ≤ 2 s. It is closed at t = 2 s. Find the voltage
across the capacitor, vC (t), for 0 ≤ t < ∞. It is given that vC (0) = 0 V.
– Solution: Consider Fig. 2.2. We know that
i(t) = CdvC (t)/dt

⇒ vC (t) = 2.5t V for 0 ≤ t ≤ 2 s. (2.6)
When the switch is closed at t = 2 s, we have
vC (t) = vC (∞) − (vC (∞) − vC (2))e−(t−2)/(RC) for 2 ≤ t < ∞ (2.7)
where after source transformation (converting the Norton equivalent to the Thevenin
equivalent)
vC (∞) = 15 V
vC (2) = 5 V
R=3
C = 2 F. (2.8)
2 RL and RC Transients 41
vC (t) = 15 − 10e−(t−2)/6 V for 2 ≤ t < ∞. (2.9)
3. In Fig. 2.3, the switch S1 is closed for 0 ≤ t ≤ 1 s. It is opened at t = 1 s. At t = 1− s S2

is closed. Find i(t) for 0 ≤ t < ∞. It is given that i(0) = 0 A. If required, the Thevenin
equivalent across X Y must be computed using mesh analysis.
– Solution: We know that
v L (t) = Ldi(t)/dt. (2.10)
Therefore
i(t) = 2t A for 0 ≤ t ≤ 1 s. (2.11)
Let us now compute the Thevenin equivalent across X Y using mesh analysis. Note
that
I x = I1 − I2 . (2.12)
− 2I1 − 3I x − 3(I1 − I2 ) = 0
⇒ 4I1 = 3I2 . (2.13)
− 6I2 − 5 − 3(I2 − I1 ) = 0
⇒ −3I1 + 9I2 = −5. (2.14)
I1 = −5/9 A
I2 = −20/27 A. (2.15)
Hence
VTH = −2I1 = 10/9 V (2.16)
with a polarity as indicated in Fig. 2.4. The short-circuit current ISC is computed by
again applying KVL in mesh 1 and 2. We have
− 3I x − 3(I1 − I2 ) = 0
⇒ I1 = I2
−6I2 − 5 − 3(I2 − I1 ) = 0
⇒ I2 = −5/6 = I1 = −ISC . (2.17)
Therefore
RTH = VTH /ISC = 4/3 . (2.18)
The equivalent circuit for t ≥ 1 s is shown in Fig. 2.5. We know that
i(t) = i(∞) − (i(∞) − i(1))e−R(t−1)/L for 1 ≤ t < ∞ (2.19)
where
i(∞) = 5/6 A
i(1) = 2 A
R = 4/3
L = 2 H. (2.20)
i(t) = 5/6 + (7/6)e−2(t−1)/3 A for 1 ≤ t < ∞. (2.21)
4. In Fig. 2.6, the switch S1 is in d for 0 ≤ t ≤ 3 s. At t = 3 s it is moved to e and S2 is

closed. Find vC (t) for 0 ≤ t < ∞. It is given that vC (0) = 0 V. If required, the Thevenin
equivalent across X Y must be computed using nodal analysis. Assume that the voltage
at node a is Va = 0 V.
– Solution: Consider Fig. 2.6. We know that
i(t) = CdvC (t)/dt. (2.22)
Therefore
vC (t) = 5t/3 V for 0 ≤ t ≤ 3 s

⇒ vC (3) = 5 V. (2.23)
The Thevenin equivalent across X Y is computed as follows. Note that, in Fig. 2.7
Vx = Vc . (2.24)
Applying KCL at node c, we get

Vc Vc − 6
2Vc = +
6 4
⇒ Vc = −18/19 V. (2.25)
Hence
VTH = Vb = −3 × 2Vx = 108/19 V (2.26)
with a polarity as shown in Fig. 2.7. Similarly
ISC = −2Vx = 36/19 A. (2.27)
Hence
RTH = VTH /ISC = 3 . (2.28)
Finally, the equivalent circuit for t ≥ 3 s is illustrated in Fig. 2.8. We know that
where
vC (∞) = 108/19 V
vC (3) = 5 V
R=3
C = 3 F. (2.30)
vC (t) = 108/19 − (13/19)e−(t−3)/9 V for 3 ≤ t < ∞. (2.31)
5. In Fig. 2.9, the switch is closed at t = 0 s. Find v L (t) for t ≥ 0. It is given that i(0) = 0.
– Solution: Consider Fig. 2.9. We need to find the Thevenin equivalent across X Y , as
shown in Fig. 2.10. Applying KCL at node a, we get
Vx /4 + 3 = 3Vx
⇒ Vx = 12/11 V. (2.32)
Therefore
VTH = 3Vx × 11 = 36 V (2.33)
with a polarity as shown in Fig. 2.10. Similarly, the short-circuit current is given by
ISC = 3Vx = 36/11 A. (2.34)
Therefore
RTH = VTH /ISC = 11 . (2.35)
The equivalent circuit for t ≥ 0 is given in Fig. 2.11. After the switch is closed
i(t) = i(∞) − (i(∞) − i(0))e−Rt/L for 0 ≤ t < ∞ (2.36)
with
i(∞) = 36/11 A
i(0) = 0 A. (2.37)
Therefore
i(t) = (36/11) − (36/11)e−11t/9 A for 0 ≤ t < ∞. (2.38)

Hence
v L (t) = Ldi(t)/dt = 9(−36/11)(−11/9)e−11t/9

= 36e−11t/9 V for 0 ≤ t < ∞. (2.39)
6. In Fig. 2.12, the switch is closed at t = 0 s. Find i(t) for t ≥ 0. It is given that vC (0) = 0
V.
– Solution: Consider Fig. 2.12. We need to find the Thevenin equivalent across X Y ,
as shown in Fig. 2.13. Clearly
Vx = 4 V
VTH = 2Vx = 8 V. (2.40)
In order to compute ISC , we use mesh analysis. Applying KVL to mesh 1, we get
5 − I1 − 4(I1 − I2 ) = 0. (2.41)
KVL in mesh 2 yields

2Vx = 0
⇒ Vx = 0
⇒ 4(I1 − I2 ) = 0
⇒ I1 = I2 = ISC . (2.42)
I1 = I2 = ISC = 5 A. (2.43)
Hence
RTH = VTH /ISC = 8/5 . (2.44)
The equivalent circuit for t ≥ 0 is shown in Fig. 2.14. We know that
vC (t) = vC (∞) − (vC (∞) − vC (0))e−t/(RC) for 0 ≤ t < ∞ (2.45)
where
vC (∞) = 8 V
vC (0) = 0 V
R = 8/5
C = 2 F. (2.46)
vC (t) = 8 − 8e−5t/16 V for 0 ≤ t < ∞. (2.47)
Therefore
i(t) = CdvC (t)/dt = 2(−8)(−5/16)e−5t/16

= 5e−5t/16 A for 0 ≤ t < ∞. (2.48)

7. In Fig. 2.15, switch S1 is closed for 0 ≤ t < 2 s. At t = 2 s, S2 is closed and S1 is opened.

Find v(t) for t ≥ 0. It is given that i(0) = 0 A.
– Solution: Consider Fig. 2.15. It is clear that
v(t) = 0 V for 0 ≤ t < 2 s. (2.49)
Let us now compute i(t) for 0 ≤ t < 2 s. We know that
i(t) = i(∞) − (i(∞) − i(0))e−Rt/L for 0 ≤ t < 2 s (2.50)
where
i(∞) = 5 A
i(0) = 0 A
R=2
L = 4 H. (2.51)
i(t) = 5 − 5e−t/2 A for 0 ≤ t < 2 s. (2.52)
For t ≥ 2 s we have
i(t) = i(∞) − (i(∞) − i(2))e−R(t−2)/L for 2 ≤ t < ∞ (2.53)
where
i(∞) = 0 A
i(2) = 3.161 A
R=5
L = 4 H. (2.54)
i(t) = 3.161e−5(t−2)/4 A for 2 ≤ t < ∞. (2.55)
Finally
v(t) = −5i(t) = −15.8e−5(t−2)/4 V for 2 ≤ t < ∞. (2.56)
8. In Fig. 2.16, switch S1 is closed for 0 ≤ t < 3 s. At t = 3 s, S2 is closed and S1 is opened.

Find i(t) for t ≥ 0. It is given that vC (0) = 0 V.
– Solution: We know that
vC (t) = vC (∞) − (vC (∞) − vC (0))e−t/(RC) for 0 ≤ t < 3 s (2.57)
where
vC (∞) = 6 V
vC (0) = 0 V
R=3
C = 5 F. (2.58)
vC (t) = 6 − 6e−t/15 V for 0 ≤ t < 3 s. (2.59)

For t ≥ 3, we have
where
vC (∞) = 0 V
vC (3) = 1.09 V
R=4
C = 5 F. (2.61)
vC (t) = 1.09e−(t−3)/20 V for 3 ≤ t < ∞. (2.62)
Hence

2e−t/15 A for 0 ≤ t < 3 s
i(t) = CdvC (t)/dt = (2.63)
−0.272e−(t−3)/20 A for 3 ≤ t < ∞.
9. In Fig. 2.17, switch is closed at t = 0 s. Find i 1 (t) and i 2 (t) for t ≥ 0. It is given that
i 1 (0) = i 2 (0) = 0 A.
– Solution: Consider Fig. 2.17. We know that when two inductors are in parallel, the
equivalent inductance is
L = L 1 L 2 /(L 1 + L 2 ) = 20/9 H. (2.64)
The resulting circuit is shown in Fig. 2.18. We know that
i(t) = i(∞) − (i(∞) − i(0))e−Rt/L for 0 ≤ t < ∞ (2.65)
where
i(∞) = 3/2 = 1.5 A

i(0) = 0 A
R=2
L = 20/9 H. (2.66)
i(t) = 1.5 − 1.5e−9t/10 A for 0 ≤ t < ∞. (2.67)
Note that
Ldi(t)/dt = L 1 di 1 (t)/dt = L 2 di 2 (t)/dt

⇒ di 1 (t)/dt = (L/L 1 )di(t)/dt
di 2 (t)/dt = (L/L 2 )di(t)/dt
⇒ i 1 (t) = (L/L 1 )i(t) + C1
i 2 (t) = (L/L 2 )i(t) + C2 (2.68)
where C1 and C2 are constants that can be obtained from the initial conditions. Since
i 1 (0) = i 2 (0) = 0, we obtain C1 = C2 = 0. Therefore

i 1 (t) = (L/L 1 )i(t) = (5/9) 1.5 − 1.5e−9t/10 A for 0 ≤ t < ∞. (2.69)
Similarly

i 2 (t) = (L/L 2 )i(t) = (4/9) 1.5 − 1.5e−9t/10 A for 0 ≤ t < ∞. (2.70)
10. In Fig. 2.19, switch is closed at t = 0 s. Find v1 (t) and v2 (t) for t ≥ 0. It is given that
v1 (0) = v2 (0) = 0 V.
– Solution: Consider Fig. 2.19. We know that when two capacitors are in series, the
resultant capacitance is given by
C = C1 C2 /(C1 + C2 ) = 10/7 F. (2.71)
The resulting circuit is shown in Fig. 2.20. When the switch is closed at t = 0 s, we
have
vC (t) = vC (∞) − (vC (∞) − vC (0))e−t/(RC) for 0 ≤ t < ∞ (2.72)
where
vC (∞) = 10 V
vC (0) = 0 V
R=6
C = 10/7 F. (2.73)
vC (t) = 10 − 10e−7t/60 V for 0 ≤ t < ∞. (2.74)
Note that
i(t) = CdvC (t)/dt = −C1 dv1 (t)/dt = −C2 dv2 (t)/dt

⇒ dv1 (t)/dt = −(C/C1 )dvC (t)/dt
dv2 (t)/dt = −(C/C2 )dvC (t)/dt
⇒ v1 (t) = −(C/C1 )vC (t) + K 1
v2 (t) = −(C/C2 )vC (t) + K 2 (2.75)
where K 1 and K 2 are constants that can be found out from the initial conditions.
Since v1 (0) = v2 (0) = 0, we obtain K 1 = K 2 = 0. Therefore
v1 (t) = −(C/C1 )vC (t)

= −(5/7) 10 − 10e−7t/60 V for 0 ≤ t < ∞. (2.76)
Similarly
v2 (t) = −(C/C2 )vC (t)

= −(2/7) 10 − 10e−7t/60 V for 0 ≤ t < ∞. (2.77)
11. In Fig. 2.21, switch S1 is closed for 0 ≤ t ≤ 2 s. At t = 2 s, S1 is opened and S2 is

closed. Find i 1 (t) for t ≥ 0. It is given that i(0) = 0 A.
– Solution: Consider Fig. 2.21. We need to compute the Thevenin equivalent across
terminals X Y as seen by the inductor, for 0 ≤ t ≤ 2 s. This is illustrated in Fig. 2.22.
Clearly
VTH = 4 V
RTH = 4/3 . (2.78)
We know that
i(t) = i(∞) − (i(∞) − i(0))e−Rt/L for 0 ≤ t ≤ 2 (2.79)
where
i(∞) = 3 A
i(0) = 0 A
R = 4/3
L = 3 H. (2.80)
i(t) = 3 − 3e−4t/9 A for 0 ≤ t ≤ 2 s. (2.81)
For t ≥ 2 s, the circuit is shown in Fig. 2.23. We use
i(t) = i(∞) − (i(∞) − i(2))e−R(t−2)/L for 2 ≤ t < ∞ (2.82)
where
i(∞) = 0 A
i(2) = 1.77 A
R = 4 × 6/10 = 2.4
L = 3 H. (2.83)
i(t) = 1.77e−0.8(t−2) A for 2 ≤ t < ∞ s. (2.84)
Now
v L (t) = Ldi(t)/dt (2.85)
with a polarity as indicated in Figs. 2.22 and 2.23. Therefore
v L (t) = 4e−4t/9 V for 0 ≤ t ≤ 2 s

⇒ i 1 (t) = v L (t)/4 = e−4t/9 A for 0 ≤ t ≤ 2 s. (2.86)
For t ≥ 2 s, we use current division to obtain
i 1 (t) = −0.6i(t) = −1.06e−0.8(t−2)/9 A for 2 ≤ t < ∞ s. (2.87)
12. In Fig. 2.24, switch S1 is closed for 0 ≤ t ≤ 3 s. At t = 3 s, S1 is opened and S2 is

closed. Find i 1 (t) for t ≥ 0. It is given that vC (0) = 0 V.
– Solution: We need to compute the Thevenin equivalent across terminals X Y as seen

by the capacitor, for 0 ≤ t ≤ 3 s. This is illustrated in Fig. 2.25. Clearly
VTH = 3 V
RTH = 15/8 . (2.88)

We know that
vC (t) = vC (∞) − (vC (∞) − vC (0))e−t/(RC) for 0 ≤ t ≤ 3 s (2.89)
where
vC (∞) = 3 V
vC (0) = 0 V
R = 15/8
C = 4 F. (2.90)
vC (t) = 3 − 3e−2t/15 V for 0 ≤ t ≤ 3 s. (2.91)
For t ≥ 3 s, the circuit is shown in Fig. 2.26. We use
vC (t) = vC (∞) − (vC (∞) − vC (3))e−(t−3)/(RC) for 3 ≤ t < ∞ s (2.92)
where
vC (∞) = 0 V
vC (3) = 0.989 V
R = 6 × 3/9 = 2
C = 4 F. (2.93)
vC (t) = 0.989e−(t−3)/8 V for 3 ≤ t < ∞ s. (2.94)
Now

1 − e−2t/15 A for 0 ≤ t ≤ 3 s
i 1 (t) = vC (t)/3 = (2.95)
0.32968e−(t−3)/8 A for 3 ≤ t < ∞ s.
13. In Fig. 2.27, the switch S is closed at time t = 0 s. Find vC (t) and i 1 (t) for t ≥ 0. It is
given that vC (0− ) = 2 V. Assume that the voltage at node c is Vc = 0 for all t. Note
that Vx and Vy may be functions of time.
– Solution: Consider Fig. 2.27. Once the switch S is closed, we need to compute
the Thevenin equivalent across ad, as seen by the capacitor. This is illustrated in
Fig. 2.28. Firstly, let us compute VTH . Along path baeg, we have
Vb − 6I1 − 2Vy − 2I1 = 0. (2.96)

Note that
V y = I2
I3 = I1
Vx = 2I1 . (2.97)
Along path b f c, we have
Vb − 10 − I2 = 0. (2.98)
Applying KCL at node b, we obtain
I1 + I2 = 5 A. (2.99)
Using (2.96) through (2.99) gives
Vb = 100/7 V
I1 = 5/7 A
I2 = 30/7 A. (2.100)
Therefore
Va = Vb − 6I1
= 10 V
Vd = Vx
= 2I1
= 10/7 V
⇒ VTH = Va − Vd
= 60/7 V. (2.101)
In order to compute ISC , we apply KVL along the loop adgea to obtain
Vx + 2Vy − Vx = 0
⇒ Vy = 0
⇒ I2 = 0
⇒ I3 = 5 A
⇒ Vb = 10 V
⇒ Va = Vb − 6I3
= −20 V
⇒ I1 = Va /2
= −10 A
⇒ ISC = 15 A. (2.102)
Therefore
RTH = VTH /ISC

= 4/7 . (2.103)
vC (t) = vC (∞) − (vC (∞) − vC (0))e−t/(RC) for 0 ≤ t < ∞ s (2.104)

where
vC (∞) = 60/7 V
vC (0) = 2 V
R = RTH
= 4/7
C = 2 F. (2.105)
vC (t) = 60/7 − (46/7)e−7t/8 V for 0 ≤ t < ∞ s. (2.106)
To compute i 1 (t) consider Fig. 2.30. Note that
i C (t) = CdvC (t)/dt

= (23/2)e−7t/8 A for 0 ≤ t < ∞ s. (2.107)
Applying KVL in the loop adgea, we get
Vx + 2Vy − vC (t) − Vx = 0
⇒ Vy = vC (t)/2
= i 2 (t)
⇒ i 3 (t) = 5 − i 2 (t)
⇒ i 1 (t) = i 3 (t) − i C (t)
= 5 − i 2 (t) − i C (t). (2.108)
14. In Fig. 2.31, the switch S is closed at time t = 0 s. Find vC (t) and i 1 (t) for t ≥ 0. It is
given that vC (0− ) = 3 V. Assume that the voltage at node c is Vc = 0 for all t. Note
that Vx and Vy may be functions of time.
– Solution: Consider Fig. 2.31. Once the switch S is closed, we need to compute
the Thevenin equivalent across ad, as seen by the capacitor. This is illustrated in
Fig. 2.32. Firstly, let us compute VTH . Along path baeg, we have
Vb − 5I1 − 3Vy − I1 = 0. (2.109)
Note that
Vy = 2I2
I3 = I1
Vx = −I1 . (2.110)
Along path b f c, we have
Vb − 10 − 2I2 = 0. (2.111)
Applying KCL at node b, we obtain
I1 + I2 = 4 A. (2.112)
Using (2.109) through (2.112) gives
Vb = 24 V
I1 = −3 A
I2 = 7 A. (2.113)
Therefore
Va = Vb − 5I1
= 39 V
Vd = −Vx
= I1
= −3 V
⇒ VTH = Va − Vd
= 42 V. (2.114)
In order to compute ISC , we apply KVL along the loop adgea to obtain
Vx + 3Vy − Vx = 0
⇒ Vy = 0
⇒ I2 = 0
⇒ I3 = 4 A
⇒ Vb = 10 V
⇒ Va = Vb − 5I3
= −10 V
⇒ I1 = Va /1
= −10 A
⇒ ISC = 14 A. (2.115)
Therefore
RTH = VTH /ISC

= 3 . (2.116)
vC (t) = vC (∞) − (vC (∞) − vC (0))e−t/(RC) for 0 ≤ t < ∞ s (2.117)
where
vC (∞) = 42 V
vC (0) = 3 V
R = RTH
=3
C = 4 F. (2.118)
vC (t) = 42 − 39e−t/12 V for 0 ≤ t < ∞ s. (2.119)
To compute i 1 (t), consider Fig. 2.34. Note that
i C (t) = CdvC (t)/dt

= 13e−t/12 A for 0 ≤ t < ∞ s. (2.120)
Applying KVL in the loop adgea, we get

Vx + 3Vy − vC (t) − Vx = 0
⇒ Vy = vC (t)/3
= 2i 2 (t)
⇒ i 3 (t) = 4 − i 2 (t)
⇒ i 1 (t) = i 3 (t) − i C (t)
= 4 − i 2 (t) − i C (t). (2.121)
15. In Fig. 2.35, the switch S is closed at time t = 0 s. Find v L (t), i L (t) and i 1 (t) for t ≥ 0.
Assume that the voltage at node c is Vc = 0 for all t. Note that I x may be a function of
time.
– Solution: Consider Fig. 2.35. Once the switch S is closed, we need to compute the
Thevenin equivalent across ad, as seen by the inductor. This is illustrated in Fig. 2.36.
Firstly, let us compute VTH . It is clear that
5 − Vb
I1 =
10
Vb
Ix = . (2.122)
10
I x + 5I x = I1
⇒ Vb = 5/7 V
⇒ Va = Vb + 7
= 54/7 V
= VTH . (2.123)
Next we proceed to compute ISC . Note that

Va = 0 V
⇒ Vb = −7 V
⇒ I x = Vb /10
= −7/10 A
⇒ I1 = (5 − Vb )/10
= 12/10 A. (2.124)
Applying KCL at the supernode ab, we get
5I x + I x + ISC = I1
⇒ ISC = 54/10 A. (2.125)
Therefore
RTH = VTH /ISC

= 10/7 . (2.126)
The equivalent circuit is shown in Fig. 2.37. We know that
i L (t) = i L (∞) − (i L (∞) − i L (0))e−Rt/L for 0 ≤ t < ∞ (2.127)
where
i L (∞) = ISC
= 54/10 A
i L (0) = 0 A
R = RTH
= 10/7
L = 2 H. (2.128)
i L (t) = (54/10) − (54/10)e−5t/7 A for 0 ≤ t < ∞. (2.129)
Hence
v L (t) = Ldi L (t)/dt

= (54/7)e−5t/7 V for 0 ≤ t < ∞. (2.130)
In order to compute i 1 (t), consider Fig. 2.38. Note that
Vb = v L (t) − 7
5 − Vb
⇒ i 1 (t) =
10
= (12/10) − v L (t)/10. (2.131)
16. In Fig. 2.39, the switch S is closed at time t = 0 s. Find v L (t), i L (t) and i 1 (t) for t ≥ 0.
Assume that the voltage at node c is Vc = 0 for all t. Note that I x may be a function of
time.
– Solution: Consider Fig. 2.39. Once the switch S is closed, we need to compute the
Thevenin equivalent across ad, as seen by the inductor. This is illustrated in Fig. 2.40.
Firstly, let us compute VTH . It is clear that
10 − Vb
I1 =
6
−Vb
Ix = . (2.132)
5
I x + 6I x + I1 = 0
⇒ Vb = 50/47 V
⇒ Va = Vb + 8
= 426/47 V
= VTH . (2.133)
Next we proceed to compute ISC . Note that
Va = 0 V
⇒ Vb = −8 V
⇒ I x = −Vb /5
= 8/5 A
⇒ I1 = (10 − Vb )/6
= 3 A. (2.134)
Applying KCL at the supernode ab, we get
6I x + I x + I1 = ISC
⇒ ISC = 71/5 A. (2.135)
Therefore
RTH = VTH /ISC

= 30/47 . (2.136)
The equivalent circuit is shown in Fig. 2.41. We know that
i L (t) = i L (∞) − (i L (∞) − i L (0))e−Rt/L for 0 ≤ t < ∞ (2.137)
where
i L (∞) = ISC
= 71/5 A
i L (0) = 0 A
R = RTH
= 30/47
L = 3 H. (2.138)
i L (t) = (71/5) − (71/5)e−10t/47 A for 0 ≤ t < ∞. (2.139)
Hence

= (426/47)e−10t/47 V for 0 ≤ t < ∞. (2.140)
In order to compute i 1 (t), consider Fig. 2.42. Note that
Vb = v L (t) − 8
10 − Vb
⇒ i 1 (t) =
6
= 3 − v L (t)/6. (2.141)

17. Consider the RC circuit in Fig. 2.43a. The input vi (t) is a square wave of infinite
duration, time period T = T1 + T2 , maximum amplitude V1 and minimum amplitude
V2 , as given in Fig. 2.43b. Find vo (t) and v R (t).
– Solution: Since the input voltage vi (t) is periodic with a period T1 + T2 , both vo (t)
and v R (t) are also periodic with the same period. Hence, we only need to compute
vo (t) and v R (t) for one period. Consider the time interval t ∈ [0, T1 ]. We know that
vC (t) = vC (∞) − [vC (∞) − vC (0)] e−t/(RC) . (2.142)
Let α denote the time index in the interval t ∈ [0, T1 ]. We have
vC (0) = VC2 (say)

vC (∞) = V1 . (2.143)
Substituting (2.143) in (2.142) and taking the time index as α, we obtain
vC (α) = V1 − [V1 − VC2 ] e−α/(RC) for 0 ≤ α ≤ T1 (2.144)
with the constraint that

vC (T1 ) = V1 − [V1 − VC2 ] e−T1 /(RC)

= VC1 (say). (2.145)
Let β denote the time index in the interval t ∈ [T1 , T1 + T2 ]. Note that:
t = T1
⇒β=0
t = T1 + T2
⇒ β = T2 . (2.146)
We have
vC (0) = VC1 (say)

vC (∞) = V2 . (2.147)
Substituting (2.147) in (2.142) and taking the time index as β, we obtain
vC (β) = V2 − [V2 − VC1 ] e−β/(RC) for 0 ≤ β ≤ T2 (2.148)
vC (T2 ) = V2 − [V2 − VC1 ] e−T2 /(RC)

= VC2 . (2.149)
From (2.145) and (2.149), we get
V1 (1 − x0 ) + V2 x0 (1 − y0 )
VC1 =
1 − x0 y0
V1 y0 (1 − x0 ) + V2 (1 − y0 )
VC2 = (2.150)
1 − x0 y0
where
x0 = e−T1 /(RC)
y0 = e−T2 /(RC) . (2.151)
To summarize:

vC, 1 (t) for 0 ≤ t < T1
vC (t) = (2.152)
vC, 2 (t) for T1 ≤ t < T1 + T2
where
vC, 1 (t) = V1 − [V1 − VC2 ] exp(−t/(RC))

vC, 2 (t) = V2 − [V2 − VC1 ] exp(−(t − T1 )/(RC)) (2.153)
where VC1 and VC2 are given in (2.150). In order to compute v R (t), we first note
that i(t) in Fig. 2.43a is given by
i(t) = CdvC (t)/dt

⇒ v R (t) = Ri(t)
= RCdvC (t)/dt. (2.154)
Therefore

[V1 − VC2 ] exp(−t/(RC)) for 0 ≤ t < T1
v R (t) =
]V2 − VC1 ] exp(−(t − T1 )/(RC)) for T1 ≤ t < T1 + T2
(2.155)
where VC1 and VC2 are given in (2.150). Let us consider an example where vi (t)
has the following parameters:
V1 = 3 V
V2 = −1 V
T1 = 1 s
T2 = 3 s. (2.156)
The plot of vi (t), vC (t) and v R (t) when RC = 40 s is shown in Figs. 2.44, 2.45
and 2.46. The plot of vC (t) and v R (t) when RC = 4 s is shown in Figs. 2.47 and
2.48. The plot of vC (t) and v R (t) when RC = 0.4 s is shown in Figs. 2.49 and 2.50.
18. Consider the R L circuit in Fig. 2.51a. The input vi (t) is a square wave of infinite
duration, time period T = T1 + T2 , maximum amplitude V1 and minimum amplitude
V2 , as given in Fig. 2.51b. Find vo (t) and v L (t).
– Solution: Since the input voltage vi (t) is periodic with a period T1 + T2 , both vo (t)
and v L (t) are also periodic with the same period. Hence, we only need to compute
vo (t) and v L (t) for one period. Consider the time interval t ∈ [0, T1 ]. We know that
i L (t) = i L (∞) − [i L (∞) − i L (0)] e−Rt/L . (2.157)

Fig. 2.44 Plot of vi (t)
Fig. 2.45 Plot of vC (t) when RC = 10T

Fig. 2.46 Plot of v R (t) when RC = 10T
Fig. 2.47 Plot of vC (t) when RC = T

Fig. 2.48 Plot of v R (t) when RC = T
Fig. 2.49 Plot of vC (t) when RC = 0.1T

Fig. 2.50 Plot of v R (t) when RC = 0.1T

Let α denote the time index in the interval t ∈ [0, T1 ]. We have
i L (0) = I L2 (say)
i L (∞) = V1 /R

= I1 . (2.158)
Substituting (2.158) in (2.157) and taking the time index as α, we obtain
i L (α) = I1 − [I1 − I L2 ] e−Rα/L for 0 ≤ α ≤ T1 (2.159)
i L (T1 ) = I1 − [I1 − I L2 ] e−RT1 /L

= I L1 (say). (2.160)
Let β denote the time index in the interval t ∈ [T1 , T1 + T2 ]. Note that:
t = T1
⇒β=0
t = T1 + T2
⇒ β = T2 . (2.161)
We have
i L (0) = I L1 (say)
i L (∞) = V2 /R

= I2 . (2.162)
Substituting (2.162) in (2.157) and taking the time index as β, we obtain
i L (β) = I2 − [I2 − I L1 ] e−Rβ/L for 0 ≤ β ≤ T2 (2.163)
i L (T2 ) = I2 − [I2 − I L1 ] e−RT2 /L

= I L2 . (2.164)
From (2.160) and (2.164), we get

I1 (1 − x0 ) + I2 x0 (1 − y0 )
I L1 =
1 − x0 y0
I1 y0 (1 − x0 ) + I2 (1 − y0 )
I L2 = (2.165)
1 − x0 y0
where
x0 = e−RT1 /L
y0 = e−RT2 /L . (2.166)
To summarize

i L, 1 (t) for 0 ≤ t < T1
i L (t) = (2.167)
i L, 2 (t) for T1 ≤ t < T1 + T2
where
i L, 1 (t) = I1 − [I1 − I L2 ] exp(−Rt/L)

i L, 2 (t) = I2 − [I2 − I L1 ] exp(−R(t − T1 )/L) (2.168)
where I L1 and I L2 are given in (2.165). Now
v R (t) = Ri L (t)

v R, 1 (t) for 0 ≤ t < T1
= (2.169)
v R, 2 (t) for T1 ≤ t < T1 + T2
where
v R, 1 (t) = V1 − [V1 − V2 ] exp(−Rt/L)

v R, 2 (t) = V2 − [V2 − V1 ] exp(−R(t − T1 )/L) (2.170)
where
V1 (1 − x0 ) + V2 x0 (1 − y0 )
V1 =
1 − x0 y0
V y (1 − x0 ) + V2 (1 − y0 )
V2 =
1 0
(2.171)
1 − x0 y0
where x0 and y0 are defined in (2.166). Similarly

v L, 1 (t) for 0 ≤ t < T1
= (2.172)
v L, 2 (t) for T1 ≤ t < T1 + T2
Fig. 2.52 Plot of vi (t)
Fig. 2.53 Plot of v R (t) when L/R = 10T

Fig. 2.54 Plot of v L (t) when L/R = 10T
Fig. 2.55 Plot of v R (t) when L/R = T

Fig. 2.56 Plot of v L (t) when L/R = T
Fig. 2.57 Plot of v R (t) when L/R = 0.1T

Fig. 2.58 Plot of v L (t) when L/R = 0.1T
where
v L, 1 (t) = [V1 − V2 ] exp(−Rt/L)

v L, 2 (t) = [V2 − V1 ] exp(−R(t − T1 )/L) (2.173)
where V1 and V2 are defined in (2.171). Let us consider an example where vi (t) has
the following parameters:
V1 = 3 V
V2 = −1 V
T1 = 1 s
T2 = 3 s. (2.174)
The plot of vi (t), v R (t) and v L (t) when L/R = 40 s is shown in Figs. 2.52, 2.53 and
2.54. The plot of v R (t) and v L (t) when L/R = 4 s is shown in Figs. 2.55 and 2.56.
The plot of v R (t) and v L (t) when L/R = 0.4 s is shown in Figs. 2.57 and 2.58.
AC Circuits—Steady-State Analysis
3
1. In Fig. 3.1, the magnitude of the phasor voltages across L and C are 5 V and 4 V,
respectively. Find the magnitude of the phasor voltage across R and the values of I , θ ,
L and C. It is given that the magnitude of the phasor represents the peak value (not the
rms value).
– Solution: Consider Fig. 3.1. Let VR = V R ∠θ ◦ denote the phasor voltage across
the resistor. Then the phasor voltages across the inductor and the capacitor are
VL = VL ∠(θ + 90)◦ and VC = VC ∠(θ − 90)◦ , respectively. It is given that VL = 5
V and VC = 4 V. This is illustrated in Fig. 3.2. We have
V R ∠θ ◦ + VL ∠(θ + 90)◦ + VC ∠(θ − 90)◦ = 10∠0◦

⇒ V R cos(θ ) − sin(θ ) = 10
V R sin(θ ) + cos(θ ) = 0
⇒ (V R cos(θ ) − sin(θ ))2 + (V R sin(θ ) + cos(θ ))2 = 102
√
⇒ V R = 99
√
θ = − tan−1 (1/ 99).
(3.1)
Therefore
√
I = 99/4 A
I ωL = 5
√
⇒ L = 10/ 99 H
I /(ωC) = 4
√
⇒ C = 99/32 F. (3.2)

https://doi.org/10.1007/978-3-031-09363-0_3
86 3 AC Circuits—Steady-State Analysis
Fig. 3.1 AC circuit
Fig. 3.2 AC circuit
2. In Fig. 3.3, the magnitude of the phasor currents through L and C are 8 A and 4 A,
respectively. Find the magnitude of the phasor current through R and the values of V ,
θ , L and C. It is given that the magnitude of the phasor represents the peak value (not
the rms value).
– Solution: Consider Fig. 3.4. Let IR = I R ∠θ ◦ denote the phasor current through
the resistor. Then the phasor currents through the inductor and capacitor can be
represented by IL = I L ∠(θ − 90)◦ and IC = IC ∠(θ + 90)◦ respectively. It is given
that I L = 8 A and IC = 4 A. This is illustrated in Fig. 3.5. We have
Fig. 3.3 AC circuit

3 AC Circuits—Steady-State Analysis 87
Fig. 3.4 AC circuit
Fig. 3.5 AC circuit
I R ∠θ ◦ + I L ∠(θ − 90)◦ + IC ∠(θ + 90)◦ = 8∠0◦

⇒ I R cos(θ ) + 4 sin(θ ) = 8
I R sin(θ ) − 4 cos(θ ) = 0
⇒ (I R cos(θ ) + 4 sin(θ )) + (I R sin(θ ) − 4 cos(θ ))2 = 82 .
2
(3.3)
Hence
√
IR = 48

−1 1
θ = tan √ . (3.4)
3
Therefore
√
V = 3 48 V
V /ωL = 8
√
⇒ L = 3/2 H
V ωC = 4
√
⇒ C = 1/(9 3) F. (3.5)
Fig. 3.6 AC circuit
3. In Fig. 3.6, find Ix using mesh analysis.
– Solution: Consider Fig. 3.6. Let the phasor current in the two loops be I1 and I2 . We
have
I1 − I2 = Ix . (3.6)
The KVL equation for mesh 1 is
5 − 4 I1 − j ωL Ix = 0
⇒ 4 I1 + 2j ( I1 − I2 ) = 5. (3.7)

1
− 2 Ix − I2 + j ωL Ix = 0
j ωC
⇒ Ix (−2 + 2j) + 4j I2 = 0
⇒ ( I1 − I2 )(−2 + 2j) + 4j I2 = 0
⇒ I1 = j I2 . (3.8)
From (3.7) and (3.8), we have

5j
I1 =
−2 + 2j
5
I2 = . (3.9)
−2 + 2j
Therefore
Ix = I1 − I2 = 5/2 A. (3.10)

Fig. 3.7 AC circuit
4. In Fig. 3.7, find Vx using nodal analysis. Assume that the voltage at node a is
Va = 0 V.
– Solution: Consider Fig. 3.7. Applying KCL at node b, we have
Vx Vx − 6
+ = 3Vx
1/(j ωC) j ωL
2j
⇒ Vx = . (3.11)
5
5. In Fig. 3.8, find Z such that maximum power is delivered to it. You may assume that
the voltage at node a is Va = 0 V.
– Solution: Consider Fig. 3.8. We need to find out the Thevenin equivalent across X Y
as seen by Z . This is illustrated in Fig. 3.9. To compute VTH , note that
Fig. 3.8 AC circuit

Fig. 3.9 AC circuit
1
− Vx = 3Vx ×
j ωC
= −15j Vx
⇒ Vx = 0
⇒ VTH = 8∠ − 90◦ = −8j. (3.12)
Next, ISC is computed by applying KCL at node b. Let the voltage at node b be Vb . We
have
Vb + 8j Vb
+ = 3Vx . (3.13)
2 + 1/(j ωC) j ωL
However
Vb + 8j 1
Vx = − ×
2 + 1/(j ωC) j ωC
Vb + 8j
= 5j . (3.14)
2 − 5j
Vb + 8j Vb Vb + 8j

+ = 15j
2 + 1/(j ωC) j ωL 2 − 5j
Vb + 8j Vb Vb + 8j
+ = 15j
2 − 5j 8j 2 − 5j
⇒ Vb = 0.3308937 − 7.8769892j V. (3.15)
Therefore
ISC = Vb /(j ωL) = −0.9846236 − 0.0413617j A. (3.16)

Hence
Z TH = VTH / ISC = 0.3407080 + 8.1106195j . (3.17)
In order to deliver maximum power to the load, we must have
Z = Z TH
∗
= 0.3407080 − 8.1106195j . (3.18)
6. In Fig. 3.10, find Z , such that the maximum power is delivered to it.
– Solution: We need to find out the Thevenin equivalent across X Y as seen by Z . To

compute VTH , consider Fig. 3.11. Applying KVL to loop 1, we get

1
10 − I1 j ωL + − 2 Vx = 0 (3.19)
j ωC
with
1
Vx = I1 × . (3.20)
j ωC
Fig. 3.10 AC circuit

I1 = 5j. (3.21)
Therefore
VTH = 2 Vx = 20 V. (3.22)
To compute ISC consider Fig. 3.12. Applying KVL to loop 1, we get

1
10 − I2 j ωL + − 2 Vx = 0 (3.23)
j ωC
with
1
Vx = I2 × . (3.24)
j ωC
I2 = 5j. (3.25)
Hence
I3 = ISC = 2 Vx /3 = 20/3 A. (3.26)
Therefore
Z TH = VTH / ISC = 3 . (3.27)
In order to deliver maximum power to the load, we must have
Z = Z TH
∗
= 3 . (3.28)
7. In Fig. 3.13, find Vx using superposition. Give the time-domain representation of Vx .

– Solution: Consider Fig. 3.13. Let us first consider the current source 4 cos(t) A alone.
The resulting circuit is shown in Fig. 3.14. Note that
I1 = 4 A (3.29)
which is also the total current in mesh 1. Hence
I1 = 4 A. (3.30)
Applying KVL to loop 2, we get

1 1
− I2 − I1 ×
− I2 R + =0
j ωC1 j ωC2
⇒ I2 = 1.2389 − 1.4159j A.
(3.31)
Next we consider the current source −6 sin(t) alone. The resulting circuit is shown in
Fig. 3.15. Note that
I3 = 6j A. (3.32)
Applying KVL to loop 2, we get
1 1

− I2 ×
− I2 − I3 R+ =0
j ωC1 j ωC2
I2 = −2.12389 + 4.14159j A.
(3.33)
Therefore, the total current in mesh 2 is
I2 = I2 + I2 = −0.8849558 + 2.7256637j A. (3.34)
Hence
1
Vx = I1 − I2 ×
j ωC1
= −13.628319 − 24.424779j A. (3.35)
The time-domain representation of Vx is
vx (t) = 27.969642 cos(t + 240.83975◦ ) V. (3.36)
8. In Fig. 3.16, find Ix using superposition. Give the time-domain representation of Ix .
Assume that the voltage at node a is Va = 0.
– Solution: Refer to Fig. 3.16. Let us first consider the voltage source −4 cos(t) alone.
This is illustrated in Fig. 3.17. Let the phasor voltage at node b be Vb . Applying
KCL at node b, we obtain
Vb − (−4) V
+ b + Vb j ωC1 = 0
R1 j ωL
−40
⇒ Vb = V. (3.37)
10 − 9j
Next we consider the voltage source 2 sin(t) V alone. This is illustrated in Fig. 3.18.
Let Vb denote the phasor voltage at node b. The KCL equation at node b is
Vb V
+ b + Vb − (−2j) j ωC1 = 0
R1 j ωL
12
⇒ Vb = V. (3.38)
10 − 9j
The total voltage at node b is

−28
Vb = Vb + Vb = . (3.39)
10 − 9j
Therefore
Vb 7j
Ix = = = −0.3480663 + 0.3867403j A. (3.40)
j ωL 10 − 9j
The time-domain representation of Ix is
i x (t) = 0.5203059 cos(t + 131.98721◦ ). (3.41)
9. In Fig. 3.19, find IL using mesh analysis. Give the time-domain representation of IL .
– Solution: Let the mesh currents be denoted by I1 and I2 as illustrated in Fig. 3.20.
Note that
I2 = −4∠ − 30◦

= −4 cos −30◦ + j sin −30◦ A

Vx = 4 I1 . (3.42)
Applying KVL to mesh 1, we have

3∠30◦ − Vx − I1 − I2 j ωL − 2 Vx = 0
⇒ I1 = −0.9936428 − 0.9043579j
(3.43)
where we have substituted from (3.42). Now
IL = I1 − I2

= 2.4704589 − 2.9043579j A. (3.44)
The time-domain representation of IL is
i L (t) = 3.8129335 cos(t + 310.38463◦ ). (3.45)
10. In Fig. 3.21, find v L (t) using mesh analysis.

– Solution: Let the mesh currents be denoted by I1 and I2 as illustrated in Fig. 3.22.
Note that

Vx = 4 I1 − I2
I2 = −2 Vx

= −8 I1 − I2
⇒ I2 = 8 I1 /7. (3.46)
Applying KVL to mesh 1, we obtain


1
◦
8∠40 − I1 j ωL + − Vx = 0
jωC

1
◦
⇒ 8∠40 − I1 j ωL + − 4 I1 − I2 = 0
jωC
−8∠40◦
⇒ I1 =
(4/7) + 2j
= 1.5677 + 3.5120j A.
(3.47)
Hence
VL = I1 × j ωL
= −10.536273 + 4.7030877j V. (3.48)
Therefore
v L (t) = 11.538287 cos(t + 155.9454◦ ) V. (3.49)
11. A two element series circuit develops a current i(t) = 4 sin(2t + 140◦ ) A on the appli-
cation of a voltage v(t) = 10 cos(2t + 30◦ ) V across its terminals.
(a) Find the values of the circuit elements.

(b) Find the maximum possible magnitude of the current, if there is no restriction on the
operating frequency. The amplitude and phase of the applied voltage remains the
same as given above.
– Solution: The applied phasor voltage is V = 10∠30◦ . The resulting phasor current
is I = 4∠50◦ . Therefore, the impedance (inverse of reactance) of the circuit is
V
Z =
I
= 2.5∠ − 20◦ . (3.50)
Clearly, the circuit has a resistor and a capacitor. Hence
2.5∠ − 20◦ = R + 1/(j ωC)

= 2.3492316 − 0.8550504j
⇒ R = 2.3492316
C = 0.5847609 F (3.51)

where we have used ω = 2 rad/s. Note that I is maximum when Z is minimum.
This happens when ω → ∞. In this case
I = V /R
= 4.2567111∠30◦ A. (3.52)
12. A two element parallel circuit develops a voltage v(t) = 8 cos(3t + 30◦ ) V on the
application of a current i(t) = 5 sin(3t + 70◦ ) A through its terminals.
(a) Find the values of the circuit elements.

(b) Find the maximum possible magnitude of the voltage, if there is no restriction on
the operating frequency. The amplitude and phase of the applied current remains the
same as given above.
– Solution: The applied phasor current is I = 5∠ − 20◦ A. The resulting phasor volt-
age is V = 8∠30◦ . Therefore, the admittance of the circuit is
Y = I/V
= (5/8)∠ − 50◦
= 0.4017423 − 0.4787778j S. (3.53)
Clearly, the circuit has a resistor and an inductor. Hence
(5/8)∠ − 20◦ = 1/R + 1/(j ωL)

= 0.4017423 − 0.4787778j
⇒ R = 2.4891581
L = 0.6962172 H. (3.54)

Note that V is maximum when Y is minimum. This happens when ω → ∞. In this
case
V = IR
= 12.445791 V. (3.55)
13. In Fig. 3.23, v(t) = 10 cos(2t + 40◦ ) and i(t) = 2 cos(2t + 40◦ ). Find R, C, the aver-
age power delivered by the source and the power factor of the source.
– Solution: Consider Fig. 3.23. Note that ω = 2 rad/sec. Since the voltage and current
are in-phase, the impedance of the circuit, as seen by the voltage source is purely
resistive. Therefore
1
j ωL + =0
j ωC
⇒ C = 1/8 F. (3.56)
Moreover
v(t)
R=
i(t)
= 5 . (3.57)
The average power delivered by the source is
P = 10 × 2/2 = 10 W. (3.58)
The power factor of the source is unity.
14. In Fig. 3.24, v(t) = 15 cos(3t) and i(t) = 3 sin(3t + 30◦ ). Find R, L, the average power
delivered by the source and the power factor of the source.
ω = 3 rad/s
V = 15∠0◦
I = 3∠ − 60◦
V
⇒ Z =
I
= 5∠60◦
= 2.5 + 4.330127 j
⇒ R = 2.5 . (3.59)
We also have
j(ωL − 1/(ωC)) = 4.330127 j

⇒ L = 1.6655979 H. (3.60)
The average power delivered by the source is
P = 15 × 3 × cos(60◦ )/2
= 11.25 W. (3.61)
The power factor of the source is cos(60◦ ) = 0.5.
15. In Fig. 3.25, find Z L , such that the maximum power is dissipated in it. Find the power
factor of the source at this load.
– Solution: Consider Fig. 3.25. We need to compute the Thevenin’s equivalent

impedance across the nodes X Y . Note that ω = 5 rad/sec. Clearly
R
Z TH = + j ωL
1 + j ω RC
= 0.8 + 3.4 j. (3.62)
Therefore
Z L = 0.8 − 3.4 j. (3.63)
For the above value of Z L , the power factor of the source is unity.
16. In Fig. 3.26, it is given that Vb = 6 V. Find Z . All independent sources operate at the
same frequency.
– Solution: Consider Fig. 3.27. Note that the operating frequency is
ω = 1 rad/sec. (3.64)
It is given that Va = 6 V. Applying KCL at node b, we obtain
Vb − Va Vb − 16∠30◦

+ = 11∠50◦
j ωL R
⇒ Vb = −10.850554 + 30.477101 j. (3.65)
Therefore
Vx = Vb − Va

= −16.850554 + 30.477101 j

⇒ I3 = Vx /(j ω L)
= 10.159034 + 5.6168512 j

⇒ I1 = (Va − 5Vx ) j ωC1
= 7.6192753 + 4.5126384 j
⇒ I2 = I3 − I1

= 2.5397584 + 1.1042128 j
⇒ Z = Va / I2

= 1.9868616 − 0.8638294 j. (3.66)
17. In Fig. 3.28, it is given that Va = 5∠(−20)◦ V. Find Z . All independent sources operate
at the same frequency.
– Solution: Consider Fig. 3.29. Note that the operating frequency is
ω = 1 rad/sec. (3.67)
It is given that Va = 5∠(−20)◦ V. Applying KCL at node b, we obtain
Vb − Va Vb − 30∠30◦

+ = −1∠10◦
j ωL R
⇒ Vb = 2.1972739 + 10.206327 j. (3.68)
Therefore
Vx = Vb − Va

= −2.5011892 + 11.916428 j

⇒ I3 = Vx /(j ω L)
= 2.979107 + 0.6252973 j

⇒ I1 = (Va − 2 Vx ) j ωC1
= 0.5108591 + 0.1940168 j
⇒ I2 = I3 − I1

= 2.4682478 + 0.4312805 j
⇒ Z = Va / I2

= 1.7296919 − 0.9950715 j. (3.69)
18. In Fig. 3.30, it is given that Va = 0∠0◦ V. Find I1 , I2 , I3 and I4 .
Ve = 4∠(−40)◦
Vg = 5∠(−130)◦
= Vd
ω = 2 rad/sec. (3.70)
Applying KCL at node f we get:


(V f − Ve ) j ωC1 + (V f − Vg ) j ωC2 + (V f − Vd )/(j ωL) + V f /R = 0.(3.71)
Substituting the relevant parameters in (3.71), we obtain
V f = 1.8851213 − j 2.6031502 V. (3.72)
Moreover
Ve − Vg = 2 I1

⇒ I1 = 3.1390579 + j 0.6295359 A. (3.73)
It can be seen that
I5 = (V f − Ve ) j ωC1

= 0.0319997 − j 1.1790564 A
I6 = (V f − Vg ) j ωC2
= −0.6135360 + j 2.5495297 A
I7 = V f /R
= 0.3770243 − j 0.5206300 A
I8 = (V f − Vg )/(j ωL)
= 0.2045120 − j 0.8498432 A. (3.74)
Therefore
I2 = I1 + I5

= 3.1710577 − j 0.5495205 A
I4 = I2 + I8
= 3.3755697 − j 1.3993638 A
I3 = I4 + I6
= 2.7620336 + j 1.1501659 A. (3.75)
19. In Fig. 3.32, it is given that Va = 0∠0◦ V. Find I1 , I2 , I3 and I4 .
Ve = 6∠(−60)◦
Vg = 3∠(30)◦
= Vd
ω = 3 rad/sec. (3.76)
Applying KCL at node f , we get
(V f − Ve ) j ωC1 + (V f − Vg ) j ωC2 + (V f − Vd )/(j ωL) + V f /R = 0. (3.77)
Substituting the relevant parameters in (3.77), we obtain
V f = 2.7433186 − j 0.7144534 V. (3.78)
Moreover
Vg − Ve = 3 I1

⇒ I1 = −0.1339746 + j 2.2320508 A. (3.79)
It can be seen that
I5 = (V f − Ve ) j ωC1

= −13.445097 − j 0.7700442 A
I6 = (V f − Vg ) j ωC2
= 13.28672 + j 0.8714544 A
I7 = V f /R
= 0.3429148 − j 0.0893067 A
I8 = (V f − Vg )/(j ωL)
= −0.1845378 − j 0.0121035 A. (3.80)
Therefore
I2 = I1 + I5

= −13.579072 + j 1.4620066 A
I4 = I2 + I8

= −13.76361 + j 1.4499031 A
I3 = I4 + I6

= −0.4768894 + j 2.3213575 A. (3.81)
Resonance, Bode Plots and Two-Port Networks
4
1. In Fig. 4.1, find the input impedance Z in at resonance and the resonant frequency in
rad/s.
– Solution: Consider Fig. 4.1. Let

1
Z C =
j ωC
Z = R + j ωL. (4.1)
Then
Z C Z
Z in =
Z C + Z

R + j ωL
= . (4.2)
1 − ω2 LC + j ω RC
We know that at resonance Z in is purely resistive. This can happen only when (for a
real constant K )

R + j ωL = K 1 − ω2 LC + j ω RC
⇒ R = K (1 − ω2 LC)
ωL = K ω RC. (4.3)
From (4.3), we obtain the resonant frequency ω0 and the input impedance Z in as

https://doi.org/10.1007/978-3-031-09363-0_4
112 4 Resonance, Bode Plots and Two-Port Networks
Fig. 4.1 Resonance
1 R2
ω02 = − 2 rad/s
LC L
Z in =K
L
= . (4.4)
RC
2. In Fig. 4.2, find the resonant frequency in rad/s and the current i(t) at resonance.
– Solution: Consider Fig. 4.2.
Let
Z 1 = R1 + j ωL
R2 /(j ωC)
Z 2 =
1/(j ωC) + R2
R2
= . (4.5)
1 + j ωC R2
At resonance, the input impedance
Z in = Z 1 + Z 2
R1 + R2 − ω2 LC R2 + j ωL + j ω R1 R2 C
= (4.6)
1 + j ωC R2
Fig. 4.2 Resonance

4 Resonance, Bode Plots and Two-Port Networks 113
Fig. 4.3 Resonance
must be purely resistive. Therefore (for a real constant K )
R1 + R2 − ω2 LC R2 + j ωL + j ω R1 R2 C = K (1 + j ωC R2 )
⇒ K = R1 + R2 − ω2 LC R2
L + R1 R2 C = K C R2 . (4.7)
At resonance
K = (L + R1 R2 C)/(C R2 )
ω02 = (R1 + R2 − K )/(LC R2 )
i(t) = (Vm /K ) sin(ωt + θ ) A. (4.8)
3. In Fig. 4.3, find the resonant frequency in rad/s and the voltage v(t) at resonance.
– Solution
Let
Z 2 = R2 + j ωL. (4.9)
Then
Z 2 /(j ωC)
Z 1 =
Z 2 + 1/(j ωC)
Z 2
=
1 + j ωC Z 2
R2 + j ωL
= . (4.10)
1 − ω2 LC + j ωC R2
Fig. 4.4 Resonance
At resonance, Z 1 must be real-valued. Therefore, we must have (for some real constant
K)
R2 + j ωL = K (1 − ω2 LC + j ωC R2 )
⇒ R2 = K (1 − ω2 LC)
ωL = ωC R2 . (4.11)
At resonance
L
K =
C R2

1 R2
ω0 =
2
1−
LC K
R1 K
v(t) = Am sin(ωt + θ ) × . (4.12)
R1 + K
4. In Fig. 4.4, find the resonant frequency in radians per second and the input impedance
Z in at resonance.
– Solution:
Let
1
Z = R2 +
j ωC
1 + j ωC R2
= (4.13)
j ωC
The input admittance Yin is:

1 1 1
Yin = + + . (4.14)
R1 j ωL Z
At resonance Yin must be real-valued. Hence

1 1
Yin, 1 = +
j ωL Z
1 − ω2 LC + j ωC R2
= (4.15)
−ω2 LC R2 + j ωL
must be real-valued. Therefore (for some real constant K )
− ω2 LC R2 + j ωL = K (1 − ω2 LC + j ωC R2 )
⇒ −ω2 LC R2 = K (1 − ω2 LC)
ωL = K ωC R2 . (4.16)
At resonance
L
K =
C R2
1
ω02 =
LC − C 2 R22
K R1
Z in = . (4.17)
K + R1
5. In Fig. 4.5, find H (ω) = Vo /Vs . Draw the Bode magnitude and phase plot of H (ω).
– Solution Consider Fig. 4.5.
Let
Fig. 4.5 Transfer function

R = R2 + R3
R/(j ωC)
Z =
R + 1/(j ωC)
R
=
1 + j ω RC
R3
K1 = . (4.18)
R2 + R3
Then
Z
Vo = Vs K 1
R1 + Z
Vo R K1
⇒ =

Vs R + R 1 + j ω RC R1
K
=
1 + j ω/ω0
= H (ω) (4.19)
where
R K1
K =
R + R1
1 RC R1
= . (4.20)
ω0 R + R1
The Bode magnitude and phase plots are shown in Fig. 4.6, where
G = 20 log10 (K ) dB. (4.21)
6. In Fig. 4.7, express the transfer function in the form

j ω/ω0
H (ω) = Vo /Vs = . (4.22)
1 + j ω/ω1
Find ω0 and ω1 in terms of the given parameters. Draw the Bode magnitude and phase
plot of H (ω) assuming that ω1 = 0.1ω0 .
– Solution
Let
Fig. 4.6 Bode plot
R = R2 + R3
j ωL R
Z =
R + j ωL
R R1
R =
R + R1
R3
K1 = . (4.23)
R2 + R3
Therefore
Vo Z K 1
=
Vs R1 + Z
j ωL R K 1
=
R1 R + j ωL(R1 + R)
j ωL K 1 /R1
=
1 + j ωL(R1 + R)/(R R1 )
j ωL K 1 /R1
=
1 + j ωL/R
j ω/ω0
=
1 + j ω/ω1
= H (ω) (4.24)
where
R R1
R =
R + R1
ω0 = R1 /(L K 1 )
ω1 = R /L. (4.25)
It is given that
ω1 = 0.1ω0 . (4.26)
The phase contribution of various terms in (4.24) is given in Fig. 4.8. The magnitude
and phase plots are shown in Fig. 4.9.
7. Draw the Bode magnitude and phase plot of
j ω/100
H (ω) = . (4.27)
(1 + j ω/1000)2
– Solution The phase contribution of each of the terms in H (ω) is given in Fig. 4.10.
The magnitude and phase plots are shown in Fig. 4.11.
Fig. 4.8 Bode plot

Fig. 4.9 Bode plot
Fig. 4.10 Bode plot
(1 + j ω/1000)2
H (ω) = (4.28)
j ω/100
The magnitude and phase plots are shown in Fig. 4.13.
9. In Fig. 4.14, find H (ω) = Vo /Vs . It is given that R2 /L = 10/(R1 C). Draw the Bode
magnitude and phase plot of H (ω). The amplifier provides a gain of G = 10. Assume
that the current in branch ab and the voltage at node c is zero. However, the current
through R2 may be non-zero.
Fig. 4.11 Bode plot
Fig. 4.12 Bode plot
– Solution: We have:
1
V1 /Vs =
1 + ω R1 C
1
=
1 + j ω/ω0
V2 /V1 = 10
R2
Vo /V2 =
R2 + j ωL
1
=
1 + j ωL/R2
1
= (4.29)
1 + j ω/ω1
Fig. 4.13 Bode plot
where
1
ω0 =
R1 C
R2
ω1 = . (4.30)
L
Therefore
10
Vo /Vs =
(1 + j ω/ω0 )(1 + j ω/ω1 )
= H (ω) (4.31)
Fig. 4.15 Bode plot
where it is given that
ω1 = 10ω0 . (4.32)
The phase contribution of each of the terms in (4.31) is given in Fig. 4.15. The
magnitude and phase plots is given in Fig. 4.16.
10. In Fig. 4.17, find H (ω) = Vo /Vs . It is given that 1/(R2 C) = 10R1 /L. Draw the Bode
magnitude and phase plot of H (ω). The amplifier provides a gain of G = 0.1. Assume
Fig. 4.16 Bode plot

that the current in branch ab and the voltage at node c is zero. However, the current
through R2 may be non-zero.
j ωL
V1 /Vs =
R1 + j ωL
j ωL/R1
=
1 + j ωL/R1
j ω/ω0
=
1 + j ω/ω0
V2 /V1 = 0.1
R2
Vo /V2 =
R2 + 1/(j ωC)
j ω R2 C
=
1 + j ω R2 C
j ω/ω1
= (4.33)
1 + j ω/ω1
where
R1
ω0 =
L
1
ω1 = . (4.34)
R2 C
Therefore
0.1(j ω/ω0 )(j ω/ω1 )
Vo /Vs =
(1 + j ω/ω0 )(1 + j ω/ω1 )
= H (ω) (4.35)
Fig. 4.18 Bode plot
where it is given that
ω1 = 10ω0 . (4.36)
The phase contribution of each of the terms in (4.35) is given in Fig. 4.18. The magnitude
and phase plots is given in Fig. 4.19.
11. Find the transmission parameters of the two-port network in Fig. 4.20. The operating
frequency is ω = 1 rad/s.
– Solution: Consider Fig. 4.20. Recall that
V1 = A V2 − B I2

I1 = C V2 − D
I2 . (4.37)
Note that

V1
A = . (4.38)
V2
I2 =0
Consider Fig. 4.21. Let us open-circuit port 2 ( I2 = 0) and apply and voltage V1 at port
1. Note that V2 is the open-circuit voltage. We have
Fig. 4.19 Bode plot
Fig. 4.20 Two-port network

−3Vx
V2 =
j ωC
= j 12 Vx . (4.39)
Moreover
Vx = ( I1 + 3Vx ) j ωL

j 2 I1
⇒ Vx = . (4.40)
1 − 6j
Applying KVL to mesh 1 and using (4.40), we get
V1 = I1 + Vx

1 − 4j
⇒ V1 = I1 . (4.41)
1 − 6j
Since
V2 = j 12 Vx
−24 I1
= (4.42)
(1 − 6 j)
we have

V1 −1 + 4 j
=
V2
I2 =0
24

= A. (4.43)
Next

V1
− = B. (4.44)
I2 V2 =0
Consider Fig. 4.22. Let us short-circuit port 2 (V2 = 0) and apply a voltage V1 at port
1. Note that
1/(jωC)
I2 = 3Vx
R2 + 1/(j ωC)
−6 j Vx
=
1−2j
12 I1
= (4.45)
(1 − 2 j)(1 − 6 j)
where we have used
Vx = ( I1 + 3Vx ) j ωL

j 2 I1
⇒ Vx = . (4.46)
1 − 6j
Hence

V1 (1 − 2 j)(1 − 6 j) V1
= ·
I2
V2 =0
12 I1
(1 − 2 j)(1 − 4 j)
=
12
= − B (4.47)
where we have used (applying KVL in mesh 1 and using (4.46))

V1 = I1 + Vx

1 − 4j
⇒ V1 = I1 . (4.48)
1 − 6j
From (4.42)

I1 −1 + 6 j
= S
V2 I2 =0
24

= C. (4.49)
Similarly, from (4.45), we have

I1 (1 − 2 j)(1 − 6 j)
=
I2
V2 =0
12

= − D. (4.50)
12. Find the hybrid parameters of the two-port network in Fig. 4.23. The operating frequency
is ω = 1 rad/s. Assume that the voltage at node c is zero.
– Solution: Consider Fig. 4.23. Recall that:
V1 = h11 I1 + h12 V2

I2 = h21 I1 + h22 V2 . (4.51)
Note that

V1
h11 = . (4.52)
I1
V2 =0
Consider Fig. 4.24. Let us short-circuit node two and apply V1 at port 1. We have
Vb = Va − 2 Ix

Va
Ix =
1/(j ωC)
= j Va /2
⇒ Vb = Va (1 − j) (4.53)
Applying KCL in the supernode ab, we get
Va − V1 Va Vb (R2 + j ωL)

+ + =0
R1 1/(j ωC) j ωL R2
⇒ Va − V1 + j Va /2 − j 2 Va = 0
2 − 3j
⇒ V1 = Va
2
2
⇒ Va = V1
2 − 3j
(4.54)
Moreover
V1 − Va
I1 =
1
−3 j
= V1 . (4.55)
2 − 3j
Therefore

V1 −2 + 3 j
=
I1
V2 =0
3j
= h11 . (4.56)
Next

V1
= h12 . (4.57)
V2 I1 =0
Consider Fig. 4.25. Let us short-circuit port 1 ( I1 = 0) and apply V2 at port 2. We have
V1 = Va
Va = Vb + 2 Ix
Va
Ix =
1/(j ωC)
= j Va /2
⇒ Vb = Va − 2 Ix
= V1 (1 − j). (4.58)
Now
V2 = Vb + I2

= V1 (1 − j) + I2 . (4.59)
However

Vb
I2 = Ix +
j ωL
= j V1 /2 − j V1 (1 − j)

= V1 (−j /2 − 1). (4.60)
V2 = V1 (1 − j) + V1 (−j /2 − 1)

= V1 (−3 j /2) . (4.61)
Therefore

V1
= 2 j/3
V2 I1 =0
= h12 . (4.62)
Next

I2
= h21 . (4.63)
I1 V2 =0
Consider Fig. 4.24. We have
I2 = −Vb /1
= −Va (1 − j)
−2 V1 (1 − j)
= . (4.64)
2 − 3j

I2 2(1 − j)
=
I1
V2 =0
3j
= h21 . (4.65)
Finally

I2
= h22 . (4.66)
V2 I1 =0
Consider Fig. 4.25. From (4.60) and (4.61), we have


I2 (1 + j /2)
=
V2
I1 =0
3 j /2
= h22 . (4.67)
13. The admittance parameters of a reciprocal two-port network shown in Fig. 4.26 are
y11 = 2 S, y12 = 1 S and y22 = 3 S. A 4 resistor is connected across port 2. Find I2
if V1 = 13 V.
Note that the admittance parameters are specified with the 4 resistor removed.
I1 = y11 V1 + y12 V2

I2 = y21 V1 + y22 V2 . (4.68)
Since the network is reciprocal y12 = y21 . We first need to compute the Thevenin
equivalent across port 2 with the 4 resistor removed. Note that

VTH = V2 . (4.69)
I2 =0
−V1
V2 =
3

= VTH . (4.70)
Next

ISC = − I2 . (4.71)
V2 =0
Again from (4.68) and (4.71), we get
ISC = − I2 = −V1 . (4.72)
Therefore
VTH 1
Z TH = = . (4.73)
ISC 3
The equivalent circuit across port two is shown in Fig. 4.27. Clearly
−VTH
I2 =
(13/3)
V1
=
13
= 1 A. (4.74)
14. The impedance parameters of a reciprocal two-port network shown in Fig. 4.28 are
z 11 = 2 , z 12 = 4 and z 22 = 1 . A 5 resistor is connected across port 1. Find
I1 if I2 = 3 A.
Note that the impedance parameters are specified with the 5 resistor removed.
V1 = z 11 I1 + z 12 I2

V2 = z 21 I1 + z 22 I2 . (4.75)
Since the network is reciprocal z 12 = z 21 . We need to compute the Thevenin equivalent

across port 1, as seen by the 5 resistor. Note that

VTH = V1 . (4.76)
I1 =0
VTH = z 12 I2 = 4 I2 . (4.77)
Similarly

ISC = − I1 . (4.78)
V1 =0
z 12 I2
ISC = . (4.79)
z 11
Therefore
VTH
Z TH = = 2 . (4.80)
ISC
The equivalent circuit across port 1 is illustrated in Fig. 4.29. Clearly
I1 = −12/7 A. (4.81)

Fig. 4.30 Bode plot
j ω/100
H (ω) = . (4.82)
(1 + j ω/500)(1 + j ω/2000)
– Solution: The phase contribution of each of the terms in H (ω) is given in Fig. 4.30.
Note that:
φ1 = −45 log10 (200/50)

= −27.09o
φ2 = −45 log10 (2000/50)
= −72.09o
φ3 = −45 log10 (500/200)
= −17.91o
φ4 = −45 log10 (5000/200)
= −62.91o . (4.83)
The magnitude plot is shown in Fig. 4.31. Note that

Fig. 4.31 Bode plot
G = 20 log10 (500/100)
= 13.98 dB
= 20 log10 (2000/ω1 )
⇒ ω1 = 104 rad/s. (4.84)
The phase plot is shown in Fig. 4.32.

16. In Fig. 4.33, find H (ω) = Vo /Vs . Draw the Bode magnitude and phase plot of H (ω).
– Solution: Clearly
R
H (ω) =
R + j ωL
1
= (4.85)
1 + j ω/ω0
where
1 L
= . (4.86)
ω0 R
The Bode magnitude and phase plot is shown in Fig. 4.34.

Fig. 4.32 Bode plot
5
H (ω) = . (4.87)
(1 + j ω/100)(1 − j ω/500)
Show all the steps, the important points on the x and y axes and the slopes. The x-axis
must coincide with 0 dB.
Note that:
Fig. 4.34 Bode plot
Fig. 4.35 Bode plot

φ1 = −45 log10 (50/10)

= −31.45o
φ2 = −45 log10 (500/10)
= −76.45o
φ3 = +45 log10 (100/50)
= +13.546o
φ4 = +45 log10 (1000/50)
= +58.546o . (4.88)
The magnitude plot is shown in Fig. 4.36. Note that:
G = 20 log10 (5)
= 13.98 dB (4.89)
and
G − 20 log10 (ω1 /100) = 0

⇒ ω1 = 500 rad/s. (4.90)
Fig. 4.36 Bode plot

Fig. 4.37 Bode plot

3
H (ω) = . (4.91)
(1 − j ω/200)(1 + j ω/600)
Note that
φ1 = +45 log10 (60/20)

= +21.47o
φ2 = +45 log10 (600/20)
= +66.47o
φ3 = −45 log10 (200/60)
= −23.53o
φ4 = −45 log10 (2000/60)
Fig. 4.38 Bode plot
= −68.53o . (4.92)
G = 20 log10 (3)
= 9.54 dB (4.93)
and
G − 20 log10 (ω1 /200) = 0

⇒ ω1 = 600 rad/s. (4.94)

(1 + j ω/500)
H (ω) = . (4.95)
(1 + j ω/100)2
Fig. 4.39 Bode plot
Fig. 4.40 Bode plot

Fig. 4.41 Bode plot
Note that
φ1 = −90 log10 (50/10)

= −62.91o
φ2 = −90 log10 (500/10)
= −152.91o
φ3 = +45 log10 (100/50)
= +13.55o
φ4 = +45 log10 (1000/50)
= +58.55o . (4.96)
G = −40 log10 (500/100)

= −27.96 dB. (4.97)

Fig. 4.42 Bode plot
(1 + j ω/100)
H (ω) = . (4.98)
(1 + j ω/500)2
Note that
φ1 = −90 log10 (100/50)

= −27.09o
φ2 = −90 log10 (1000/50)
= −117.09o
φ3 = +45 log10 (50/10)
= +31.45o
φ4 = +45 log10 (500/10)
= +76.45o . (4.99)

Fig. 4.43 Bode plot
G = 20 log10 (500/100)
= 13.98 dB (4.100)
and
20 log10 (500/100) = −20 log10 (500/ω1 )

⇒ ω1 = 2500 rad/s. (4.101)

21. Consider a parallel R LC circuit with R = 10 k, L = 1 µH and C = 0.1 nF. Find the
resonant frequency in Hz, the quality factor at resonance and the half-power bandwidth
in Hz.
– Solution: For a parallel R LC circuit, the resonant frequency in Hz is given by

1
f0 = √
2π LC
108
=
2π
= 15915494 Hz. (4.102)
Fig. 4.44 Bode plot

Fig. 4.46 Bode plot
The quality factor at resonance is given by

C
Q0 = R
L
= 100. (4.103)
Similarly, the half-power bandwidth in Hz is

ω0
B=
2π Q 0
106
=
2π
= 159154.94 Hz. (4.104)
22. Derive the expression for the quality factor at resonance of a parallel R LC circuit.
– Solution: Consider the parallel R LC circuit shown in Fig. 4.47. The quality factor
is defined as
maximum energy stored
Q = 2π . (4.105)
total energy lost per period
Fig. 4.47 Parallel R LC

resonant circuit
Energy can be stored only in an inductor and capacitor. Energy can be lost only in a
resistor. Therefore
[wC (t) + w L (t)]max
Q 0 = 2π (4.106)
PR T0
where Q 0 is the quality factor at resonance, wC (t) and w L (t) are the energy stored in
the capacitor and inductor respectively, PR is the average power lost in the resistor and
T0 is the time period at resonant frequency. Let
I = Im ∠0o ≡ Im cos(ω0 t) (4.107)
where
2π 1
ω0 = =√ (4.108)
T0 LC
is the resonant frequency in rad/s. The input admittance is
Y = 1/R + j ωC + 1/(j ωL)

⇒ Y = 1/R
ω
0

⇒ Vo = IR
ω0
⇒ vo (t) = Im R cos(ω0 t)

IL = IR/(j ω0 L)
ω0
⇒ i L (t) = Im R/(ω0 L) cos(ω0 t − 90o )
= Im R/(ω0 L) sin(ω0 t). (4.109)
Therefore, the energy stored in the capacitor is

1 2
wC (t) = Cv (t)
2 o
1
= C Im2 R 2 cos2 (ω0 t). (4.110)
2
The energy stored in the inductor is
1 2
w L (t) = Li (t)
2 L
1 L Im2 R 2
= sin2 (ω0 t). (4.111)
2 ω02 L 2
Clearly
1 2 2
wC (t) + w L (t) = CI R (4.112)
2 m
is a constant, and is hence also the maximum energy stored. Now
1 2
PR = I R (4.113)
2 m
independent of ω. Therefore, the quality factor at resonance is
1 2
Q 0 = 2π × C Im2 R 2 × 2
2 Im RT0
= ω0 RC

C
=R . (4.114)
L
23. Derive the expression for the quality factor at resonance of a series R LC circuit.
– Solution: Consider the series R LC circuit shown in Fig. 4.48. The quality factor is
defined as
maximum energy stored
Q = 2π . (4.115)
total energy lost per period
Energy can be stored only in an inductor and capacitor. Energy can be lost only in a
resistor. Therefore
[wC (t) + w L (t)]max
Q 0 = 2π (4.116)
PR T0
where Q 0 is the quality factor at resonance, wC (t) and w L (t) are the energy stored in
the capacitor and inductor respectively, PR is the average power lost in the resistor and
T0 is the time period at resonant frequency. Let
Fig. 4.48 Series R LC resonant

circuit
V = Vm ∠0o ≡ Vm cos(ω0 t) (4.117)
where
2π 1
ω0 = =√ (4.118)
T0 LC
is the resonant frequency in rad/s. The input impedance is:
Z = R + j ωL + 1/(j ωC)

⇒ Z = R
ω
0

⇒ I = V /R
ω0
⇒ i(t) = (Vm /R) cos(ω0 t)

VC = I/(j ω0 C)
ω0
⇒ vC (t) = Vm /(ω0 RC) cos(ω0 t − 90o )
= Vm /(ω0 RC) sin(ω0 t). (4.119)
Therefore, the energy stored in the capacitor is

1 2
wC (t) = Cv (t)
2 C
1 L Vm2
= sin2 (ω0 t). (4.120)
2 R2
The energy stored in the inductor is
1 2
w L (t) = Li (t)
2
1 L Vm2
= cos2 (ω0 t). (4.121)
2 R2
Clearly
1
wC (t) + w L (t) = L V 2 /R 2 (4.122)
2 m
is a constant, and is hence also the maximum energy stored. Now
1 2
PR = V /R (4.123)
2 m
independent of ω. Therefore, the quality factor at resonance is
1 Vm2 2R
Q 0 = 2π × L × 2
2 R2 Vm T0
= ω0 L/R

1 L
= . (4.124)
R C
24. For the circuit given in Fig. 4.49, find the input impedance Z in across terminals ab.
– Solution: Consider the circuit shown in Fig. 4.50. Let us apply a voltage V = 1∠0o .
Let the resulting current be I. Then
Z in = V / I
= 1/ I. (4.125)
Applying KCL to mesh 1, we get
Fig. 4.49 Input impedance

− 4 I1 − 3( I1 − I3 ) − 5( I1 − I2 ) − 1 = 0

⇒ −12 I1 + 5 I2 + 3 I3 − 1 = 0. (4.126)
Applying KCL to mesh 2, we get:
− 6 I2 − 5( I2 − I1 ) − 2( I2 − I3 ) = 0

⇒ 5 I1 − 13 I2 + 2 I3 = 0. (4.127)
− I3 − 2( I3 − I2 ) − 3( I3 − I1 ) = 0

⇒ 3 I1 + 2 I2 − 6 I3 = 0. (4.128)
From (4.126), (4.127) and (4.128), we get
I1 = −0.1319073 A
I2 = −0.0641711 A
I3 = −0.0873440 A. (4.129)
Now
I = I2 − I1
= 0.0677362 A. (4.130)
Therefore
Z in = 1/ I
= 14.763158 . (4.131)
25. For the circuit given in Fig. 4.51, find the input impedance Z in across terminals ab.
– Solution: Consider the circuit shown in Fig. 4.52. Let us apply a voltage V = 1∠0o .
Let the resulting current be I.
Then
Z in = V / I
= 1/ I. (4.132)
− 4 I1 − 2( I1 − I3 ) − ( I1 − I2 ) − 1 = 0

⇒ −7 I1 + I2 + 2 I3 − 1 = 0. (4.133)
− 6 I2 − ( I2 − I1 ) − 3( I2 − I3 ) = 0

⇒ I1 − 10 I2 + 3 I3 = 0. (4.134)

− 5 I3 − 3( I3 − I2 ) − 2( I3 − I1 ) = 0

⇒ 2 I1 + 3 I2 − 10 I3 = 0. (4.135)
From (4.133), (4.134) and (4.135), we get
I1 = −0.1582609 A
I2 = −0.0278261 A
I3 = −0.04 A. (4.136)
Now
I = I2 − I1
= 0.1304348 A. (4.137)
Therefore
Z in = 1/ I
= 7.6666667 . (4.138)
26. For the circuit given in Fig. 4.53, find the admittance parameters. It is given that ω = 2
rad/sec. Is the network reciprocal? Justify your answer.
– Solution: Consider the circuit shown in Fig. 4.53. Recall that the admittance param-
eters are given by
Fig. 4.53 Admittance parameters
I1 = y11 V1 + y12 V2

I2 = y21 V1 + y22 V2 . (4.139)
Define
Z C = 1/(j ωC)
= −j
Z L = j ωL
= 8 j . (4.140)
Now

I1
y11 = . (4.141)
V1
V2 =0
Consider Fig. 4.54. Let

Z 1 = Z C R
Z C R
=
Z C + R
−2 j
= . (4.142)
2−j
Let
Z 2 = Z 1 + Z L
8 + 14 j
= . (4.143)
2−j
Therefore
y11 = 1/ Z 2
2−j
= S. (4.144)
8 + 14 j
Next, we note that

I1
y12 = . (4.145)
V2
V1 =0
Consider Fig. 4.55. Define
Z 3 = Z L R
Z L R
=
Z L + R
16 j
= . (4.146)
2 + 8j

Let
Z 4 = Z C + Z 3
4 + 7j
= . (4.147)
1 + 4j
Now
V2
I2 =
Z 4
1 + 4j
= V2 · . (4.148)
4 + 7j
Moreover
R
− I1 = I2 ·
Z L + R
V2
= (4.149)
4 + 7j
where we have substituted from (4.148). Therefore
1
y12 = − S. (4.150)
4 + 7j
Next, we have

I2
y21 = . (4.151)
V1
V2 =0
Consider Fig. 4.54. Note that
V1
I1 =
Z 2
R
− I2 = I1 ·
R + Z C

V1
=
4 + 7j
−1
⇒ y21 = S
4 + 7j
= y12 . (4.152)
Finally

I2
y22 = . (4.153)
V2
V1 =0
Consider Fig. 4.55. Clearly
y22 = 1/ Z 4
1 + 4j
= S. (4.154)
4 + 7j
Since
y12 = y21 (4.155)
the network is reciprocal.

27. For the circuit given in Fig. 4.56, find the admittance parameters. It is given that ω = 1
rad/sec. Is the network reciprocal? Justify your answer.
– Solution: Consider the circuit shown in Fig. 4.56. Recall that the admittance param-
eters are given by
I1 = y11 V1 + y12 V2

I2 = y21 V1 + y22 V2 . (4.156)
Define
Z C = 1/(j ωC)
= −2 j
Z L = j ωL
= 2 j . (4.157)

Now

I1
y11 = . (4.158)
V1 V2 =0
Consider Fig. 4.57. Let
Z 1 = Z C Z L
Z C Z L
=
Z C + Z L
= ∞ . (4.159)
Let
Z 2 = Z 1 + R
= ∞ . (4.160)
Therefore
y11 = 1/ Z 2
= 0 S. (4.161)
Next, we note that

I1
y12 = . (4.162)
V2 V1 =0
Consider Fig. 4.58. Define

Z 3 = Z L R
Z L R
=
Z L + R
6j
= . (4.163)
3+2j
Let
Z 4 = Z C + Z 3
4
= . (4.164)
3+2j
Now
V2
I2 =
Z 4
3+2j
= V2 · . (4.165)
4
Moreover
Z L
− I1 = I2 ·
Z L + R
= V2 × 0.5 j (4.166)
where we have substituted from (4.165). Therefore
y12 = −0.5 j S. (4.167)
Next, we have

I2
y21 = . (4.168)
V1
V2 =0
Consider Fig. 4.57. Note that
V1
I1 =
Z 2
=0

⇒ Vab = V1
⇒ I2 = Vab / Z L
= V1 / Z L
⇒ y21 = −0.5 j S
= y12 . (4.169)
Finally

I2
y22 = . (4.170)
V2
V1 =0
Consider Fig. 4.58. Clearly
y22 = 1/ Z 4
3+2j
= S. (4.171)
4
Since
y12 = y21 (4.172)
the network is reciprocal.

Diode Circuits
5
1. Draw Vo versus Vi for the circuit in Fig. 5.1. Assume ideal diode.
– Solution: Consider Fig. 5.1. We have the following situations.
(a) Let D be OFF. This implies that
Vo = 3 V
Vi < 3 V. (5.1)
(b) Next we assume D is ON. The resulting circuit is shown in Fig. 5.2a.
Applying KVL we get:
Vi − I − 3 − 2I = 0
⇒ I = Vi /3 − 1 mA > 0
⇒ Vi > 3 V. (5.2)
Hence
Vo = 2Vi /3 + 1. (5.3)
The plot of Vo versus Vi is shown in Fig. 5.2b.
2. Draw Vo versus Vi for the circuit in Fig. 5.3. Assume ideal diode.
– Solution: We have the following situations.

https://doi.org/10.1007/978-3-031-09363-0_5
164 5 Diode Circuits
Fig. 5.1 Diode circuit 1k D

Vi
Vo
+ 3V
2k
Fig. 5.2 Diode circuit 1k

Vi I
(a) Vo
+ 3V
2k
(b) Vo (volt)
3 2Vi /3 + 1
Vi (volt)
0 3
Fig. 5.3 Diode circuit 3k D

Vi Vo
+ 4V
2k
5 Diode Circuits 165

Vi I
(a) Vo
+ 4V
2k
(b) Vo (volt)
12/5
Vi (volt)
−6 0 4
Vo = 4 V
Vi > 4 V. (5.4)
(b) Next we assume D is ON.

The resulting circuit is shown in Fig. 5.4a. We have:
Vo − Vi 0 − (Vo − 4)
I = =
3 2
12 2Vi
⇒ Vo = + . (5.5)
5 5
3. Draw Vo versus Vi for 0 ≤ Vi ≤ 8 V for the circuit in Fig. 5.5. Assume ideal diode.

Fig. 5.5 Diode circuit 1k 3k

Vi
Vo
−
D
2V
+
4V
−
2k
Vo = Vi − 2 V
⇒ Vo > 4 V
⇒ Vi > 6 V. (5.6)
(b) Next we assume D is ON. The resulting circuit is shown in Fig. 5.6a. We have:
− 2I + 4 − 3I + 2 − I = Vi
6 − Vi
⇒I = . (5.7)
6
Therefore
Vo = −2I + 4
= 2 + Vi /3. (5.8)
4. Draw Vo versus Vi for 3 ≤ Vi ≤ 14 V for the circuit in Fig. 5.7. Assume ideal diode.

Fig. 5.6 Diode circuit 1k I 3k

Vi
(a) Vo
+
−
4V
2V
−
2k
(b) Vo (volt)
2
Vi (volt)
0 6 8
Fig. 5.7 Diode circuit 5k 4k

Vi
Vo
+
D
3V
+
1V
−
1k
Vo = Vi − 3 V
⇒ Vo < 1 V
⇒ Vi < 4 V. (5.9)
Fig. 5.8 Diode circuit 5k I 4k

Vi
(a) Vo
+
−
1V
3V
1k
(b) Vo (volt)
1
Vi (volt)
0 3 4 14
(b) Next we assume D is ON. The resulting circuit is shown in Fig. 5.8a. We have:
Vi − 5I − 3 − 4I − 1 − I = 0
Vi − 4
⇒I = . (5.10)
10
Therefore
Vo = Vi − 5I − 3 − 4I
Vi + 6
= . (5.11)
10
5. Find (there is no need to draw) Vo versus Vi for the circuit in Fig. 5.9. Assume cut-in
voltage of the zener to be 1 V and the breakdown voltage to be 7 V. The maximum
forward bias current through the zener is 3 mA, and the maximum reverse bias current
through the zener is 5 mA. The resistance of the zener when it is conducting is zero.
Assume the knee current to be zero.
Hence find the range of Vi that can be applied.

Fig. 5.9 Zener circuit 5V

1k
+
Vi Vo
6k

1k If
+
Vi Vo
−
1V
+
6k
(a) Z is forward biased. The resulting circuit is shown in Fig. 5.10. We have:
− 6I f − 1 − 5 − I f = Vi
−6 − Vi
⇒ If = >0
7
⇒ Vi < −6 V. (5.12)
Since
I f , max = 3 mA
−6 − Vi
=
7
⇒ Vi = −27 V. (5.13)
We also have
Vo = −6I f − 1
6Vi + 29
= . (5.14)
7
(b) Z is OFF. Clearly
Vo = Vi + 5. (5.15)
(c) Z is reverse biased. The resulting circuit is shown in Fig. 5.11. We have:
Vi − Ir + 5 − 7 − 6Ir = 0
Vi − 2
⇒ Ir = >0
7
⇒ Vi > 2 V. (5.16)
Since
Ir , max = 5 mA
Vi − 2
=
7
⇒ Vi = 37 V. (5.17)
We also have
Vo = Vi − Ir + 5
6Vi + 37
= . (5.18)
7
To summarize:
⎧
⎨ (6Vi + 29)/7 for − 27 ≤ Vi < −6 V
Vo = Vi + 5 for − 6 ≤ Vi ≤ 2 V (5.19)
⎩
(6Vi + 37)/7 for 2 < Vi ≤ 37 V.
The range of Vi is −27 ≤ Vi ≤ 37 V.
forward bias current through the zener is 2 mA, and the maximum reverse bias current
through the zener is 6 mA. The resistance of the zener when it is conducting is zero.
Assume the knee current to be zero.


1k Ir
+
Vi Vo
+
7V
6k

4k
+
Vi Vo
7k
(a) Z is forward biased. The resulting circuit is shown in Fig. 5.13. We have:
Vi − 4I f + 3 − 1 − 7I f = 0
Vi + 2
⇒ If = >0
11
⇒ Vi > −2 V. (5.20)
Since
I f , max = 2 mA
Vi + 2
=
11
⇒ Vi = 20 V. (5.21)
We also have

4k If
+
Vi Vo
1V
+
7k
Vo = Vi − 4I f + 3
7Vi + 25
= . (5.22)
11
(b) Z is OFF. Clearly
Vo = Vi + 3. (5.23)
(c) Z is reverse biased. The resulting circuit is shown in Fig. 5.14. We have:
− 7Ir − 5 − 3 − 4Ir = Vi
−(Vi + 8)
⇒ Ir = >0
11
⇒ Vi < −8 V. (5.24)
Since
Ir , max = 6 mA
−(Vi + 8)
=
11
⇒ Vi = −74 V. (5.25)
We also have
Vo = −7Ir − 5
7Vi + 1
= . (5.26)
11
To summarize:

4k Ir
+
Vi Vo
−
5V
+
7k

Vi Vo
2k 3k
D1 D2
+ +
3V 5V
− −
⎧
⎨ (7Vi + 25)/11 for − 2 < Vi ≤ 20 V
Vo = Vi + 3 for − 8 ≤ Vi ≤ −2 V (5.27)
⎩
(7Vi + 1)/11 for − 74 ≤ Vi < −8 V.
voltage of the diodes to be 1 V. The maximum forward bias currents through D1 and D2
are 4 mA and 6 mA respectively. The resistance of the diodes when they are conducting
is zero.
(a) D1 and D2 are OFF. In this case

Fig. 5.16 Diode circuit 1k If 1

Vi Vo
2k
−
1V
+
+
3V
Vo = Vi . (5.28)
(b) D1 ON and D2 OFF. The resulting circuit is shown in Fig. 5.16. We have:
3 − 1 − 2I f 1 − I f 1 = Vi
2 − Vi
⇒ If1 = >0
3
⇒ Vi < 2 V. (5.29)
Since
I f 1, max = 4 mA
2 − Vi
=
3
⇒ Vi = −10 V. (5.30)
We also have
Vo = Vi + I f 1
2Vi + 2
= . (5.31)
3
(c) D1 OFF and D2 ON. The resulting circuit is shown in Fig. 5.17. We have:
Vi − I f 2 − 3I f 2 − 1 − 5 = 0
Vi − 6
⇒ If2 = >0
4
⇒ Vi > 6 V. (5.32)
Since

Vi Vo
3k
+
1V
−
+
5V

Vi Vo
If 1 If 2
2k 3k
−
+
1V 1V
+
+ −
+
3V 5V
− −
I f 2, max = 6 mA
Vi − 6
=
4
⇒ Vi = 30 V. (5.33)
We also have
Vo = Vi − I f 2
3Vi + 6
= . (5.34)
4
(d) D1 ON and D2 ON. The resulting circuit is shown in Fig. 5.18. We have
Vo = 3 − 1 − 2I f 1
= 5 + 1 + 3I f 2
⇒ 2I f 1 + 3I f 2 = −4. (5.35)
However, since I f 1 > 0 and I f 2 > 0, (5.35) is not possible.

Therefore D1 ON and D2 ON is not possible.
To summarize:
⎧
⎨ (3Vi + 6)/4 for 6 < Vi ≤ 30 V
Vo = Vi for 2 ≤ Vi ≤ 6 V (5.36)
⎩
(2Vi + 2)/3 for − 10 ≤ Vi < 2 V.
voltage of the diodes to be 1 V. The maximum forward bias currents through D1 and D2
are 3 mA and 5 mA respectively. Hence find the range of Vi that can be applied.
(a) D1 and D2 are OFF. In this case
Vo = Vi . (5.37)
(b) D1 ON and D2 OFF. The resulting circuit is shown in Fig. 5.20. We have:

Vi Vo
D1 D2
7k 3k
− −
2V 4V
+ +

Vi Vo
−
1V
+
7k
−
2V
+
− 2 − 7I f 1 − 1 − 6I f 1 = Vi
−(3 + Vi )
⇒ If1 = >0
13
⇒ Vi < −3 V. (5.38)
Since
I f 1, max = 3 mA
−(3 + Vi )
=
13
⇒ Vi = −42 V. (5.39)
We also have
Vo = Vi + 6I f 1
7Vi − 18
= . (5.40)
13
(c) D1 OFF and D2 ON. The resulting circuit is shown in Fig. 5.21. We have:
Vi − 6I f 2 − 1 − 3I f 2 + 4 = 0
Vi + 3
⇒ If2 = >0
9
⇒ Vi > −3 V. (5.41)
Since

Vi Vo
+
1V
−
3k
−
4V
+

Vi Vo
−
+
+
−
7k 3k
If 1 − If 2 −
2V 4V
+ +
I f 2, max = 5 mA
Vi + 3
=
9
⇒ Vi = 42 V. (5.42)
We also have
Vo = Vi − 6I f 2
3Vi − 18
= . (5.43)
9
(d) D1 ON and D2 ON. The resulting circuit is shown in Fig. 5.22. We have
Fig. 5.23 Power supply D i(t)

v(t)
100 Ω
Vo = −2 − 7I f 1 − 1
= −4 + 3I f 2 + 1
⇒ 7I f 1 + 3I f 2 = 0. (5.44)
However, since I f 1 > 0 and I f 2 > 0, (5.44) is not possible.

Therefore D1 ON and D2 ON is not possible.
To summarize:
⎧
⎨ (7Vi − 18)/13 for − 42 ≤ Vi < −3 V
Vo = Vi for Vi = 3 V (5.45)
⎩
(3Vi − 18)/9 for − 3 < Vi ≤ 42 V.
9. Find the average current (Idc ) for the circuit shown in Fig. 5.23. It is given that the cut-in
voltage of the diode is 1 V and the forward resistance is 50 . The applied voltage is
v(t) = 2 sin(ω0 t). Indicate the direction of Idc .
(a) D is OFF. In this case
i(t) = 0. (5.46)
(b) D ON. The resulting circuit is shown in Fig. 5.24. We have:
v(t) − 1 − 150i(t) = 0
v(t) − 1
⇒ i(t) = >0
150
⇒ v(t) > 1 V. (5.47)
Since i(t) is periodic

i(t)
v(t)
−
50 Ω
1V
100 Ω
Fig. 5.24 Diode circuit
Fig. 5.25 Diode circuit 2
1.5
0.5
ω0 t
v(t)
0
t1 t2
-0.5
-1
-1.5
-2
0 1 2 3 4 5 6
T0
1
Idc = i(t) dt (5.48)
T0 t=0
where
ω0 = 2π/T0 . (5.49)
Since i(t) is non-zero for t1 ≤ t ≤ t2 as illustrated in Fig. 5.25, we have

t2
1
Idc = i(t) dt
T0 t=t1
= 1.4533 mA. (5.50)
The direction of Idc is identical to that of i(t).
10. Find the average current (Idc ) for the circuit shown in Fig. 5.26. It is given that the cut-in
voltage of the diode is 1 V and the forward resistance is 50 . The applied voltage is
v(t) = 2 sin(ω0 t). Indicate the direction of Idc .

(a) D is OFF. In this case
i(t) = 0. (5.51)
(b) D ON. The resulting circuit is shown in Fig. 5.27. We have:
v(t) + 1 + 100i(t) = 0
−(v(t) + 1)
⇒ i(t) = >0
100
⇒ v(t) < −1 V. (5.52)
Since i(t) is periodic

T0
1
Idc = i(t) dt (5.53)
T0 t=0
where
ω0 = 2π/T0 . (5.54)
Since i(t) is non-zero for t1 ≤ t ≤ t2 as illustrated in Fig. 5.28, we have

t2
1
Idc = i(t) dt
T0 t=t1
= 2.18 mA. (5.55)
Fig. 5.26 Power supply D i(t)

v(t)
50 Ω
Fig. 5.27 Diode circuit i(t)

−
v(t)
50 Ω
1V
50 Ω
Fig. 5.28 Diode circuit 2
1.5
0.5
t1 t2 ω0 t
v(t)
0
-0.5
-1
-1.5
-2
0 1 2 3 4 5 6
Fig. 5.29 Power supply i(t)

vi (t) vo (t)
D
+
R C
−
The direction of Idc is identical to that of i(t).
11. The peak current through the diode in Fig. 5.29 is 4 A and R = 100 . Find C, the
average current (Idc ) through R (neglecting the ripple voltage) and the ripple voltage
(Vr ). The applied voltage is vi (t) = Vm sin(ω0 t), with Vm = 10 V and frequency 400
Hz. Assume ideal diode.
– Solution: Consider Figs. 5.29 and 5.30.
The average current through R (in the downward direction) is
Idc ≈ Vm /R
= 0.1 A. (5.56)
The peak diode current (I D, max = 4 A) for a half-wave rectifier is given by:

I D, max = Idc (1 + 2π 2Vm /Vr )
⇒ Vr = 0.519 V. (5.57)
The direction of I D, max is identical to the direction of i(t) in Fig. 5.29. Again, for a half-wave
rectifier:
Fig. 5.30 Power supply Vr
10
8 vo (t)
6
4 vi (t)
2
0 ω0 t
-2 ≈ T0
-4
D OFF D ON
i(t) = 0 i(t) = 0
-6
-8
-10
0 2 4 6 8 10 12
Fig. 5.31 Power supply i(t)

vi (t) vo (t)
D
−
R C
+
Vm Vm T0
Vr = =
f 0 RC RC
⇒ C = 481.6 µF. (5.58)
12. The peak current rating of the diode in Fig. 5.31 is 5 A and R = 150 . Find C, the
Hz. Assume ideal diode.
– Solution: Consider Figs. 5.31 and 5.32. The average current through R (in the upward
direction) is
Idc ≈ Vm /R
= 0.1 A. (5.59)
The peak diode current (I D, max = 5 A) for a half-wave rectifier is given by:
Fig. 5.32 Power supply 15
10
i(t) = 0
D ON
5 vi (t) i(t) = 0
D OFF
≈ T0 ω0 t
0
-5
-10
vo (t)
-15
0 2 4 6 8 10 12
Vr

I D, max = Idc (1 + 2π 2Vm /Vr )
⇒ Vr = 0.49327 V. (5.60)
The direction of I D, max is identical to the direction of i(t) in Fig. 5.31. Again, for a
half-wave rectifier:
Vm Vm T0
Vr = =
f 0 RC RC
⇒ C = 506.8 µF. (5.61)
13. The peak current through the diodes in Fig. 5.33 is 3 A and R = 100 . Find C, the
Hz. Assume ideal diodes.
– Solution: Consider Figs. 5.33 and 5.34. The average current through R (in the downward
direction) is
Idc ≈ Vm /R
= 0.06 A. (5.62)
The peak diode current (I D, max = 3 A) for a full-wave rectifier is given by:

I D, max = Idc (1 + 2π Vm /2Vr )
⇒ Vr = 0.049 V. (5.63)
Fig. 5.33 Power supply D1 i(t)

vi (t) vo (t)
+
R C
−vi (t)
D2 −
Fig. 5.34 Power supply vo (t)
5 |vi (t)|
4 ≈ T0 /2 D1 ON
D1, D2 OFF D2 OFF
3
2 D2 ON
D1 OFF
1
D1, D2 OFF
0 ω0 t
0 2 4 6 8 10 12
The direction of I D, max is identical to the direction of i(t) in Fig. 5.33. Again, for a full-wave
rectifier:
Vm Vm T0
Vr = =
2 f 0 RC 2RC
⇒ C = 1520.5 µF. (5.64)
14. The peak current rating of the diodes in Fig. 5.35 is 3 A and R = 200 . Find C, the
Hz. Assume ideal diodes.
– Solution: Consider Figs. 5.35 and 5.36. The average current through R (in the upward
direction) is
Idc ≈ Vm /R
= 0.06 A. (5.65)
Fig. 5.35 Power supply D1 i(t)

vi (t) vo (t)
−
R C
−vi (t)
D2 +
Fig. 5.36 Power supply 0
-2
≈ T0 /2
vi (t) D1, D2 OFF
-4
D1 ON, D2 OFF
-6
-8
≈ T0 /2
D1 OFF, D2 ON
D1, D2 OFF
-10
-12
0 2 4 6 8 10 12
vo (t) Vr
The peak diode current (I D, max = 3 A) for a full-wave rectifier is given by:

I D, max = Idc (1 + 2π Vm /2Vr )
⇒ Vr = 0.098 V. (5.66)
The direction of I D, max is identical to the direction of i(t) in Fig. 5.35. Again, for a
full-wave rectifier:
Vm Vm T0
Vr = =
2 f 0 RC 2RC
⇒ C = 760.2 µF. (5.67)
forward bias current rating (I Z , f , max ) of the zener is 5 mA, and the maximum reverse
bias current rating (I Z , r , max ) of the zener is 8 mA. The resistance of the zener when it
is conducting is zero. The zener knee current is also zero. The diode can be assumed
Fig. 5.37 Zener circuit 1k

Vi Vo
−
4V
2k
to have zero cut-in voltage and zero forward resistance. The peak current rating of the
diode (I D, max ) is 10 mA.
(a) I = 0 . Clearly
Vo = Vi − 4. (5.68)
(b) I > 0. Then D must be ON and Z must be in the breakdown region. The resulting
circuit is shown in Fig. 5.38. We have:
Vi − I − 4 − 3 − 2I = 0
Vi − 7
⇒I = >0
3
⇒ Vi > 7 V. (5.69)
Now
Imax = min{I D, max , I Z , r , max }

= min{8, 10}
= 8 mA. (5.70)
Since

Vi I Vo
−
4V +
3V
−
2k
Imax = 8 mA
Vi − 7
=
3
⇒ Vi = 31 V. (5.71)
We also have
Vo = 3 + 2I
2Vi − 5
= . (5.72)
3
To summarize:

(2Vi − 5)/3 for 7 < Vi ≤ 31 V
Vo = (5.73)
Vi − 4 for Vi ≤ 7 V
The range of Vi is −∞ < Vi ≤ 31 V.
forward bias current rating (I Z , f , max ) of the zener is 4 mA, and the maximum reverse
bias current rating (I Z , r , max ) is 6 mA. The resistance of the zener when it is conducting
is zero. The zener knee current is also zero. The diode has a cut-in voltage of 1 V and
zero forward resistance. The peak current rating of the diode (I D, max ) is 2 mA.


Vi
Vo
−
D
2V
3k
(a) I = 0 . Clearly
Vo = Vi − 2. (5.74)
(b) I > 0. Then D must be ON and Z must be in the breakdown region. The resulting
circuit is shown in Fig. 5.40. We have:
− 3I − 5 − 1 + 2 − I = Vi
−Vi − 4
⇒I = >0
4
⇒ Vi < −4 V. (5.75)
Now
Imax = min{I D, max , I Z , r , max }

= min{2, 6}
= 2 mA. (5.76)
Since
Imax = 2 mA
−Vi − 4
=
4
⇒ Vi = −12 V. (5.77)
We also have

Vi I
Vo
−
−
2V
1V
+
−
5V
+
3k
Vo = −3I − 5 − 1
3Vi − 12
= . (5.78)
4
To summarize:

Vi − 2 for Vi ≥ −4 V
Vo = (5.79)
(3Vi − 12)/4 for − 12 ≤ Vi < −4 V
The range of Vi is −12 < Vi < ∞ V.
17. Consider the voltage regulator circuit in Fig. 5.41. Assume that v(t) = 12 cos(100π t)
and I1 can be neglected compared to I R . The maximum instantaneous power rating of
the zener is 64 mW, at a zener current I Z = 10 mA. The knee current is I Z K = 2 mA
and VZ 0 = 6 V.
(a) Find the average value of Vi (Vdc ) and the maximum variation on either side of Vdc .
No derivation is required.
(b) Derive and compute the line regulation.
(c) Derive and compute the load regulation.
(d) Assuming that Vi is fixed at the maximum value computed in part (a), what is the
minimum value of R L for which the zener operates in the breakdown region?
– Solution:
D1
R1 = 1 k
v(t) Vi I1 Vo IL
D2
Z
−v(t) R = 50 Ω
RL
C = 1000 μF +
IR IZ
−
Fig. 5.41 Zener circuit
(a) We know that the ripple voltage at the output of the full-wave rectifier is:
Vp
Vr =
2 f RC
= 2.4 V (5.80)
where
V p = 12 V
f = 50 Hz. (5.81)
Therefore
Vr
Vdc = V p − V
2
= 10.8 V. (5.82)
The variation on either side of Vdc is ±1.2 V. Next, we need to find out the zener
resistance r z . Refer to Fig. 5.42.
We have:
PZ , max = VZ 0 I Z , max + I Z2 , max r z

⇒ r z = 40 (5.83)
where we have substituted
PZ ,max = 64 mW
I Z , max = 10 mA
VZ 0 = 6 V. (5.84)
(b) The line regulation is defined as:

D1
R1 = 1 k
v(t) Vi I1 Vo IL
D2
IZ
−v(t) R = 50 Ω
+
RL
VZ0
C = 1000 μF + −
IR
−
rz

d Vo
(5.85)
d Vi R L →∞
When R L → ∞, I1 = I Z and we have:
Vi − I Z R1 − VZ 0 − I Z r z = 0
Vi − VZ 0
⇒ IZ = (5.86)
R1 + r z
Therefore
Vo = VZ 0 + I Z r z
Vi − VZ 0
= VZ 0 + rz . (5.87)
R1 + r z
Hence, the line regulation is

d Vo rz
=
d Vi R L →∞ R1 + r z
= 0.03846 V/V
= 38.46 mV/V. (5.88)
This means that if Vi increases by 1 V, Vo increases by 38.46 mV.

(c) The load regulation is defined as:
d Vo
(5.89)
d IL
when R L is present and Vi is kept constant. Note that
I1 = I L + I Z
Vi − Vo Vo − VZ 0
⇒ = + IL
R1 rz
d Vo −r z R1
⇒ =
d IL R1 + r z
≈ −r z
= −40 mV/mA. (5.90)
This means that if I L increases by 1 mA, Vo decreases by 40 mV, when Vi is kept

constant.
(d) Note that
Vo, min
R L, min = . (5.91)
I L, max
However
Vo, min = VZ 0 + I Z K r z
= 6.08 V (5.92)
and
Vi − Vo, min
I1, max =
R1
= 12 − 6.08
= 5.92 mA. (5.93)
Now
I L, max = I1, max − I Z K

= 3.92 mA. (5.94)
Therefore
R L, min = 6.08/3.92 = 1.551 k . (5.95)
18. A zener is operating in the breakdown region. When the zener current is 1 mA, the
voltage across the zener is 6 V. When the zener current is 6 mA, the voltage across the
zener is 6.4 V. Find the model for the zener diode. If the knee current is 0.5 mA, find the
knee voltage. Assume piecewise linear characteristics of the zener in the breakdown
region.
i
(a) −
i = −IZ
−VZK −VZ0
v v = −VZ
A −IZK
+
(b)
+
VZ0
rz
– Solution: Consider Fig. 5.43a. It is given that the zener is operating in the breakdown
region. Observe that VZ 0 is the point of intersection of the line AB on the x-axis. The
equation of the line AB is of the form
i = mv + c (5.96)
where
−1 − (−6)
m=
−6 − (−6.4)
= 12.5
i
=
v
1
=
rz
⇒ rz = 0.08 k. (5.97)
Therefore
c = −1 − 12.5 × (−6)
= 74. (5.98)
Hence
− VZ 0 = −c/m
= −5.92 V. (5.99)
The model for the zener diode is shown in Fig. 5.43b. Finally
−0.5 − c
− VK =
m
= −5.96 V. (5.100)
19. A zener is operating in the breakdown region. When the zener current is 2 mA, the
voltage across the zener is 8 V. When the zener current is 6 mA, the voltage across the
zener is 8.2 V. Find the model for the zener diode. If the knee current is 1 mA, find the
knee voltage. Assume piecewise linear characteristics of the zener in the breakdown
region.
– Solution: Consider Fig. 5.44a. It is given that the zener is operating in the breakdown
region. Observe that VZ 0 is the point of intersection of the line AB on the x-axis. The
equation of the line AB is of the form
i = mv + c (5.101)
where
−2 − (−6)
m=
−8 − (−8.2)
= 20
i
=
v
1
=
rz
⇒ rz = 0.05 k. (5.102)
Therefore
i
(a) −
i = −IZ
−VZK −VZ0
v v = −VZ
A −IZK
+
(b)
+
VZ0
rz
c = −2 − 20 × (−8)
= 158. (5.103)
Hence
− VZ 0 = −c/m
= −7.9 V. (5.104)
The model for the zener diode is shown in Fig. 5.44b. Finally
−1 − c
− VK =
m
= −7.95 V. (5.105)
Bipolar Junction Transistors
6
1. Determine whether the npn transistor in Fig. 6.1 is in active region or saturation. Hence,
find I B , IC and VC E .
Assume VB E = 0.7 V when the transistor is in active or saturation and VC E = 0.2 V
when it is in saturation.
– Solution: Consider Fig. 6.1. We have the following situations:
(a) Assume that the transistor is in the cut-off region. Then VB E = 10 V, which is
not possible.
(b) Assume that the transistor is in active region. Hence, VB E = 0.7 V and IC = β I B .
However, from Fig. 6.2
VCC − VB E
IB =
RB
10 − 0.7
=
300
= 0.031 mA
⇒ IC = 3.1 mA. (6.1)
Therefore
VC E = 10 − RC IC
= 3.8 V
> 0.2 V. (6.2)
Therefore, the transistor is in active region and it cannot be in saturation.

https://doi.org/10.1007/978-3-031-09363-0_6
198 6 Bipolar Junction Transistors
Fig. 6.1 Transistor biasing VCC = 10 V
RB = 300 k RC = 2 k
β = 100
RB = 300 k RC = 2 k
IC
IB +
VCE
−
β = 100
2. Determine whether the pnp transistor in Fig. 6.3 is in active region or saturation. Hence,
find I B , IC and VC E .
Assume VB E = −0.7 V when the transistor is in active or saturation and VC E =
−0.2 V when it is in saturation.
– Solution: We have the following situations:
(a) Assume that the transistor is in the cut-off region. Then VB E = −12 V, which is
not possible.
(b) Assume that the transistor is in active region. Hence, VB E = −0.7 V and IC =
β I B . However, from Fig. 6.4
VB E − VCC
IB =
RB
−0.7 − (−12)
IB =
400
= 0.02825 mA
⇒ IC = 2.11875 mA. (6.3)
6 Bipolar Junction Transistors 199
Fig. 6.3 Transistor biasing VCC = −12 V
RB = 400 k RC = 4 k
β = 75
RB = 400 k RC = 4 k
IC
IB +
VCE
−
β = 75
Therefore
VC E − RC IC = VCC
⇒ VC E = −3.525 V
< −0.2 V. (6.4)
Therefore, the transistor is in active region and it cannot be in saturation.
3. Determine R B and I B in Fig. 6.5. It is given that VC E = 4 V.

Assume VB E = 0.7 V when the transistor is in active region or saturation.
– Solution: Consider Fig. 6.5. Since VC E = 4 V, the transistor is in the active region.
Hence, IC = β I B and I E = (β + 1)I B . Applying KVL in the base–emitter loop, we
get
RC = 1 k
RB
+
IB
VCE = 4 V
−
β = 20
RE = 1 k
VCC − I E RC − I B R B − 0.7 − I E R E = 0
⇒ 12 − (β + 1)I B (RC + R E ) − I B R B − 0.7 = 0
11.3
⇒ IB = .
21(RC + R E ) + R B
(6.5)
Applying KVL in the collector–emitter loop, we get
VCC − I E RC − VC E − I E R E = 0
⇒ I E = 4 mA
21 × 11.3
⇒ 21I B =
21(RC + R E ) + R B
= 4 mA
⇒ I B = 0.1904762 mA
R B = 17.325 k. (6.6)
4. Determine R B and I B in Fig. 6.6. It is given that VC E = −4 V.

Assume VB E = −0.7 V when the transistor is in active region or saturation.
• Solution: Since VC E = −4 V, the transistor is in the active region. Hence, IC = β I B

and I E = (β + 1)I B .
Applying KVL in the base–emitter loop, we get
RC = 2 k
RB
+
IB
VCE = −4 V
−
β = 10
RE = 1 k
− I E R E + VB E − I B R B − I E RC = VCC
−I E − 0.7 − I B R B − 2I E = −10
⇒ −33I B − 0.7 − I B R B = −10
9.3
⇒ IB = . (6.7)
33 + R B
Applying KVL in the collector–emitter loop, we get
− I E R E + VC E − I E RC = VCC
−I E − 4 − 2I E = −10
⇒ I E = 2 mA
11 × 9.3
⇒ IE =
33 + R B
= 2 mA
⇒ R B = 18.15 k
I B = 0.1818182 mA. (6.8)
5. Determine I B and VC E in Fig. 6.7. State whether the transistor is in cut-off, active region
or saturation.
Assume VB E = 0.7 V when the transistor is in the active region or saturation and
VC E = 0.2 V when it is in saturation.
– Solution: Consider Fig. 6.7. We have the following cases:

R1 = 80 k RC = 2 k
β = 100
R2 = 40 k
RE = 1 k
RC = 2 k
IC
RTH = 80/3 k
β = 100
IB
+ RE = 1 k
VTH = 3 V
−
IE
(a) Assume that the transistor is in cut-off region. Then VB E = 3 V, which is not
possible.
Hence, the transistor cannot be in the cut-off region.
(b) Assume that the transistor is in the active region. Hence, IC = β I B and I E =
(β + 1)I B . Applying Thevenin’s theorem across R2 , we get the resultant circuit
as shown in Fig. 6.8. Applying KVL in the base–emitter loop
VTH − RTH I B − VBE − (β + 1)I B R E = 0

⇒ I B = 0.0180157 mA. (6.9)
Applying KVL in the collector–emitter loop

VCC − β I B RC − VC E − (β + 1)I B R E = 0
⇒ VC E = 3.5772846 V.
(6.10)
Since VC E > 0.2 V, the transistor is in active region, and therefore, cannot be in
saturation.
6. Determine I B and VC E in Fig. 6.9. State whether the transistor is in the active region
or saturation.
Assume VB E = −0.7 V when the transistor is in the active region or saturation and
VC E = −0.2 V when it is in saturation.
– Solution: We have the following cases:
(a) Assume that the transistor is in active region. Hence, IC = β I B and I E = (β +

1)I B . Applying Thevenin’s theorem across R2 , we get the resultant circuit as
shown in Fig. 6.10. Applying KVL in the base–emitter loop
VTH + I B RTH − VBE + (β + 1)I B R E = 0

⇒ I B = 0.0140227 mA.
(6.11)
RC = 3 k
R1 = 100 k
β = 100
R2 = 50 k RE = 2 k
RC = 3 k
RTH = 100/3 k IC
β = 100
IB
+
VTH = −4 V
− RE = 2 k
IE
− (β + 1)I B R E + VCE − RC β I B = VCC

⇒ VC E = −4.9606232 V.
(6.12)
Since VC E < −0.2 V, the transistor is in active region, and therefore, cannot be
in saturation.
or saturation.

VTH − I B RTH − VBE − (β + 1)I B R E = 0

⇒ I B = 0.1034664 mA.
(6.13)

R1 = 100 k RC = 3 k
β = 100
R2 = 60 k
RE = 0.1 k
RC = 3 k
IC
RTH = 300/8 k
β = 100
IB
+ RE = 0.1 k
VTH = 45/8 V
−
IE
VCC − β I B RC − VCE − R E (β + 1)I B = 0

⇒ VC E = −17.084926 V.
(6.14)
Since VC E < 0.2 V, the transistor is not in the active region and hence it must be
in saturation.
(b) Assume that the transistor is in saturation. Hence, VC E = 0.2 V. Applying KVL
in the base–emitter loop, we have
VTH − I B RTH − VBE − (I B + IC )R E = 0

⇒ −0.1IC − 37.6I B + 4.925 = 0. (6.15)
RC = 2 k
R1 = 90 k
β = 100
R2 = 50 k RE = 0.15 k
Applying KVL in the collector–emitter loop, we have
VCC − IC RC − VCE − R E (I B + IC ) = 0
⇒ −3.1IC − 0.1I B + 14.8 = 0. (6.16)
I B = 0.1182969 mA
IC = 4.7703775 mA. (6.17)
Since
IC
= 40.325476 < β (6.18)
IB
it is confirmed that the transistor is indeed in saturation.
or saturation.
Assume VB E = −0.7 V when the transistor is in active region or saturation and VC E =

RC = 2 k
RTH = 450/14 k IC
β = 100
IB
+
VTH = −55/14 V
− RE = 0.15 k
IE
VTH + I B RTH − VBE + (β + 1)I B R E = 0

⇒ I B = 0.0682676 mA.
(6.19)
− (β + 1)I B R E + VCE − RC β I B = VCC

⇒ VC E = 3.6877813 V.
(6.20)
Since VC E > −0.2 V, the transistor is not in the active region and hence it must
be in saturation.
(b) Assume that the transistor is in saturation. Hence, VC E = −0.2 V. Applying
KVL in the base–emitter loop, we have
VTH + I B RTH − VBE + (I B + IC )R E = 0

450 55
⇒ 0.15IC + + 0.15 I B − + 0.7 = 0. (6.21)
14 14
− (I B + IC )R E + VCE − RC IC = VCC
⇒ −2.15IC − 0.15I B + 10.8 = 0
⇒ 2.15IC + 0.15I B − 10.8 = 0. (6.22)

RB = 45 k RC = 6 k
β = 80
RE = 3 k
I B = 0.0766698 mA
IC = 5.0179068 mA. (6.23)
Since
IC
= 65.448322 < β (6.24)
IB
9. Determine I B and IC in Fig. 6.15. State whether the transistor is in the cut-off, active
or saturation region.
Assume VB E = 0.7 V when the transistor is in active region or saturation and VC E =
0.2 V when it is in saturation.
– Solution: Consider Fig. 6.15. We have the following cases:
(a) Assume that the transistor is cut-off. Then VB E = 11 V, which is not possible.
Hence, the transistor cannot be cut-off.
(b) Assume that the transistor is in active region. Hence, IC = β I B and I E = (β +
1)I B . Applying KVL in the base–emitter loop (see Fig. 6.16)
VCC − I B R B − VBE − (β + 1)I B R E = 0

⇒ I B = 0.0357639 mA.
(6.25)

RB = 45 k RC = 6 k
IC
IB +
VCE
−
β = 80
IE
RE = 3 k
VCC − β I B RC − VCE − R E (β + 1)I B = 0

⇒ VC E = −14.857292 V.
(6.26)
Since VC E < 0.2 V, the transistor is not in the active region and hence it must be
in saturation.
(c) Assume that the transistor is in saturation. Hence, VC E = 0.2 V. Applying KVL
in the base–emitter loop, we have
VCC − I B R B − VBE − (I B + IC )R E = 0
⇒ 10.3 − 3IC − 48I B = 0. (6.27)
Applying KVL in the collector–emitter, loop we have
VCC − IC RC − VCE − R E (I B + IC ) = 0
⇒ 10.8 − 9IC − 3I B = 0. (6.28)
I B = 0.1425532 mA
IC = 1.1524823 mA. (6.29)
Since
IC
= 8.0845771 < β (6.30)
IB
RB = 55 k RC = 7 k
β = 90
RE = 2 k
10. Determine I B and IC in Fig. 6.17. State whether the transistor is in the active region or
saturation.
(a) Assume that the transistor is in the active region. Hence, IC = β I B and I E =
(β + 1)I B . Applying KVL in the base–emitter loop (see Fig. 6.18)
− I E R E + VBE − I B R B = VCC
⇒ I B = 0.0392405 mA.
(6.31)
− I E R E + VCE − RC IC = VCC
⇒ VC E = 21.863291 V.
(6.32)
Since VC E > −0.2 V, the transistor is not in the active region and hence it must
be in saturation.
(b) Assume that the transistor is in saturation. Hence, VC E = −0.2 V. Applying
KVL in the base–emitter loop, we have
RB = 55 k RC = 7 k
IC
IB +
VCE
−
β = 90
RE = 2 k
− (I B + IC )R E + VBE − I B R B = VCC
⇒ 9.3 − 2IC − 57I B = 0. (6.33)
− (I B + IC )R E + VCE − RC IC = 0
⇒ 9.8 − 9IC − 2I B = 0. (6.34)
I B = 0.1259332 mA
IC = 1.0609037 mA. (6.35)
Since
IC
= 8.424337 < β (6.36)
IB
or saturation.
Assume VB E = 0.7 V when the transistor is in active region or saturation and VC E = 0.2
V when it is in saturation.

Fig. 6.19 Transistor biasing VEE = −11 V
RE = 1 k
β = 100
RB = 40 k
Fig. 6.20 Transistor biasing VEE = −11 V
RE = 1 k
IB −
VCE
+
β = 100
RB = 40 k
IC

1)I B . Applying KVL in the base–emitter loop in Fig. 6.20, we get
− R B I B − VB E − I E R E = VE E
⇒ I B = 0.0730496 mA. (6.37)
− VC E − I E R E = VE E
⇒ VC E = 3.6219858 V. (6.38)
Since VC E > 0.2 V, it is in active region and hence it cannot be in saturation.

Fig. 6.21 Transistor biasing VEE = 8 V
RE = 2 k
β = 90
RB = 80 k
Fig. 6.22 Transistor biasing VEE = 8 V
RE = 2 k
IB −
VCE
+
β = 90
RB = 80 k
IC
or saturation.
Assume VB E = −0.7 V when the transistor is in active region or saturation and VC E =

R B I B − VB E + I E R E = VE E
⇒ I B = 0.0278626 mA. (6.39)
Fig. 6.23 Transistor biasing

β = 100
RE = 1 k RC = 2 k
VEE = −4 V VCC = 9 V
Fig. 6.24 Transistor biasing VCE

− + IC
β = 100
IB
RE = 1 k RC = 2 k
− VC E + I E R E = VE E
⇒ VC E = −2.9290076 V. (6.40)
Since VC E < −0.2 V, it is in active region and hence it cannot be in saturation.
or saturation.
Assume VB E = 0.7 V when the transistor is in active region or saturation and VC E = 0.2
V when it is in saturation.

VE E + I E R E + VB E = 0
⇒ I B = 0.0326733 mA. (6.41)
VCC − IC RC − VC E − I E R E = VE E
⇒ VC E = 3.1653465 V. (6.42)

β = 150
RE = 2 k RC = 3 k
VEE = 5 V VCC = −9 V

IE − + IC
β = 150
RE = 2 k IB RC = 3 k
VEE = 5 V VCC = −9 V
or saturation.

VE E − I E R E + VB E = 0
⇒ I B = 0.0142384 mA. (6.43)
VE E − I E R E + VC E − IC RC = VCC
⇒ VC E = −3.2927152 V. (6.44)
Since VC E < −0.2 V, it is in active region and hence it cannot be in saturation.


β = 150
RE = 1.5 k RC = 2 k
RB = 120 k

− + IC
β = 150
IB
RE = 1.5 k RC = 2 k
RB = 120 k
or saturation.

VE E + I E R E + VB E + I B R B = 0
⇒ I B = 0.0152958 mA. (6.45)
VCC − IC RC − VC E − I E R E = VE E
⇒ VC E = 4.9467532 V. (6.46)

VCC
(a) (b) ib C
R1 RC
B
hie
io +
vi
hf e ib
vo
+ ii
R2 RL
RE
E
Fig. 6.29 Transistor ac analysis
16. Determine the small signal voltage gain Av = vo /vi , input impedance Z i = vi /i i and
the output impedance Z o = vo /i o |vi =0 in Fig. 6.29a. The simplified hybrid model for
the transistor is shown in Fig. 6.29b.
Assume that the transistor is biased in the active region and the impedance of the
capacitors is negligible at the frequency of operation.
– Solution: Consider Fig. 6.29. The equivalent circuit is shown in Fig. 6.30. Note that
RTH = R1 ||R2
R1 R2
=
R1 + R2
Ro = RC ||R L
RC R L
= . (6.47)
RC + R L
We also have
vi − h ie i b − (1 + h f e )i b R E = 0 (6.48)
and
vo = −h f e i b Ro . (6.49)

vi ii B ib C io vo
+ +
RTH
hf e ib
hie Ro = RC ||RL
RE
vo
AV =
vi
−h f e Ro
= . (6.50)
h ie + (1 + h f e )R E
Next, the input impedance is given by

vi
Zi = (6.51)
ii
where vi is the applied voltage. From (6.48), we have
vi
Z i =
ib
= h ie + (1 + h f e )R E . (6.52)
Therefore
Z i = Z i ||RTH
Z RTH
= i . (6.53)
Z i + RTH
Similarly

vo
Zo = (6.54)
i o vi =0
where vo is the applied voltage. We have

− i b h ie − (1 + h f e )i b R E = 0
⇒ i b = 0. (6.55)
Hence
Z o = Ro . (6.56)
– Solution: The equivalent circuit is shown in Fig. 6.32. We have
vi − h ie i b − (1 + h f e )i b R E = 0 (6.57)
and
vo = −h f e i b RC . (6.58)
VCC
ib C
(a) (b)
RB RC
B
io +
vi
vo hf e ib
hie
+ ii
RE
E

vi ii B ib C io vo
+ +
RB
hf e ib
hie RC
RE
vo
AV =
vi
−h f e RC
= . (6.59)
h ie + (1 + h f e )R E

vi
Zi = (6.60)
ii
vi
Z i =
ib
= h ie + (1 + h f e )R E . (6.61)
Therefore
Z i = Z i ||R B
Z RB
= i . (6.62)
Zi + RB
Similarly

vo
Zo = (6.63)
i o vi =0

− i b h ie − (1 + h f e )i b R E = 0
⇒ i b = 0. (6.64)
Hence
Z o = RC . (6.65)
– Solution: Consider Fig. 6.33. The equivalent circuit is shown in Fig. 6.34. We have
vi − h ie i b − (1 + h f e )i b R E = 0 (6.66)
and
vo = (1 + h f e )i b R E . (6.67)

vo
AV =
vi
(1 + h f e )R E
AV = . (6.68)
h ie + (1 + h f e )R E
VEE
(a) (b)
RE B ib C
vo
hie
vi
io + hf e ib
+ ii
RB
E

vi ii B ib C
+
RB
hf e ib
hie
E
vo
io +
RE
i1

vi
Zi = (6.69)
ii
vi
Z i =
ib
= h ie + (1 + h f e )R E . (6.70)
Therefore
Z i = Z i ||R B
Z RB
= i . (6.71)
Zi + RB
Similarly

vo
Zo = (6.72)
i o vi =0
− i b h ie − vo = 0
−vo
⇒ ib = . (6.73)
h ie
Moreover
vo
i1 = . (6.74)
RE
Applying KCL at node E, we get
i o + (1 + h f e )i b = i 1
vo vo
⇒ io = + (1 + h f e )
RE h ie
io 1 1
⇒ = + (1 + h f e )
vo RE h ie
1
= . (6.75)
Zo
– Solution: Refer to Fig. 6.35. The equivalent circuit is shown in Fig. 6.36. We have
− h ie i b = vi (6.76)
and
vo = −h f e i b RC . (6.77)
(a) (b)
vi vo
ib
ii io
B C
RE RC hie
hf e ib
VEE VCC
E

Fig. 6.36 Transistor ac vi ii i1 E C io vo

analysis
+ +
hf e ib
RE hie RC
ib B
vo
Av =
vi
h f e RC
= . (6.78)
h ie
vi
Zi = (6.79)
ii
where vi is the applied voltage. Applying KCL at node E, we have
i 1 + (1 + h f e )i b = 0
⇒ i 1 = −i b (1 + h f e )
vi
⇒ i1 = (1 + h f e ) (6.80)
h ie
where we have used (6.76). Therefore
vi
Z i =
i1
h ie
= . (6.81)
(1 + h f e )
Hence
vi
Zi =
ii
= Z i ||R E
Z RE
= i . (6.82)
Zi + RE
Similarly

vo
Zo = (6.83)
i o vi =0
− i b h ie = 0
⇒ i b = 0. (6.84)
Hence

vo
Zo =
i o vi =0
= RC . (6.85)
capacitors are negligible at the frequency of operation.
– Solution: The equivalent circuit is shown in Fig. 6.38. We have
− (h ie + R B )i b = vi (6.86)
and
vo = −h f e i b RC . (6.87)
(a) (b)
vi vo
ib
ii io
B C
RE RC hie
RB
hf e ib
VEE VCC
E

Fig. 6.38 Transistor ac vi ii i1 E C io vo

analysis
+ +
hf e ib
RE hie RC
ib
B
RB
vo
AV =
vi
h f e RC
= . (6.88)
h ie + R B
vi
Zi = (6.89)
ii
where vi is the applied voltage. Applying KCL at node E, we have
i 1 + (1 + h f e )i b = 0
⇒ i 1 = −i b (1 + h f e )
vi
⇒ i1 = (1 + h f e ) (6.90)
h ie + R B
where we have used (6.86). Therefore
vi
Z i =
i1
h ie + R B
= . (6.91)
(1 + h f e )
Hence
vi
Zi =
ii
= Z i ||R E
Z RE
= i . (6.92)
Zi + RE
Similarly

vo
Zo = (6.93)
i o vi =0
− i b (h ie + R B ) = 0
⇒ i b = 0. (6.94)
Hence

vo
Zo =
i o vi =0
= RC . (6.95)
Op Amp Circuits and Oscillators
7
1. Determine the transfer function H (ω) = Vo /Vs in Fig. 7.1. Assume ideal op amp.
If vs (t) = Vm cos(ωt) (denoted by the phasor Vs ) and RC = 3/ω find vo (t) (denoted
by the phasor Vo ).
– Solution: Consider Fig. 7.1. We have:
V1 R
=
Vs R + 1/(j ωC)
j ω RC
=
1 + j ω RC
Vo R2
= 1+

V1 R1

Vo R2 j ω RC
⇒ = 1+ · . (7.1)
Vs R1 1 + j ω RC
It is given that Vs = Vm ∠0◦ and RC = 3/ω. Therefore

R2 3j
Vo = 1 + · · Vm ∠0◦
R1 1 + 3j

R2 3Vm
= 1+ · √ ∠(90 − 71.565051)◦
R1 10

R2 3Vm
= 1+ · √ ∠ 18.434949◦ . (7.2)
R1 10
Hence

R2 3Vm
vo (t) = 1 + · √ cos(ωt + 18.434949◦ ). (7.3)
R1 10

https://doi.org/10.1007/978-3-031-09363-0_7
230 7 Op Amp Circuits and Oscillators
Fig. 7.1 Op amp filter R2
R1
− Vo
Vs +
V1
C
R
Fig. 7.2 Op amp filter R2
R1
− Vo
R +
Vs
V1
If vs (t) = Vm cos(ωt) (denoted by the phasor Vs ) and RC = 2/ω find vo (t) (denoted
by the phasor Vo ).
V1 1/(j ωC)

=

Vs R + 1/(j ωC)
1
=
1 + j ω RC
Vo R2
= 1+

V1 R1

Vo R2 1
⇒ = 1+ · . (7.4)
Vs R1 1 + j ω RC
7 Op Amp Circuits and Oscillators 231
− R2
Vo
+
R1
Vs
V1
C2
C1
Fig. 7.3 Op amp filter
It is given that Vs = Vm ∠0◦ and RC = 2/ω. Therefore

R2 1
Vo = 1 + · · Vm ∠0◦
R1 1+2j

R2 Vm
= 1+ · √ ∠ − 63.434949◦ . (7.5)
R1 5
Hence

R2 Vm
vo (t) = 1 + · √ cos(ωt − 63.434949◦ ). (7.6)
R1 5
If vs (t) = Vm sin(ωt), R1 C1 = 2/ω and R2 C2 = 1/ω find vo (t).
V1 1/(j ωC1 )

=

Vs R 1 + 1/(j ωC 1 )
1
=
1 + j ω R1 C 1
Vo 1/(j ωC2 )
=

V1 R 2 + 1/(j ωC 2 )
1
=
1 + j ω R2 C 2
Vo 1 1
⇒ = · . (7.7)

Vs 1 + j ω R C
1 1 1 + j ω R2 C 2
It is given that Vs = Vm ∠ − 90◦ , R1 C1 = 2/ω and R2 C2 = 1/ω. Therefore

C2
− Vo
C1 +
Vs
V1
R2
R1
1 1
Vo = · · Vm ∠ − 90◦
1+2j 1+ j
Vm
= √ ∠ (−90 + 251.56505)◦
10
Vm
= √ ∠ 161.56505◦ . (7.8)
10
Hence
Vm
vo (t) = √ cos(ωt + 161.56505◦ ). (7.9)
10
If vs (t) = Vm sin(ωt), R1 C1 = 1/ω and R2 C2 = 0.5/ω find vo (t).
V1 R1
=
Vs R1 + 1/(j ωC1 )
j ω R1 C 1
=
1 + j ω R1 C 1
Vo R2
=
V1 R2 + 1/(j ωC2 )
j ω R2 C 2
=
1 + j ω R2 C 2

Vo j ω R1 C 1 j ω R2 C 2
⇒ = · . (7.10)
Vs 1 + j ω R1 C 1 1 + j ω R2 C 2
It is given that Vs = Vm ∠ − 90◦ , R1 C1 = 1/ω and R2 C2 = 0.5/ω. Therefore
j 0.5 j
Vo = · · Vm ∠ − 90◦
1 + j 1 + 0.5 j
0.5Vm
= √ ∠ (90 + 288.43495)◦
2.5
0.5Vm
= √ ∠ 18.434949◦ . (7.11)
2.5
Hence
0.5Vm
vo (t) = √ cos(ωt + 18.434949◦ ). (7.12)
2.5
If 1/(R1 C1 ) = 106 rad/s and 1/(R2 C2 ) = 4 × 106 rad/s find the radian frequency at
which vo (t) (denoted by the phasor Vo ) and vs (t) (denoted by the phasor Vs ) are in-
phase. At this frequency, find the voltage gain vo (t)/vs (t).
V1 R1
=

Vs R 1 + 1/(j ωC1 )
j ω R1 C 1
=
1 + j ω R1 C 1
Vo 1/(j ωC2 )
=

V1 R 2 + 1/(j ωC 2 )
− R2
Vo
C1 +
Vs
V1
C2
R1

1
=
1 + j ω R2 C 2
Vo j ω R1 C 1 1
⇒ = ·
Vs 1 + j ω R1 C 1 1 + j ω R2 C 2
j ω R1 C 1
= . (7.13)
1 − ω R1 C1 R2 C2 + j ω(R1 C1 + R2 C2 )
2
If vs (t) and vo (t) are to be in-phase, we require Vo /Vs to be real-valued at a certain
ω = ω0 . Therefore
1
ω0 = √
R1 R2 C 1 C 2
= 2 × 106 rad/s. (7.14)
The voltage gain at ω = ω0 is H (ω0 )

R1 C 1
H (ω0 ) =
R1 C 1 + R2 C 2
= 0.8
vo (t)
= . (7.15)
vs (t)
R4 = 9 k
R3 = 1 k
− R2
Vo
C1 + V2
Vs
V1
C2
R1

If 1/(R1 C1 ) = 105 rad/s and 1/(R2 C2 ) = 9 × 105 rad/s find the radian frequency at
which vo (t) (denoted by the phasor Vo ) and vs (t) (denoted by the phasor Vs ) are in-
phase. At this frequency, find the voltage gain vo (t)/vs (t).
V1 R1
=

Vs R 1 + 1/(j ωC1 )
j ω R1 C 1
=
1 + j ω R1 C 1

V2 R4
= 1+
V1 R3
Vo 1/(j ωC2 )
=
V2 R2 + 1/(j ωC2 )
1
=
1 + j ω R2 C 2

Vo j ω R1 C 1 1 R4
⇒ = · · 1+
Vs 1 + j ω R1 C 1 1 + j ω R2 C 2 R3

j ω R1 C 1 R4
= · 1 +
1 − ω 2 R1 C1 R2 C2 + j ω(R1 C1 + R2 C2 ) R3
(7.16)
If vs (t) and vo (t) are to be in-phase, we require Vo /Vs to be real-valued at a certain
ω = ω0 .
Therefore
1
ω0 = √
R1 R2 C 1 C 2
= 3 × 105 rad/s. (7.17)
The voltage gain at ω = ω0 is H (ω0 )

R1 C 1 R4
H (ω0 ) = · 1+
R1 C 1 + R2 C 2 R3
=9
= vo (t)/vs (t). (7.18)
7. Plot Vo versus Vi for the op amp in Fig. 7.7. Assume ideal op amp and Vsat = ±10 V.
– Solution: Consider Fig. 7.7. Due to the positive feedback, Vo = ±10 V. We have:
Fig. 7.7 Schmitt trigger
+
Vi
− Vo
2V +
5k
4k
Fig. 7.8 Hysteresis loop Vo (volt)

10
−58/9 22/9 Vi (volt)
−10
V+ = 4Vo /9
V− = Vi + 2. (7.19)
Let us assume that Vo = 10 V. Therefore V− < V+ . Then V+ = 40/9 V. Vo changes

to −10 V when
V− > 40/9
⇒ Vi > 40/9 − 2
> 22/9. (7.20)
Let us assume that Vo = −10 V. Therefore V− > V+ . Then V+ = −40/9 V. Vo

changes to 10 V when
V− < −40/9
⇒ Vi < −40/9 − 2
< −58/9. (7.21)
The hysteresis loop is shown in Fig. 7.8.


Vi
− Vo
−
3V +
3k
6k
V+ = 6Vo /9
V− = Vi − 3. (7.22)
Let us assume that Vo = 9 V. Therefore V− < V+ . Then V+ = 6 V. Vo changes to

−9 V when
V− > 6
⇒ Vi > 6 + 3
> 9. (7.23)
Let us assume that Vo = −9 V. Therefore V− > V+ . Then V+ = −6 V. Vo changes

to 9 V when
V− < −6
⇒ Vi < −6 + 3
< −3. (7.24)
V+ = 2Vo /6 + 1
V− = Vi − 4. (7.25)

9
−3 9 Vi (volt)
−9

Vi
− Vo
−
4V +
+
1V
4k
−
2k

−12 V when
V− > 5
⇒ Vi > 5 + 4
> 9. (7.26)

to 12 V when
V− < −3
⇒ Vi < −3 + 4
< 1. (7.27)
12
1 9 Vi (volt)
−12
+
Vi
− Vo
2V +
+
3V
2k
−
3k
V+ = 3Vo /5 + 3
V− = Vi + 4. (7.28)

−10 V when
V− > 9
⇒ Vi > 9 − 4
> 5. (7.29)

to 10 V when
V− < −3
⇒ Vi < −3 − 4
< −7. (7.30)

10
−7 5 Vi (volt)
−10
– Solution: Consider Fig. 7.15. Due to the positive feedback, Vo = ±10 V. By comput-
ing the Thevenin equivalent across node X and ground, as seen by the 1.5 k resistor,
we get the equivalent circuit shown in Fig. 7.16. Applying KCL at node X we get:
Vo − V+ V+ − 1
=
1.5 0.5
Vo + 3
⇒ V+ =
4
V− = Vi . (7.31)

to −10 V when
V− > 13/4
⇒ Vi > 13/4. (7.32)

Vi
− Vo
+
1.5 k
X
1k 1k
+
2V
−

Vi
− Vo
+
1.5 k
X
0.5 k
+
1V

V− < −7/4
⇒ Vi < −7/4. (7.33)
– Solution: Consider Fig. 7.18. Due to the positive feedback, Vo = ±10 V. By com-
puting the Thevenin equivalent across node X and ground, as seen by the 7 k resistor,
we get the equivalent circuit shown in Fig. 7.19. Applying KCL at node X we get:
Vo − V+ V+ − (−2)
=
7 3
3Vo − 14
⇒ V+ =
10
V− = Vi . (7.34)

to −10 V when
V− > 16/10
⇒ Vi > 1.6. (7.35)

10
−7/4 13/4 Vi (volt)
−10

Vi
− Vo
+
7k
X
6k 6k
−
4V
+
V− < −44/10
⇒ Vi < −4.4. (7.36)
13. The system in Fig. 7.21 is known to oscillate at one particular non-zero frequency. It
is given that
10
A(ω) =
(1 + j ω/ω0 )(1 + j ω/(10ω0 ))
β(ω) = K /(j ω). (7.37)
Determine the frequency of oscillation and K .
– Solution: Consider Fig. 7.21. For the given system, we have:
Vo A(ω)
= . (7.38)
Vi 1 + A(ω)β(ω)

Vi
− Vo
+
7k
X
3k
−
2V
+
10
−4.4 1.6 Vi (volt)
−10
Fig. 7.21 Oscillator block Vi + Vo

diagram A(ω)
−
β(ω)
The condition for oscillation is (Barkhausen criterion):
A(ωc )β(ωc ) = −1 (7.39)
where ω = ωc is the frequency of oscillation. Since β(ω) is purely imaginary, A(ω)

must also be purely imaginary at the frequency of oscillation. Note that
10
A(ω) = (7.40)
1 − ω 2 /(10ω02 ) + j 11ω/(10ω0 )
√
is purely imaginary for ω = ω0 10 = ωc . Therefore
100ω0
A(ωc ) =
11ωc j
100
= √ . (7.41)
11 10 j
Hence
−1
β(ωc ) =
A(ωc )
√
−11 10 j
=
100
K
=
j ωc
⇒ K = 11ω0 /10. (7.42)
is given that
20
A(ω) =
[(1 − j ω/ω0 )(1 + j ω/(10ω0 )) + j ω/ω1 ]
β(ω) = −1/10. (7.43)
Determine the frequency of oscillation and the relation between ω0 and ω1 .
– Solution: For the given system, we have:
Vo A(ω)
= . (7.44)
Vi 1 + A(ω)β(ω)
The condition for oscillation is:
A(ωc )β(ωc ) = −1 (7.45)
where ω = ωc is the frequency of oscillation. Since β(ω) is purely real, A(ω) must
also be purely real at the frequency of oscillation. Note that
20
A(ω) = (7.46)
1 + ω 2 /(10ω02 ) + j ω(1/ω1 − 9/(10ω0 ))

diagram A(ω)
−
β(ω)
is purely real for ω1 = 10ω0 /9. Therefore

20
A(ω) = . (7.47)
1 + ω 2 /(10ω02 )
Hence
A(ωc )β(ωc ) = −1
√
⇒ ωc = ω0 10. (7.48)
is given that
4
A(ω) =
1 − ω 2 /ω02 + j(ω/ω1 + ω 3 /ω23 )
β(ω) = K j ω. (7.49)
Vo A(ω)
= . (7.50)

Vi 1 + A(ω)β(ω)
A(ωc )β(ωc ) = −1 (7.51)
where ω = ωc is the frequency of oscillation. Since β(ω) is purely imaginary, A(ω)

must also be purely imaginary at the frequency of oscillation. Note that
4
A(ω0 ) = (7.52)
j (ω0 /ω1 + ω03 /ω23 )
is purely imaginary. Therefore ωc = ω0 . Hence

diagram A(ω)
−
β(ω)
A(ω0 )β(ω0 ) = −1

1 ω02
⇒ K = (−1/4) + 3 . (7.53)
ω1 ω2
is given that
6
A(ω) =
1 + ω 2 /ω12 + j(ω/ω2 − ω 3 /ω33 )
β(ω) = K . (7.54)
Vo A(ω)
= . (7.55)
Vi 1 + A(ω)β(ω)
A(ωc )β(ωc ) = −1 (7.56)
where ω = ωc is the frequency of oscillation. Since β(ω) is purely real, A(ω) must
also be purely real at the frequency of oscillation. Note that
ω/ω2 − ω 3 /ω33 = 0

⇒ ω = ω33 /ω2
= ωc . (7.57)
Hence

diagram A(ω)
−
β(ω)
A(ωc )β(ωc ) = −1
⇒ K A(ωc ) = −1
⇒ K = −1/A(ωc )
−(ω12 + ωc2 )
= . (7.58)
6ω12
17. For the op amp circuit in Fig. 7.25 find Vo versus Vi . Z1 has a cut-in voltage of 1 V and
a breakdown voltage of 4 V. Z2 has a cut-in voltage of 1 V and a breakdown voltage
of 5 V. Assume ideal op amp. Assume zero knee current for the zener diodes and zero
resistance when they are conducting.
Z1 Z2
IZ
1k
Vi
− Vo
+
2k
+
3V
Fig. 7.25 Op-amp circuit
4V 1V
IZ
+
−
+
1k
Vi
− Vo
I1
+
I2 2k
+
3V

1V 5V
+
−
+
IZ
1k
Vi
− Vo
I1
+
I2 2k
+
3V
– Solution: Consider Fig. 7.25. Due to negative feedback, V+ = V− = 0 V. We have

the following situations:
(a) I Z > 0. In this case Z1 is in breakdown region and Z2 is forward biased, as

shown in Fig. 7.26. Note that:
I1 + I2 = I Z
⇒ Vi + 3/2 = I Z > 0
⇒ Vi > −3/2 V
⇒ Vo = −5 V. (7.59)
(b) I Z < 0. In this case Z1 is forward biased and Z2 is in breakdown region, as

shown in Fig. 7.27. Again
I1 + I2 = I Z
⇒ Vi + 3/2 = I Z < 0
⇒ Vi < −3/2 V
⇒ Vo = 6V. (7.60)
(c) I Z = 0. Then there is no negative feedback. This can happen only when Vi =
−3/2 V. Here
Vi − 3
I1 = −I2 =
3
⇒ V− = Vi − I1
= 0 V. (7.61)
If the open loop op amp gain (A) is infinite, then
Vo = A(V+ − V− ) (7.62)
is indeterminate. To summarize:
⎧
⎨ −5 V for Vi > −3/2 V
Vo = 6 V for Vi < −3/2 V (7.63)
⎩
indeterminate for Vi = −3/2 V
18. Consider the single op amp difference amplifier shown in Fig. 7.28. It is given that
R1 = R3 = 10 k, R2 = 100 k and R4 = 100.1 k. Compute the common mode rejection
ratio (CMRR) in dB.
– Solution: Consider Fig. 7.28. The output voltage vo can be written as:
vo = Ad vd + Acm vc (7.64)
where
vd = v2 − v1
vc = (v2 + v1 )/2. (7.65)
Fig. 7.28 Op amp difference R2

amplifier
R1
v1
− vo
v2
+
R3
R4
Thus
vo
Ad =
vd
vc =0

vo
Acm = . (7.66)
v
c vd =0
For the circuit in Fig. 7.28, it can be shown that the common mode gain is:

R4 R2 R3
Acm = 1−
R3 + R4 R1 R4
= 0.0009083. (7.67)
The differential mode gain is:

1 R2 R4 (R1 + R2 )
Ad = +
2 R1 R1 (R3 + R4 )
= 10.000454. (7.68)
Therefore
CMRR = 20 log10 (|Ad |/|Acm |)

= 80.836141 dB. (7.69)
19. Consider the op amp circuit shown in Fig. 7.29. Using superposition, find vo in terms
of v1 , v2 and v3 .
– Solution: We use superposition to compute vo . We have

−R f
vo1 = v1
R1
−R f
vo2 = v2
R
2
Rf
vo3 = 1+ v3 (7.70)
R
Fig. 7.29 Op amp circuit Rf
R1
v1
− vo
v2
+
R2
v3
R2
R1
R2
− R1
−
v1 +
+ vo
v2
Fig. 7.30 Op amp circuit
where
R1 R2
R= . (7.71)
R1 + R2
Therefore
vo = vo1 + vo2 + vo3 . (7.72)
20. Consider the op amp circuit shown in Fig. 7.30. Find vo in terms of v1 and v2 .
i 1 = v1 /R2
i 2 = (vx − v1 )/R1
i 3 = (v2 − v1 )/R. (7.73)
Applying KCL at node A we get
i1 = i2 + i3

1 1 1 v2 R 1
⇒ v x = v1 R 1 + + − . (7.74)
R1 R2 R R
Using superposition, the output voltage can be written as:

−R2 −R2 R2
vo = v x + v1 + v2 1 + (7.75)
R1 R R3
where R3 = R1 R. Substituting for vx from (7.74) we get
vo = K (v2 − v1 ) (7.76)
R
i3
i2
R2
R1
R2
− R1
A −
i1
+ vx
v1
+ vo
v2
where

1 2
K = 1 + R2 + . (7.77)
R1 R
21. Draw the circuit diagram of a triangular wave generator using a non-inverting Schmitt
trigger. Derive the expression for the time period of the triangular waveform. Assume
ideal op amp(s) and that when the op amp functions as a comparator, its output voltages
are ±Vs . The threshold values of the Schmitt trigger need not be derived.
– Solution: The circuit diagram of the triangular wave generator using a non-inverting
Schmitt trigger is shown in Fig. 7.32. Op amp 1 functions as a comparator and op
amp 2 as an integrator. Therefore vo (t) takes values ±Vs . The threshold values of
the non-inverting Schmitt trigger are:
R1
VTL = −Vs
R2
R1
VTU = Vs . (7.78)
R2
Note that
vo (t)
i(t) = (7.79)
R
and
vi (t) = −vC (t). (7.80)
(a) Let vo (t) = Vs . Then vo (t) changes to −Vs when
vi (t) < VTL . (7.81)

R2
Schmitt trigger
+
1
R1 − vo (t)
vC (t)
− +
i(t)
i(t)
C R
−
2 +
vi (t)
Integrator
Vs
vo (t)
VT U
t
vi (t)
VT L
−Vs
T1 T2
Fig. 7.32 A triangular wave generator using a non-inverting Schmitt trigger
Now
i(t) = Vs /R
= CdvC (t)/dt
= −Cdvi (t)/dt
⇒ vi (t) = −Vs t/(RC) + K 1 . (7.82)
Note that
vi (0) = K 1 = VTU
vi (T1 ) = VTL
R1
⇒ T1 = 2RC . (7.83)
R2
(b) Let vo (t) = −Vs . Then vo (t) changes to Vs when
vi (t) > VTU . (7.84)
Now
i(t) = −Vs /R
= CdvC (t)/dt
= −Cdvi (t)/dt
⇒ vi (t) = Vs t/(RC) + K 2 . (7.85)
Note that
vi (0) = K 2 = VTL
vi (T2 ) = VTU
R1
⇒ T2 = 2RC . (7.86)
R2
The time period of the triangular waveform is

R1
T = T1 + T2 = 4RC . (7.87)
R2
22. Find the input impedance across terminals AB for the op amp circuit shown in Fig. 7.33.
Assume that the op amp is ideal and functions like an amplifier.
– Solution: Consider the circuit in Fig. 7.34. The input impedance is given by:
v
Z in = . (7.88)
i
Note that
v
i1 =
R1
⇒ vo = v + i 1 R
= v(1 + R/R1 )
⇒ i = (v − vo )/R
Fig. 7.33 Op amp circuit R = 10 k
R1 = 20 k
A R = 10 k
i1
−
vo
+
i
R1 = 20 k
i
A R = 10 k
+
v
B
−
= −v/R1
⇒ v/i = −R1 = −20 k. (7.89)
The given circuit is used to simulate a negative resistance.
23. Find the input impedance across terminals AB for the op amp circuit shown in Fig. 7.35.
Assume that the op amp is ideal and functions like an amplifier.
– Solution: Consider the circuit in Fig. 7.36. The input impedance is given by:
v
Z in = . (7.90)
i
R1 = 30 k
A R = 20 k
i1
−
vo
+
i
R1 = 30 k
i
A R = 20 k
+
v
B
−
Note that
v
i1 =
R1
⇒ vo = v + i 1 R
= v(1 + R/R1 )
⇒ i = (v − vo )/R
= −v/R1
⇒ v/i = −R1 = −30 k. (7.91)
D1 R
R
Vi
− R −
+ +
R
D2
+
Vo
−
The given circuit is used to simulate a negative resistance.
24. Find Vo /Vi for the circuit shown in Fig. 7.37. Assume that the I − V characteristic of
both the diodes is given by
I = I S e V /VT (7.92)
where I denotes the current through the diode, V is the voltage across the diode, I S is
the saturation current, VT is the thermal voltage and V VT . Assume ideal op amps.
– Solution: Consider Fig. 7.38. Clearly
V1 = −VD1
Vi = I D1 R
= I S R e−V1 /VT

Vi
⇒ V1 = −VT ln (7.93)
IS R
Similarly
+ −
VD1
D1 ID1 R
R
Vi
− R −
V2
+ +
V1
R
R
− +
VD2
D2
+
Vo
− ID2
V2 = −2V1

Vi
= 2VT ln
IS R
VD2 = V2
I D2 = I S e V2 /VT
Vo = −I D2 R
Vi2
=− . (7.94)
IS R
Thus the circuit in Fig. 7.37 functions as a squarer.
Combinational Circuits
8
1. Convert 4310 to binary and octal.
– Solution: Refer to Fig. 8.1 for decimal-to-binary conversion. We have:
4310 =
101 0112

= 538 . (8.1)
2. Convert 7110 to binary and octal.
7110 =
001
000 1112

= 1078 . (8.2)
3. Convert 56.1910 to binary (upto six bits after the binary point) and octal.
56.1910 ≈ 000 .

111 001 1002

≈ 70.148 . (8.3)
4. Convert 91.4810 to binary (upto six bits after the binary point) and octal.

https://doi.org/10.1007/978-3-031-09363-0_8
260 8 Combinational Circuits
Fig. 8.1 Number system Remainder

2 43
2 21 1
2 10 1
2 5 0
2 2 1
2 1 0
2 0 1 Read up
Fig. 8.2 Number system Remainder

2 71
2 35 1
2 17 1
2 8 1
2 4 0
2 2 0
2 1 0
2 0 1 Read up
91.4810 ≈
001 011 .
011 011 1102

≈ 133.368 . (8.4)
5. Minimize the boolean function
F = Ā B̄ C̄ D̄ + A B̄ C̄ D̄ + Ā B̄C D̄ + ĀBC D̄ + A B̄C D̄. (8.5)
using the K-map.
– Solution: Refer to Fig. 8.5. The minimized function in sum-of-products (SOP) form
is:
F = B̄ D̄ + ĀC D̄. (8.6)

F(A, B, C, D) = m(0, 2, 5, 10, 12, 15) + d(4, 7, 8, 13). (8.7)
using the K-map. Implement the function using NAND gates.
– Solution: Refer to Fig. 8.6. The minimized function is:

8 Combinational Circuits 261
Remainder Carry
2 56 0.19 × 2 = 0.38 0 Read down
0.38 × 2 = 0.76 0
2 28 0
0.76 × 2 = 1.52 1
2 14 0 0.52 × 2 = 1.04 1
0.04 × 2 = 0.08 0
2 7 0
0.08 × 2 = 0.16 0
2 3 1
2 1 1
2 0 1 Read up
Fig. 8.3 Number system
Remainder C arr y
2 91 0.48 × 2 = 0.96 0 Read down
0.96 × 2 = 1.92 1
2 45 1
0.92 × 2 = 1.84 1
2 22 1 0.84 × 2 = 1.68 1
0.68 × 2 = 1.36 1
2 11 0
0.36 × 2 = 0.72 0
2 5 1
2 2 1
2 1 0
2 0 1 Read up
Fig. 8.5 K-map CD 00 01 11 10

AB
00 1 0 0 1
01 0 0 0 1
11 0 0 0 0
10 1 0 0 1
Fig. 8.6 K-map CD 00 01 11 10

AB
00 1 0 0 1
01 X 1 X 0
11 1 1 0 X
10 X 0 0 1
B̄
D̄
C̄
F (A, B, C, D)
D̄
Fig. 8.7 NAND implementation of Fig. 8.6
F(A, B, C, D) = B̄ D̄ + C̄ D̄ + B D. (8.8)
The implementation using NAND gates is shown in Fig. 8.7.

F(A, B, C, D) = m(2, 5, 7, 6, 13, 15, 10)

+ d(4, 8, 9, 11, 14). (8.9)
using the K-map. The minimized function should be in product-of-sums (POS) form.
Implement the minimized function using NOR gates.
– Solution: Refer to Fig. 8.8. The minimized function is:
F(A, B, C, D) = C̄ D̄ + B̄ D
⇒ F(A, B, C, D) = (C + D)(B + D̄). (8.10)
The implementation using NOR gates is shown in Fig. 8.9.
8. The truth table of a 1-bit (one binary digit) full-adder is shown in Fig. 8.10. Implement
the sum (S) and the carry-out (Cout ) functions using only NAND gates.
– Solution: Refer to Fig. 8.10. The sum function is given by:
S = Ā B̄C + ĀB

C̄ + A B̄ C̄ + ABC
. (8.11)
F1 F2
CD 00 01 11 10
AB
00 0 0 0 1
01 X 1 1 1
11 0 1 1 X
10 X X X 1
Fig. 8.8 K-map
D
F (A, B, C, D)
D̄
Fig. 8.9 NOR implementation of Fig. 8.8
Fig. 8.10 Truth table of a 1-bit A B Cin S Cout

full-adder
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Implementation of S using NAND gates is shown in Fig. 8.11. The K-map for Cout
is shown in Fig. 8.12. We have
Cout = AB + BC + AC. (8.12)
The implementation of Cout using NAND gates is shown in Fig. 8.13.
9. Realize the following function using one 4-to-1 multiplexer:
F = AB + BC. (8.13)
Ā
B̄
Ā F1
C̄
F̄1
A
B̄
C̄
A
F̄2
B
S
C
Fig. 8.11 Implementation of S using NAND gates
Fig. 8.12 K-map for Cout AB 00 01 11 10
C
0 0 1 0
0
1 0 1 1 1
Fig. 8.13 Implementation of A

Cout using NAND gates
B
B
Cout
C
C
Fig. 8.14 Implementation of A B

(8.13) using 4-to-1 MUX
0
0
F
C 1
0 2
3 1
AB should be taken as control signals, with A as the most significant bit (MSB) and
B as the least significant bit (LSB). Assume that the variables and their complements
are both available.
– Solution: The function can be written as:
F = AB · 1 + ĀBC + ABC
= AB(1 + C) + ĀBC
= AB · 1 + ĀB · C. (8.14)
The implementation of F is shown in Fig. 8.14.
10. Realize the following function using one 4-to-1 multiplexer and NAND gates:
F = ĀBC + B D + AC̄ D. (8.15)
AB should be taken as control signals, with A as the most significant bit (MSB). Assume
that the variables and their complements are both available.
– Solution: The function can be written as:
F = ĀBC + B D + AC̄ D
= ĀBC + (A + Ā)B D + A(B + B̄)C̄ D
= ĀBC + AB D + ĀB D + AB C̄ D + A B̄ C̄ D
= Ā B̄ · 0 + ĀB(C + D) + A B̄ · C̄ D + AB · D. (8.16)
The implementation of F is shown in Fig. 8.15.
11. Realize the function F represented by the K-map in Fig. 8.16, using a 4-to-1 multiplexer.
A B
0
C̄ 0
F
1
D̄
2
3
C̄ D
Fig. 8.15 Implementation of (8.15) using 4-to-1 MUX and NAND gates
Fig. 8.16 K-map CD 00 01 11 10

AB
0 1 X 0
00
X 0 0 1
01
X 1 X X
11
0 0 0 X
10
Fig. 8.17 Implementation of CD 00 01 11 10

Fig. 8.16 using 4-to-1 MUX
AB
0 1 X 0
00 F =D
X 0 0 1
01 F = D̄
X 1 X X
11 F =1
0 0 0 X
10 F =0
– Solution: Refer to Fig. 8.17. The implementation using 4-to-1 multiplexer is shown
in Fig. 8.18.
12. Realize a 4-to-16 line decoder using five 1-to-4 demultiplexers with strobe (enable).
Assume that all the demultiplexer inputs and outputs are active high.
– Solution: The implementation is depicted in Fig. 8.19.

Note that when S = 0 the DEMUX is disabled and all output lines are low. When
S = 1, the DEMUX is enabled and only one output line (determined by the control
inputs) takes the value D(=1).

D
0
F
D̄ 1
0 2
1 3
Fig. 8.19 Implementation of C D

4-to-16 line decoder using
1-to-4 demultiplexers
D0
0
1 D1
D 1
D2
2
D3
S 3
C D
D4
0
1 D5
D 1
A B
D6
2
D7
S 3
0
1
D 1
C D
2
S 3
D8
0
1
1 D9
D 1
D10
2
D11
S 3
C D
D12
0
1 D13
D 1
D14
2
D15
S 3
13. Simplify the following Boolean expression:
F = (B + A)(C + Ā)(B + C). (8.17)
F = (B + A)(C + Ā)(B + C)
= (B + A) + (C + Ā) + (B + C)
= Ā B̄ + AC̄ + B̄ C̄. (8.18)
14. Simplify the following Boolean expression:
F = (AB C̄)(C̄ + AB). (8.19)
F = (AB C̄)(C̄ + AB)

= ( Ā + B̄ + C)C( Ā + B̄)
= ĀC + Ā B̄C + ĀC + Ā B̄C + B̄C + B̄C
= ĀC + B̄C(1 + Ā)
= ĀC + B̄C
= ( Ā + B̄)C. (8.20)
15. For the digital circuit shown in Fig. 8.20, obtain a simplified expression for the output
F.
– Solution: From Fig. 8.21, we have F = C.
16. Convert 111.56110 to binary (upto 9 bits after the binary point) and octal.
111.56110 ≈
001 111 .
101 100
011 1112

≈ 157.4378 . (8.21)
17. Convert 121.32110 to binary (upto 9 bits after the binary point) and octal.

C
F
Fig. 8.20 Combinational circuit
A Ā
AC̄
B ABC
C C̄
C̄ F =C
Fig. 8.21 Combinational circuit
Remainder Carry
2 111 0.561 × 2 = 1.122 1 Read down
0.122 × 2 = 0.244 0
2 55 1
0.244 × 2 = 0.488 0
2 27 1 0.488 × 2 = 0.976 0
0.976 × 2 = 1.952 1
2 13 1
0.952 × 2 = 1.904 1
2 6 1 0.904 × 2 = 1.808 1
0.808 × 2 = 1.616 1
2 3 0
0.616 × 2 = 1.232 1
2 1 1 Read up
0 1

Remainder Carry
2 121 0.321 × 2 = 0.642 0 Read down
0.642 × 2 = 1.284 1
2 60 1
0.284 × 2 = 0.568 0
2 30 0 0.568 × 2 = 1.136 1
0.136 × 2 = 0.272 0
2 15 0
0.272 × 2 = 0.544 0
2 7 1 0.544 × 2 = 1.088 1
0.088 × 2 = 0.176 0
2 3 1
0.176 × 2 = 0.352 0
2 1 1 Read up
0 1
Fig. 8.24 K-map BD 00 01 11 10

AC
1 0 X 0
00
X X X 0
01
X 0 0 0
11
X 1 1 1
10
121.32110 ≈
001 001 .
111 010
100 1002

≈ 171.2448 . (8.22)
18. Realize the function F represented by the K-map in Fig. 8.24, using a 4-to-1 multiplexer.
– Solution: Refer to Fig. 8.24. The the modified K-map is shown in Fig. 8.25. The
implementation using 4-to-1 multiplexer is shown in Fig. 8.26.
19. It is given that
18m + 25m = 46m . (8.23)
Find m.
– Solution: Converting (8.23) to base−10, we get:
m + 8 + 2m + 5 = 4m + 6
⇒ m = 7. (8.24)
Fig. 8.25 Modified K-map for CD 00 01 11 10

Fig. 8.24
AB
1 0 X X F = D̄
00
0 X X 0 F =0
01
1 1 0 0 F = C̄
11
X 1 0 X F = C̄
10

D̄
0
0 F
1
C̄
2
C̄
3
28m + 37m = 66m . (8.25)
Find m.
2m + 8 + 3m + 7 = 6m + 6
⇒ m = 9. (8.26)
21m + 15m = 36m . (8.27)
Find m.
2m + 1 + m + 5 = 3m + 6 (8.28)
which is true for all m. However, for the given problem, m has to be an integer greater
than 6.
30m + 22m = 52m . (8.29)
Find m.
3m + 2m + 2 = 5m + 2 (8.30)
which is true for all m. However, for the given problem, m has to be an integer greater
than 5.
Sequential Circuits
9
1. Show how a negative edge triggered D flip-flop can be used to implement a divide-by-2
operation. Justify your answer with sketches of the clock and the Q output.
– Solution: The divide-by-2 operation can be obtained by connecting the Q̄ to the D

input, as illustrated in Fig. 9.1. The clock and the Q outputs are also shown in the
same figure.
2. Show that the characteristic equation for the complement output of the J K flip-flop is
Q̄ t+1 = J¯ Q̄ t + K Q t . (9.1)
– Solution: The truth table for Q t+1 is shown in Fig. 9.2a. The K-map is depicted in
Fig. 9.2b. It is clear that (9.1) is satisfied.
3. For the circuit in Fig. 9.3, determine Q A Q B Q C for eight clock cycles. Assume initial
value of Q A Q B Q C = 0. Use suitable input-output table. The table must have eight rows,
including the initial state.
– Solution: The transition table for the J K flip-flop is shown in Fig. 9.4. The sequence
of states for eight clock cycles is shown in Fig. 9.5.
4. Realize a positive edge triggered D flip-flop from a positive edge triggered T flip-flop.
– Solution: The block diagram for converting a T flip-flop into a D flip-flop is shown
in Fig. 9.6a. The truth table for the T flip-flop and the corresponding requirement for
the D input is depicted in Fig. 9.6b. Finally, the truth table for the T input, in terms

https://doi.org/10.1007/978-3-031-09363-0_9
274 9 Sequential Circuits
CLK
T
t
D Q
Q
CLK
Q̄
t
2T
Fig. 9.1 Sequential circuit
JK 00 01 11 10
(a) J K Qt Qt+1 (b)
Qt
0 0 0 0
0 0 1 1
0
0 0 1 1
1 1 0 0 1
0 1 0 0
0 1 1 0
K-map for Qt+1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Truth table for Qt+1
J Q J Q J Q
A B C
K Q̄ K Q̄ K Q̄
CLK

9 Sequential Circuits 275
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Fig. 9.4 Transition table for the J K flip-flop
Time n Time n + 1
QA QB QC JA KA JB KB JC KC QA QB QC
0 0 0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 0 0 0 0 0 1 1
0 1 1 1 1 1 1 0 0 1 0 1
1 0 1 1 1 0 0 0 0 0 0 1
0 0 1 1 1 1 1 1 1 1 1 0
1 1 0 1 1 0 0 0 0 0 1 0
0 1 0 1 1 1 1 0 0 1 0 0
1 0 0 1 1 0 0 0 0 0 0 0
Fig. 9.5 Sequence of states for the circuit in Fig. 9.3
of D and Q n , is shown in Fig. 9.6c. From Fig. 9.6c we have:
T = D Q̄ n + D̄ Q n . (9.2)
5. The truth table of an AB flip-flop is given in Fig. 9.7. Show how the AB flip-flop can
be realized using a J K flip-flop and only NAND gates. Assume that only AB inputs are
available and their complements are not available.
– Solution: Refer to Fig. 9.8a. Clearly
J = A
K = B̄. (9.3)
6. Design a mod-5 asynchronous up-counter using positive edge triggered J K flip-flops

and only NOR gates. Assume that all flip-flops have an asynchronous active-low reset
(clear).
– Solution: The circuit is shown in Fig. 9.9.

Fig. 9.6 Converting a T (a)

flip-flop into a D flip-flop
Q
Logic T Q
D
CLK
Q̄
D flip-flop
(b)
T Qn Qn+1 D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
(c)
D Qn T
0 0 0
1 1 0
1 0 1
0 1 1
Fig. 9.7 Truth table of an AB A B Qn+1

flip-flop
0 0 0
0 1 Qn
1 0 Q̄n
1 1 1
7. Design a synchronous counter using positive edge triggered J K flip-flops that runs
through the following state sequence: 0, 3, 4, 7, 5, 2, 1, 6, 0. Draw the circuit diagram.
– Solution: Since there are eight distinct states, three J K flip-flops are required. The
transition table for the J K flip-flop is shown in Fig. 9.10. The state sequence and
the J K requirement for each flip-flop is shown in Fig. 9.11. The truth table for J A ,
K A , JC , and K C is shown in Fig. 9.12. Note that J B = K B = 1. The circuit diagram
is shown in Fig. 9.13.
(a) A B Qn+1 J K
0 0 0 0 1
0 1 Qn 0 0
1 0 Q̄n 1 1
1 1 1 1 0
(b)
A
J Q
B
K Q̄
AB flip-flop
Fig. 9.8 a J K inputs required to implement the AB flip-flop
(a)
C B A
1 1 1
J Q J Q J Q
CLK C LK CLK
1 1 1
K Q̄ K Q̄ K Q̄
C LR C LR C LR
(b)
QA QB QC Q̄A Q̄B Q̄C
0 0 0 1 1 1
0 0 1 1 1 0
0 1 0 1 0 1 Decode
0 1 1 1 0 0
1 0 0 0 1 1
1 0 1 0 1 0
Fig. 9.9 A mod-5 asynchronous up-counter

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Fig. 9.10 Transition table for the J K flip-flop
Time n Time n + 1 Required inputs

QA QB QC QA QB QC JA KA JB KB JC KC
0 0 0 0 1 1 0 X 1 X 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 1 1 X 0 1 X 1 X
1 1 1 1 0 1 X 0 X 1 X 0
1 0 1 0 1 0 X 1 1 X X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 1 1 0 1 X 1 X X 1
1 1 0 0 0 0 X 1 X 1 0 X
0 0 0
Fig. 9.11 State sequence and J K requirement for each flip-flop
QA QB QA QB
00 01 11 10 00 01 11 10
QC QC
0 0 X X X X 1 0
0 0
1 1 1 X X 1 X X 0 1
JA = QC KA = QB Q̄C + Q̄B QC
QA QB QA QB
00 01 11 10 00 01 11 10
QC QC
1 1 0 1 X X X X
0 0
1 X X X X 1 1 1 0 1
JC = Q̄A + Q̄B KC = Q̄A + Q̄B
Fig. 9.12 Truth table for J K input of each flip-flop

1
J Q J Q J Q
A B C
K Q̄ 1 K Q̄ K Q̄
CLK
Fig. 9.13 Circuit diagram
Fig. 9.14 Transition table for Qn Qn+1 J K

the J K flip-flop
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
8. Design a synchronous counter using positive edge triggered J K flip-flops that runs
through the following state sequence: 0, 2, 4, 6, 7, 5, 3, 1, 0. Draw the circuit diagram.
transition table for the J K flip-flop is shown in Fig. 9.14. The state sequence and
the J K requirement for each flip-flop is shown in Fig. 9.15. The truth table and the
Boolean expressions for the three flip-flop inputs are shown in Fig. 9.16. The circuit
diagram is shown in Fig. 9.17.
9. Design a synchronous counter using only positive edge triggered J K flip-flops and 3-
input OR gates that runs through the following state sequence: 0, 4, 3, 2, 5, 6, 1, 7, 0.
Draw the circuit diagram.

0 0 0 0 1 0 0 X 1 X 0 X
0 1 0 1 0 0 1 X X 1 0 X
1 0 0 1 1 0 X 0 1 X 0 X
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
1 0 1 0 1 1 X 1 1 X X 0
0 1 1 0 0 1 0 X X 1 X 0
0 0 1 0 0 0 0 X 0 X X 1
0 0 0
QA QB QA QB
00 01 11 10 00 01 11 10
QC QC
0 1 X X X X 0 0
0 0
1 0 0 X X 1 X 0 X 1
JA = QB Q̄C KA = Q̄B QC
QA QB QA QB
00 01 11 10 00 01 11 10
QC QC
1 X X 1 X 1 0 X
0 0
1 0 1 X 1 X 1 1 X
JB = QA + Q̄C KB = Q̄A + QC
QA QB QA QB
00 01 11 10 00 01 11 10
QC QC
0 0 1 0 X X X X
0 0
1 X X X X 1 1 0 0 0
JC = QA QB KC = Q̄A Q̄B
Fig. 9.16 Truth table for J K input of each flip-flop

J Q J Q J Q
A B C
K Q̄ K Q̄ K Q̄
CLK
Fig. 9.18 Transition table for Qn Qn+1 J K

the J K flip-flop
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
transition table for the J K flip-flop is shown in Fig. 9.18. The state sequence and the
J K requirement for each flip-flop is shown in Fig. 9.19. Assuming the don’t care
(X) to be 1, it is clear that:

0 0 0 1 0 0 1 X 0 X 0 X
1 0 0 0 1 1 X 1 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 1 0 1 1 X X 1 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 0 0 1 X 1 X 1 1 X
0 0 1 1 1 1 1 X 1 X X 0
1 1 1 0 0 0 X 1 X 1 X 1
0 0 0
J Q J Q J Q
A B C
K Q̄ K Q̄ K Q̄
CLK

J¯A = Q̄ A Q B Q C
⇒ J A = Q A + Q̄ B + Q̄ C
K̄ A = Q A Q̄ B Q C
⇒ K A = Q̄ A + Q B + Q̄ C
J¯B = Q̄ A Q̄ B Q̄ C
⇒ JB = Q A + Q B + Q C
K̄ B = Q̄ A Q B Q C
⇒ K B = Q A + Q̄ B + Q̄ C
J¯C = Q̄ A Q̄ B Q̄ C
⇒ JC = Q A + Q B + Q C
K̄ C = Q̄ A Q̄ B Q C
⇒ K C = Q A + Q B + Q̄ C . (9.4)
The circuit diagram is shown in Fig. 9.20.

Two-Port Networks
A
A linear two-port network shown in Fig. A.1 contains linear elements like resistors, capaci-
tors, inductors and dependent sources. By definition, it does not contain independent sources.
The independent sources are supposed to be applied across the two-ports. Two-port networks
are characterized by different parameters. They are listed below:
1. The admittance parameters are given by:
I1 = y11 V1 + y12 V2

I2 = y21 V1 + y22 V2
(A.1)
where

I1
y11 =
V1 V =0
2
I1
y12 =
V2 V =0
1
I2
y21 =
V1 V =0
2
I2

y22 = . (A.2)
V2 V =0
1
Note that V1 = 0 implies that port 1 is short-circuited, and so on. Now, (A.1) can be
written in matrix notation as
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer 285
Nature Switzerland AG 2023
https://doi.org/10.1007/978-3-031-09363-0
286 Appendix: Two-Port Networks
Fig. A.1 A linear two-port + I1 I2 +

network Two-port
Port 1 V1 linear V2 Port 2
network
−
I = y V
(A.3)
where

I = I1 I2 T

= V1 V2 T
V

y11 y12
y = . (A.4)
y21 y22
Now, consider Fig. A.2 where the two-port networks are connected in parallel. We have
A
I A = y A V
I B = y B VB (A.5)
where

yA, 11 yA, 12
y A =
yA, 21 yA, 22

yB, 11 yB, 12
y B = (A.6)
yB, 21 yB, 22
+ IA, 1 IA, 2 +
Two-port
VA, 1 network VA, 2
A
+ I1 I2 +
−
V1 V2
+ IB, 1 IB, 2 +
− −
Two-port
VB, 1 network VB, 2
B
−
Fig. A.2 Two-port networks connected in parallel

Appendix: Two-Port Networks 287
denote the admittance matrices for networks A and B respectively and

I A = IA, 1 IA, 2 T

A = VA, 1 VA, 2 T
V

I B = IB, 1 IB, 2 T

B = VB, 1 VB, 2 T
V (A.7)
denote the current and voltage vectors for network A and B respectively. From Fig. A.2
we have
VA, 1 = VB, 1
= V1
VA, 2 = VB, 2
= V2
IA, 1 + IB, 1 = I1
IA, 2 + IB, 2 = I2 . (A.8)
From (A.5), (A.7) and (A.8) we obtain
I A + I B = (y A + y B ) V

⇒ I = yV (A.9)
where I and V
are defined in (A.4) and
y A + y B = y. (A.10)
Thus, when two-port networks are connected in parallel, the resulting admittance matrix
is the sum of the individual admittance matrices.
2. The impedance parameters are given by:
V1 = z 11 I1 + z 12 I2

V2 = z 21 I1 + z 22 I2 (A.11)
where

V1
z 11 =
I1 I =0
2
V1

z 12 =
I2 I =0
1
V2
z 21 =
I1 I =0
2
V2
z 22 = . (A.12)
I2
I1 =0
Note that I1 = 0 implies that port 1 is open-circuited, and so on. Now, (A.11) can be
written in matrix notation as
= z I
V (A.13)
where

I = I1 I2 T

= V1 V2 T
V

z 11 z 12
z = . (A.14)
z 21 z 22
Now, consider Fig. A.3 where the two-port networks are connected in series. We have
A = z A I A
V
B = y B I B
V (A.15)
I1 + IA, 1 IA, 2 + I2
+ Two-port +
VA, 1 network VA, 2
A
− −
V1 V2
+ IB, 1 IB, 2 +
Two-port
VB, 1 network VB, 2
− B −
− −
Fig. A.3 Two-port networks connected in series

where

z A, 11 z A, 12
z A =
z A, 21 z A, 22

z B, 11 z B, 12
z B = (A.16)
z B, 21 z B, 22
A, V
denote the impedance matrices for networks A and B respectively and V B , I A and
I B are given by (A.7). From Fig. A.3 we have
I1 = IA, 1
I2 = IA, 2
V1 = VA, 1 + VB, 1
V2 = VA, 2 + VB, 2 . (A.17)
If we further impose the constraint that
IA, 1 = IB, 1
IA, 2 = IB, 2 (A.18)
(this can happen when the two ports of network A are isolated, that is, z A, 12 = z A, 21 =
0), then from (A.15), (A.16), (A.17) and (A.18) we obtain
A +V
V B = (z A + z B ) I
⇒V = z I (A.19)
where I and V
are defined in (A.4) and
z A + z B = z. (A.20)
Thus, when two, two-port networks are connected in series, the resulting impedance
matrix is the sum of the individual impedance matrices, provided the two ports of network
A are isolated.
3. The hybrid parameters are given by:
V1 = h11 I1 + h12 V2

I2 = h21 I1 + h22 V2 (A.21)
where

V1
h11 =
I1 V =0
2
V1

h12 =
V2 I =0
1
I2
h21 =
I1 V =0
2
I2
h22 = . (A.22)
V2
I1 =0
Note that I1 = 0 implies that port 1 is open-circuited, and V2 = 0 implies that port 2 is
short-circuited.
4. The transmission parameters are given by:
V1 = t11 V2 − t12 I2

I1 = t21 V2 − t22 I2 (A.23)
where

V1
t11 =
V2 I =0
2
V1

t12 =
I2 V =0
2
I1
t21 =
V2 I =0
2
I1
t22 = . (A.24)
I2 V =0
2
Note that I2 = 0 implies that port 2 is open-circuited, and V2 = 0 implies that port 2 is
short-circuited. Now, (A.23) can be written in matrix form as

V1 V2
=t (A.25)
I1 − I2
where

t = t11 t12 . (A.26)
t21 t22
Now, consider Fig. A.4 where the two-port networks are connected in cascade. We have
+ IA, 1 IA, 2 + + IB, 1 IB, 2 +

Two-port Two-port
VA, 1 network VA, 2 VB, 1 network VB, 2
A B
− − − −
Fig. A.4 Two-port networks connected in cascade

VA, 1 VA, 2
= t A
IA, 1 − IA, 2

VB, 1 VB, 2
= t B (A.27)
IB, 1 − IB, 2
where

tA, 12
t A = t A, 11
tA, 21 tA, 22

tB, 12
t B = t B, 11 . (A.28)
tB, 21 tB, 22
Now, from Fig. A.4 we have
VA, 2 = VB, 1
− IA, 2 = I B, 1 . (A.29)
Substituting (A.29) in (A.27) we obtain:

VA, 1 VB, 2
= t A t B . (A.30)
IA, 1 − IB, 2
Thus, when two-port networks are connected in cascade, the transmission matrices are
multiplied.
Bibliography
1. M. Halkias, Integrated Electronics (Tata McGraw-Hill Publishing Company, McGraw-Hill Elec-

trical and Electronic Engineering Series, 2001)
2. W.H. Hayt, J.E. Kemmerly, (Jack Ellsworth), S.M. Durbin, Engineering Circuit Analysis, 8th edn.
(McGraw-Hill, New York, 2012). Includes index
3. S.P. Smith, Problems in Electrical Engineering: With Answers (Constable, 1954)
4. S. Adel, Sedra and Kenneth C, 5th edn. (Smith. Microelectronic Circuits Revised Edition. Oxford
University Press Inc, New York, NY, USA, 2007)
https://doi.org/10.1007/978-3-031-09363-0
Index
A Current
Amplitude, 72 division, 12
peak, 86
phasor, 86
B rms, 86
Battery, 14 saturation, 257
Bipolar junction transistor, 197 short-circuit, 9
ac analysis, 217 source
biasing, 198 independent, 1
active region, 197
cut-off region, 197
saturation region, 197 D
hybrid model, 217 Decoder, 266
npn, 197 Demultiplexer, 266
pnp, 198 strobe, 266
Bode plot Diode
magnitude, 115 cut-in voltage, 168
phase, 115 forward bias current, 168
Boolean forward resistance, 179
function ideal, 163
minimized, 260 peak current, 182
POS form, 262 zener, 168
SOP form, 260 breakdown voltage, 168
variable, 265 knee current, 168
complement, 265 reverse bias current, 168
Divide-by-2, 273
Don’t care, 281
C
Capacitor, 40
Clock, 273 F
Combinational circuits, 259 Feedback
https://doi.org/10.1007/978-3-031-09363-0
296 Index
negative, 248 M
positive, 235 Maximum power transfer, 89
Flip-flop Mesh analysis (KVL), 2
characteristic equation, 273 supermesh, 4
D, 273 Most significant bit (MSB), 265
J K , 273 Multiplexer, 263
negative edge triggered, 273 control signal, 265
positive edge triggered, 273
state, 273
T , 273 N
transition table, 273 Nodal analysis (KCL), 3
Frequency, 99 supernode, 5
resonant, 111 Norton
Full-adder, 262 equivalent, 40
carry-out, 262 Number system, 260
sum, 262 binary, 259
conversion, 259
decimal, 259
G octal, 259
Gates reminder, 259
NAND, 260
NOR, 262
O
Op amp
CMRR, 249
H
common mode gain, 250
Half-power bandwidth, 145
comparator, 252
difference amplifier, 249
differential mode gain, 250
I
filter, 230
Impedance, 99
ideal, 229
input, 217
Schmitt trigger, 236
output, 217
hysteresis loop, 236, 237
Inductor, 39
non-inverting, 252
Internal resistance
squarer, 258
parallel, 15
triangular wave generator, 252
series, 14
Oscillator, 243
Barkhausen criterion, 243
K
Kirchoff’s P
current law, 3 Passive sign convention, 24
voltage law (KVL), 1 Power
K-map, 260 dissipated (absorbed), 2
factor, 100
supplied, 3
L
Least Significant Bit (LSB), 265
Linearity, 7 Q
Linear network, 7 Quality factor, 145
Index 297
R RC, 40
Reactance, 99 RL, 40
admittance, 114 Truth table, 262
Rectifier Two-port network, 124
full-wave, 184 admittance parameters, 132
half-wave, 182 hybrid parameters, 128
Resistance impedance parameters, 133
negative, 255 reciprocal, 132
Resistor, 4 transmission parameters, 124
S
V
Sequential circuits, 273
Voltage
Source
drop, 1
dependent, 7
gain
independent, 7
small signal, 217
Source transformation, 40
open-circuit, 124
Square wave, 72
peak, 85
Superposition, 7
phasor, 85
regulator, 190
T line regulation, 190
Thevenin load regulation, 190
equivalent, 8 ripple, 182
resistance, 8 rise, 1
voltage, 8 rms, 85
Time period, 72 source
Transfer function, 116 independent, 5
Transient thermal, 257

Basic Electronic Circuits - Problems and Solutions

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K.

ISBN 978-3-031-09362-3 ISBN 978-3-031-09363-0 (eBook)

Jointly published with ANE Books India

• Dr. Surendra Prasad, IIT Delhi, India

Kanpur, India K. Vasudevan

Appendix: Two-Port Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

K. Vasudevan completed his Bachelor of Technology (Honours) from the department of

I Real-valued, constant current

Constant independent voltage source

Constant independent current source

Sinusoidal or time-varying independent voltage source.

Sinusoidal or time-varying independent current source.

Constant or time-varying dependent voltage source

Constant or time-varying dependent current source

Basic Electronics: Problems and Solutions

Electrolytic or polar capacitor

Potentiometer or variable resistor

An npn bipolar junction transistor

A pnp bipolar junction transistor

1. In Fig. 1.1, find I1 , I2 and V1 .

Solving (1.2), we get

© The Author(s) 2023 1

Fig. 1.1 A circuit 1Ω

Fig. 1.2 A circuit 3Ω

Solving (1.4), we get

− V1 − 3I1 − 2(I1 − I2 ) − 2Vx = 0

Fig. 1.3 A circuit

Solving (1.7), we get

The power dissipated in the 3 A current source is

3V1 = −810/11 watts. (1.9)

– Solution: Refer to Fig. 1.4. Note that Vd = 4 V. At node b, we have

Fig. 1.4 A circuit

Moreover, assuming voltage drop is negative and voltage rise is positive

Therefore, the power supplied by the 6 A current source is 49 × 6 = 294 W.

Fig. 1.5 A circuit

The KVL equation for the supermesh cde f c is

− 4(I3 − I1 ) − 3(I2 − I1 ) − 3I x − 6I3 = 0. (1.14)

From (1.13) and (1.14), we get

The KVL for mesh 1 is

Vb + 10 − 4(5 + 1) − 3(I1 − I2 ) − 4(I1 − I3 ) = 0

Fig. 1.6 A circuit

Applying KCL to the supernode d, f and the 6 V source, we obtain

The mesh currents can be computed as follows:

Fig. 1.7 A circuit IB

7. In Fig. 1.7, when V A = 2 V and I B = 3 A, I L = 6 A. Similarly, when V A = 1 V and

– Solution: Due to linearity and superposition we have

Solving we get K 1 = 18/7 and K 2 = 2/7. When V A = 3 V and I B = 4 A, we

8. In Fig. 1.8, when V A = 3 V and I B = 5 A, VL = 4 V. Similarly, when V A = 2 V and

– Solution: Due to linearity and superposition, we have

Fig. 1.8 A circuit

Solving we get K 1 = −12/11 and K 2 = 16/11 . When V A = 3 V and I B = 4 A,

Fig. 1.9 A circuit

The short-circuit current ISC, 1 through X Y is given by

The modified circuit to compute the Thevenin voltage across X Y , considering I B

Fig. 1.11 To compute 4Ix2 V

Using superposition, the overall Thevenin voltage across X Y is

VTH = VTH, 1 + VTH, 2

The Thevenin resistance across X Y is

RTH = RTH, 1 = RTH, 2

In order to compute ISC, 1 , we apply KCL in node b in Fig. 1.13 to obtain

Fig. 1.12 A circuit

ISC, 1 = −4I x . (1.35)

Applying KVL in the loop abcda of Fig. 1.13, we get