Deld (Ar20) Wov

Digital Electronics & Logic Design Lab B.
Tech III semester
ADITYA ENGINEERING COLLEGE(A)

Approved by AICTE , Affiliated to JNTUK & Accredited by NAAC with 'A' Grade
Recognized by UGC under the sections 2(f) and 12(B) of the UGC act 1956
Aditya Nagar, ADB Road, Surampalem – 533 437
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
DIGITAL ELECTRONICS AND LOGIC DESIGN LABORATORY
LIST OF EXPERIMENTS
B.Tech –III SEMESTER Regulation: AR20
1. Functional verification of logic gates.
2. Develop basic logic gates using universal gates.
3.Verification of De-Morgan'slaws.
4.Design a logic circuit for a given Boolean expression.
5.Design Full adder circuit and verify its truth table.
6. Design a combinational logic circuit for 8 to 1MUX.

7.Verification of functional table of 3 to 8 line Decoder/De-multiplexer.
8.Verify the truth tables of Basic Flip-flops.
9. Design a synchronous decade counter.
10. Design an 8-bit right shift register using D Flip-flop and verify the truth table.
11. Design BCD to Seven Segment Display Decoder.
12. Verify the operation of 4-bit Universal Shift Register for different Modes of operation.
AUGMENTED EXPERIMENTS
13. Design an Experimental model to demonstrate the operation of 74154 De Multiplexer
using LEDs for outputs.
14. Design BCD Adder Circuit and Test the Same using Relevant IC.
Dept. of ECE, Aditya Engineering College(A) 1

Digital Electronics & Logic Design Lab B.Tech III semester

VERIFICATION OF LOGIC GATES

NOT gate:
Truth Table
INPUTS OUTPUT VERIFIED

OUTPUT
A B=Ā ON/OFF
0 1
1 0
AND gate:
Truth Table

OUTPUT
A B Y=A.B ON/OFF
0 0 0
0 1 0
1 0 0
1 1 1


Exp No:1 Date:
VERIFICATION OF LOGIC GATES
AIM: To verify the behavior (or truth table) of logic gates using IC s
APPARATUS REQUIRED:
S.NO EQUIPMENT /COMPONENT NAME QUANTITY
1. Component development system (bread board trainer) 1
2. IC 7400 (NAND) 1
3. IC 7402 (NOR) 1
4. IC 7404 (NOT) 1
5. IC 7408 (AND) 1
6. IC 7432 (OR) 1
7. IC 7486 (EX-OR) 1
8. IC 74266 (EX-NOR) 1
9. Patch chords & Connecting Wires As per Required
THEORY:
 The NAND gate performs the logical AND-INVERT of two variables A and B produces an output C.
 The NOR gate performs the logical OR-INVERT of two variables A and B produces an output C.
 The NOT gate performs the logical INVERT of input variable A and produces an output B.
 The AND gate performs the logical AND of two variables A and B produces an output C.
 The OR gate performs the logical OR of two variables A and B produces an output C.
 The EX-OR gate performs the logical EX-OR of two variables A and B produces an output C.

OR gate:
Truth Table

OUTPUT
A B Y=A+B
ON/OFF
0 0 0
0 1 1
1 0 1
1 1 1
NAND gate:
Truth Table

OUTPUT
A B ON/OFF
0 0 1
0 1 1
1 0 1
1 1 0

PROCEDURE:
 NOT Gate:
1. Take the component development system (bread board) and insert the IC 7404 at appropriate position.
2. Connect pin No 14 to 5V and pin No.7 to GND.
3. Apply the logic input and take the output for different inputs.
 AND Gate:
1. Insert IC 7408 at appropriate position on component development system.
3. Apply the logic inputs and take the output for different combinations of inputs.
 OR Gate:
 NAND Gate
1. Take the component development system(bread board) and insert the IC 7400 at appropriate position.
2. Connect pin No 14 to 5V and pin No.7 to GND


NOR gate:
Truth Table

OUTPUT
A B ON/OFF
0 0 1
0 1 0
1 0 0
1 1 0
EX-OR gate:
Truth Table
OUTPUT VERIFIED
INPUTS OUTPUT
A B ON/OFF
0 0 0
0 1 1
1 0 1
1 1 0

 NOR Gate:
 EX-OR Gate:

Exclusive-NOR gate:
Truth Table
OUTPUT VERIFIED
INPUTS OUTPUT
A B ON/OFF
0 0 1
0 1 0
1 0 0
1 1 1

RESULT:


DEVELOP BASIC LOGIC GATES USING UNIVERSAL GATES

2 input AND gate using NAND gates AND gate Truth Table

OUTPUT
A B Y=A.B ON/OFF
AND gate realization using NAND
0 0 0
0 1 0
1 0 0
1 1 1
2- input OR gate using NAND gate: OR gate Truth Table

OUTPUT
A B Y=A+B
ON/OFF
0 0 0
OR gate realization using NAND gate
0 1 1
1 0 1
1 1 1

Exp No: 2 Date:
DEVELOP BASIC LOGIC GATES USING UNIVERSAL GATES
AIM: To implement all basic gates with Universal Gates (NAND & NOR) using ICs
APPARATUS REQUIRED:
2. IC 7400 (NAND) 1
3. IC 7402 (NOR) 1
THEORY:
The “Universal” NAND Gate: The Logic NAND Gate is generally classed as a “Universal” gate because it is one of the most
commonly used logic gate types. NAND gates can also be used to produce any other type of Ni gate function, and in practice the NAND
gate forms the basis of most practical logic circuits. By connecting them together in various combinations the three basic gate types of
AND, OR and NOT function can be formed using only NAND‘s.
Commonly available Digital Logic NAND Gate IC’s include:
TTL Logic NAND Gates CMOS Logic NAND Gates
74LS00 Quad 2-input CD4011 Quad 2-input
74LS10 Triple 3-input CD4023 Triple 3-input
74LS20 Dual 4-input CD4012 Dual 4-input
74LS30 Single 8-input
The “Universal” NOR Gate: Like the NAND gate seen in the last section, the NOR gate can also be classed as a “Universal”
type gate. NOR gates can be used to produce any other type of logic gate function just like the NAND gate and by connecting them
together in various combinations the three basic gate types of AND, OR and NOT function can be formed using only NOR‘s. As well
as the three common types above, Ex-Or, Ex-NOR gates can also be formed using just individual NAND / NOR gates.

NOT gate using NAND gate: Truth Table:

OUTPUT
A Y=Ā
0 1
NOT gate realization using NAND gate :

1 0
Fig: Realization of basic gates using NAND gate
2 input AND gate using NOR gates Truth Table

OUTPUT
A B Y=A.B ON/OFF
0 0 0
Realization of OR gate using NOR gate:
0 1 0
1 0 0
1 1 1

Commonly available neither Digital Logic NOR Gate IC does include:

TTL Logic NOR Gates CMOS Logic NOR Gates
74LS02 Quad 2-input CD4001 Quad 2-input
74LS27 Triple 3-input CD4025 Triple 3-input
74LS260 Dual 4-input CD4002 Dual 4-input
PROCEDURE:
AND Gate Realization:
1. Take the component development system(bread board) and insert the IC 7400/7402 at appropriate position
on component development system respectively.
2. Connect pin No 14 to 5v and pin No.7 to GND.
OR Gate Realization:
1. Take the component development system(bread board) and insert the IC 7400/7402 at appropriate position
on component development system respectively.
NOT Gate Realization:
1. Insert IC 7400/7402 at appropriate position on component development
system.

2 input OR gate using NOR gates OR gate Truth Table

OUTPUT
A B Y=A+B
ON/OFF
0 0 0
Realization of OR gate using NOR gate 0 1 1
1 0 1
1 1 1
NOT gate using NAND gate: NOT gate Truth Table

OUTPUT
Realization of NOT gate using NOR gate A Y=Ā ON/OFF
0 1
1 0
Fig: Realization of basic gates using NOR gate

RESULT:


VERIFICATION OF DE - MORGAN’S LAWS

REALIZATION OF DE-MORGAN’S LAWS

1.DEMORGAN’S FIRST LAW :- =
Fig: Logic diagram of Demorgan’s First Law
Fig. connection diagram for De-Morgan’s laws realization

TRUTH TABLE OF DEMORGAN’S FIRST LAW
A B VERIFIED VERIFIED
OUTPUT OUTPUT
0 0
0 1
1 0
1 1

Exp No:3 Date:
VERIFICATION OF DE - MORGAN’S LAWS
AIM: To verify the De-Morgan’s laws (or truth table) by using basic gates IC’s
APPARATUS REQUIRED:
2. IC 7404 (NOT) 1
3. IC 7408 (AND) 1
4. IC 7432 (OR) 1
THEORY:
De-Morgan’s Theorems, two extremely important logic laws are called De Morgan’s Theorems. They are
stated as follows
1. = the complement of the PRODUCT=the SUM of the complements
2. = the complement of the SUM = the PRODUCT of the
complements De-Morgan’s theorem makes it easy to transform POS to SOP or SOP to POS
forms.

2.DEMORGAN’S SECOND LAW :- =
Fig: Logic diagram of Demerger’s Second Law
Fig. connection diagram for De-Morgan’s laws realization
TRUTH TABLE OF DEMORGAN’S SECOND LAW
A B VERIFIED VERIFIED
OUTPUT OUTPUT
0 0
0 1
1 0
1 1

PROCEDURE:
1) According to the pin configuration of ICs, perform the connections.
2) Apply the different inputs and observe the outputs.
3) Verify the outputs according to the truth tables.
RESULT:


DESIGN OF LOGIC CIRCUIT FOR A BOOLEAN EXPRESSION

K-MAP :
LOGIC DIAGRAM:

Exp No:4 Date:
DESIGN OF LOGIC CIRCUIT FOR A BOOLEAN EXPRESSION
AIM: Implementation of the given Boolean Function using Logic Gates in Both Sop and Pos Forms.
APPARATUS REQUIRED:
2. IC 7404 (NOT) 1
3. IC 7408 (AND) 1
4. IC 7432 (OR) 1
THEORY:
A Boolean expression is a logical statement that is either TRUE or FALSE. Boolean expressions can compare
data of any type as long as both parts of the expression have the same basic data type. You can test data to see
if it is equal to, greater than, or less than other data. Karnaugh maps are the most extensively used tool for
simplification of Boolean functions. It is mostly used for functions having up to six variables beyond which it
becomes very cumbersome. In an n- variable K-map there are 2ⁿ cells. Each cell corresponds to one of the
combination of n variable, since there are 2ⁿ combinations of n-variables. Gray code has been used for the
identification of cells. The basic logic gates are the building blocks of more complex logic circuits. These
logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR,
Exclusive-NOR. All the combinational circuits are designed using these gates.

TRUTH TABLE:
A B C AB AC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

PROCEDURE:
1) According to the pin configuration of ICs, perform the

connections.
2) Apply the different inputs and observe the outputs.
3) Verify the outputs according to the truth tables.
RESULT:


DESIGN OF FULL ADDER CIRCUIT

Logic Diagram Of Full Adder Using Two Half Adders
S=ABCinCout = AB+ACin+BCin

Exp No:5 Date:
DESIGN OF FULL ADDER CIRCUIT
AIM: To construct Full Adder using Half Adder and verify Truth Table.
APPARATUS REQUIRED:
2. IC 7404 (NOT) 1
3. IC 7408 (AND) 1
4. IC 7432 (OR) 1
5. IC 7486 (EX-OR) 1
THEORY:
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs
and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum
output will be taken from X-OR Gate, carry output will be taken from OR Gate.
The full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is
an input carry. When a full adder logic is designed we will be able to string eight of them together to create a
byte-wide adder and cascade the carry bit from one adder to the next.


PROCEDURE:
1. Connect the trainer kit to ac power supply.
2. Connect logic sources to the inputs of the adder.
3. Connect output from SUM and CARRY to logic indicators.
4. Apply various input combinations to the adder.
5. Observe the SUM and CARRY outputs, verify the truth table for each input/ output combination.
6. Switch off the ac power supply.
RESULT:


DESIGN OF 8*1 MULTIPLEXER

PIN DIAGRAM OF 74151 (8 *1 MUX)
LOGIC DIAGRAM FOR 8*1 MULTIPLEXER

Exp No:6 Date:
DESIGN OF 8*1 MULTIPLEXER
AIM: To design and implement multiplexer using IC 74151

APPARATUS REQUIRED:
2. Multiplexer IC (74151) 1
Multiplexer:
This component contains a multiplexer for Boolean values. The multiplexer routes one of the input
values to the output connector. The selected input connector depends on the address read from the address
inputs.
The component has an internal address latch. This latch is activated if the optional connector 'Enable
Latch Address' is activated. During true condition at this input the current address is used. A change to false
condition latches the address. During false condition at this input the latched address is used. The latch is
bypassed if the optional connector 'Enable Latch Address' is deactivated.
The component also has an internal output latch. This latch is activated if the connector 'Enable
Latch Output' is activated. During true condition at this input the current addressed input value is used. Change
to false condition latches the output value. During false condition at this input the latched output value is used.
The latch is bypassed if the optional connector 'Enable Latch Output' is deactivated.
If an input is addressed which does not exist (e.g. the 15th input is selected but the component has only 14
inputs) the reset value is used

TRUTH TABLE of 74151(8 *1 MUX)
E S2 S1 S0 Y Y
0 0 0 0 D0
0 0 0 1 D1
0 0 1 0 D2
0 0 1 1 D3
0 1 0 0 D4
0 1 0 1 D5
0 1 1 0 D6
0 1 1 1 D7

Demultiplexer:
This component contains a demultiplexer for Boolean values. The demultiplexer routes the input value to one of
the output connectors. The selected output connector depends on the address read from the address inputs.
The component has an internal address latch. This latch is activated if the optional connector 'Enable Latch
Address' is activated. During true condition at this input the current address is used. A change to false condition
latches the address. During false condition at this input the latched address is used. The latch is bypassed if the
optional connector 'Enable Latch Address' is deactivated.
The component also has an internal output latch. This latch is activated if the
Connector Enable Latch Output' is activated. During true condition at this input the latch is bypassed. A change to
false condition latches the last output values. During false
condition at this input the latched output values are used. The latch is bypassed if the optional
connector 'Enable Latch' is deactivated
PROCEDURE:
1. Insert the IC 74151 at appropriate portion of component development system.

2. Give VCC and GND connections.
3. Apply logic inputs as per mode selection table and observe outputs.
RESULT:


3 TO 8 LINE DECODER/DE-MULTIPLEXER

PIN DIAGRAM OF 74138(3 TO 8 LINE DECODER/DE-MULTIPLEXER)
LOGIC DIAGRAM (POSITIVE LOGIC)

Exp No:7 Date:
3 TO 8 LINE DECODER/DE-MULTIPLEXER
AIM: To verify the truth tables of 3 to 8 line decoder/de-multiplexer.
APPARATUS REQUIRED:
2. De-Multiplexer IC (74138) 1
THEORY:
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of
system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this
decoder and the enable time of the memory usually are less than the typical access time of the memory. This
means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment

FUNCTION TABLE

PROCEDURE:

RESULT:


VERIFICATION OF BASIC FLIP-FLOPS

RS FLIP FLOP
Logic symbol Logic diagram
TRUTH TABLE:
JK FLIP FLOP
LOGIC SYMBOL LOGIC DIAGRAM

Exp No:8 Date:
VERIFICATION OF BASIC FLIP-FLOPS

AIM: To verify the truth tables of RS, D & JK Flip-Flops.
APPARATUS REQUIRED:
2. IC 7404 (NOT) 1
3. IC 7411 ( 3 Pin AND) 1
4. IC 7402 (NOR) 1
5. IC 7400(NAND) 1
6. IC 7474(D- Flip Flop) 1
7. IC 7476(JK- Flip Flop) 1
8.. Patch chords & Connecting Wires As per Required
THEORY:
A Flip Flop is a sequential device that samples its input signals and changes its output states only at times
determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which
the inputs affect the binary states.
RS Flip Flop:
The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input
on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates
in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is
set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate
state.
D FLIP FLOP:
To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are
high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by
making the two inputs complement of each other.

PIN DIAGRAM OF IC 7476 (JK FLIP FLOP )
JK FLIP FLOP:
Truth Table
Clk J K Q Ǭ State
1 0 0 Q Q1 No Change
1 0 1 0 1 Reset Q to 0
1 1 0 1 0 Set Q to 1
1 1 1 - - Toggle
D FLIP FLOP:
LOGIC SYMBOL LOGIC DIAGRAM
PIN DIAGRAM OF IC 7474 (D FLIP FLOP)
Truth Table:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R
inputs to set and reset the Flip Flop. The output Q is Handed with K input and the clock pulse, similarly the output
Q‟ is Handed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and
the Q and Q‟ output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR
gates. When both the inputs are high the output toggles continuously. This is called Race around condition and
this must be avoided.
PROCEDURE:
1. Connect the trainer kit to ac power supply
2. Connect the logic inputs for RS flip flop. Give the clock input from pulser.
3. Observe the outputs at the output terminals.
4. Verify the truth table of RS flip-flop.
5. Repeat the same procedure for D and JK flip-flops.
6. For JK flip-flop give the high clock and observe the output.
RESULT:


DESIGN A SYNCHRONOUS DECADE COUNTER

PIN DIAGRAM OF IC 7490 (DECADE COUNTER)
TRUTH TABLE:

ExpNo: 9 Date:
DESIGN A SYNCHRONOUS DECADE COUNTER
AIM: To verify the function of IC 7490 Decade counter.

APPARATUS REQUIRED:
2. IC (7490) 1
THEORY:
Counters:
A counter is a sequential circuit that counts in a cyclic sequence. It is essentially a register that goes
through a predetermined sequence of states upon the application of input pulses. There are two types of counters
– Synchronous Counter & Asynchronous Counter.
Synchronous Counter
In a synchronous counter, the input pulses are applied to all clock pulse inputs of all flip flops
simultaneously (directly). Synchronous counter is also known as parallel sequential circuit.
Asynchronous Counter
In an asynchronous counter, the flip flop output transition serves as a source for triggering other flip flops.
In other words, the clock pulse inputs of all flip flops, except the first, are triggered not by the incoming pulses,
but rather by the transition that occurs in previous flip flop‟s output.. Asynchronous counter is also known as
serial sequential circuit.
 A counter having n flip flops can have 2n output states ie., it can count 2n clock pulses (0- 2n-1)
 The largest binary number that can be represented by an n bit counter has a decimal equivalent of 2 n-1 .
example: n=3, then 2n-1= 23-1=7

COUNT SEQUENCE TABLE:

 A counter can be either in the up mode or in the down mode

 The modulus of a counter is the total number of states through which the counter can progress. For
example mod-8 counter is having 8 different states (000-111), it need
 3 flip-flops (2n=8 i.e., n represents no of flip flops)
 A decade counter is also called as mod-10 or %10 counter requires 4 flip flops
Synchronous counters are faster than asynchronous counter because in synchronous counter all flip flops
are clocked simultaneously
PROCEDURE:
2. Give VCC and GND connections
3. Apply the logic inputs as per mode selection table and observe the outputs.
4. Apply the logic inputs for count option.
5. Observe the decade count output by giving clock.
6. Note that Q0 should be connected to P,
7. To get the mod-S counter apply clock to Cr1 and the output from Q3,Q2,Q1
RESULT:


DESIGN AN 8- BIT RIGHT SHIFT REGISTER USING D - FLIP FLOP

BLOCK DIAGRAM OF 8-BIT RIGHT SHIFT REGISTER:
PIN DIAGRAM Of IC 74164 (8-Bit Right Shift Register)

Exp.No: 10 Date:
DESIGN AN 8- BIT RIGHT SHIFT REGISTER USING D - FLIP FLOP
AIM: To design an 8- bit right shift register using IC74164.

APPARATUS REQUIRED:
2. IC (74164) 1
THEORY:
The operation is as follows. Lets assume that all the flip-flops ( 1 to 8 ) have just been RESET ( CLEAR
input ) and that all the outputs Q0 to Q7 are at logic level “0” i.e., no parallel data output.
If a logic “1” is connected to the DATA input pin of FF1 then on the first clock pulse the output of FF1
and therefore the resulting Q0 will be set HIGH to logic “1” with all the other outputs still remaining LOW at
logic “0”. Assume now that the DATA input pin of FF1 has returned LOW again to logic “0”.
The second clock pulse will change the output of FF1 to logic “0” and the output of FF2 and Q 1 HIGH to
logic “1” as its input D has the logic “1” level on it from Q0. The logic “1” has now moved or been “shifted” one
place along the register to the right as it is now at Q0.
When the third clock pulse arrives this logic “1” value moves to the output of FF3 ( Q2 ) and so on until
the arrival of the fifth clock pulse which sets all the outputs Q 0 to Q7 back again to logic level “0” because the
input to FF1 has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is
shown in the following table until the complete data value of 0-0-0-0-0-0-0-1 is stored in the register. This data
value can now be read directly from the outputs of Q0 to Q7.
Then the data has been converted from a serial data input signal to a parallel data output. The truth table shows
the propagation of the logic “1” through the register from left to right as follows

TRUTH TABLE:
Clock Pulse no Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
2 0 1 0 0 0 0 0 0
3 0 0 1 0 0 0 0 0
4 0 0 0 1 0 0 0 0
5 0 0 0 0 1 0 0 0
6 0 0 0 0 0 1 0 0
7 0 0 0 0 0 0 1 0
8 0 0 0 0 0 0 0 1
9 0 0 0 0 0 0 0 0
FUNCTIONAL TABLE
INPUTS OUTPUTS
CLR CLK A B OA OB OC OD OE OF OG OH
L X X X L L L L L L L L
H L X X OA0 OB0 OC0 OD0 OE0 OF0 OG0 OH0
H ↑ H H H OAn OBn OCn ODn OEn OFn OGn
H ↑ L X L OAn OBn OCn ODn OEn OFn OGn
H ↑ X L L OAn OBn OCn ODn OEn OFn OGn

PROCEDURE:
1. Connect the D- flip-flops in a sequential manner.
2. Set the CLR signal to reset all the flip-flops initially.
3. Apply data input signal at the input of the AND gate.
4. Apply a clock signal, and verify the operation of a shift register.
RESULT:


BCD TO 7 SEGMENT DISPLAY DECODER

PIN DIAGRAM OF SEVEN SEGMENT DISPLAY
PIN DIAGRAM OF IC7446 to SEVEN SEGMENT DISPLAY

Exp.No: 11 Date:
BCD TO 7 SEGMENT DISPLAY DECODER
AIM: To verify the truth table of BCD to 7 Segment Display
APPARATUS REQUIRED:
2. IC (7446/47) 1
3. Segment Display 1
4. Resistor-220 ohms 7
THEORY:
A decoder is a combinational circuit that connects the binary information from „n‟ input lines to a maximum of
2n unique output lines. The IC7447 is a BCD to 7-segment pattern converter. The IC7447 takes the Binary Coded
Decimal (BCD) as the input and outputs the relevant 7 segment code.
The Light Emitting Diode (LED) finds its place in many applications in these modern electronic fields. One of
them is the Seven Segment Display. Seven-segment displays contains the arrangement of the LEDs in “Eight”
(8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The purpose of arranging it in that
passion is that we can make any number out of that by switching ON and OFF the particular LED‟s.
The Light Emitting Diode (LED), finds its place in many applications in this modern electronic fields. One of
them is the Seven Segment Display. Seven-segment displays contains the arrangement of the LEDs in “Eight”
(8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The purpose of arranging it in that
passion is that we can make any number out of that by switching ON and OFF the particular LED‟s. Here is the
block diagram of the Seven Segment LED arrangement.

TRUTH TABLE:
OUTPUT (Seven Segment)

INPUTS
OUTPUT
DIGIT (DISPLAY) a b c d e f g
D C B A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

PROCEDURE:
1. Connect the trainer kit to ac power supply

2. Connect Inputs A, B, C, D to Input Switches.
2. Connect 7-Segment Outputs (a, b, c, d, e, f, g) to Output Switches.
3. Verify the output display observe the LED outputs.
RESULT:


4-BIT UNIVERSAL SHIFT REGISTER

PIN DIAGRAM OF 4-BIT UNIVERSAL SHIFT REGISTER

Exp No: 12 Date:
4-BIT UNIVERSAL SHIFT REGISTER
AIM: To Verify the Truth Table of 4-Bit Universal Shift Register
APPARATUS REQUIRED:
2. IC (74LS194) 1
THEORY:
Today, high speed bi-directional "universal" type Shift Registers such as the TTL 74LS194,
74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in either serial-to-
serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, and as a parallel-to-parallel
multifunction data register, hence the name "Universal". These devices can perform any combination of
parallel and serial input to output operations but require additional inputs to specify desired function and to
pre-load and reset the device.
Universal shift registers are very useful digital devices. They can be configured to respond to operations
that require some form of temporary memory, delay information such as the SISO or PIPO configuration modes
or transfer data from one point to another in either a serial or parallel format. Universal shift registers are
frequently used in arithmetic operations to shift data to the left or right for multiplication or division.

LOGIC DIAGRAM
FUNCTIONAL DIAGRAM

PROCEDURE:
1. Insert the IC 74LS194 at appropriate portion of component development system.

RESULT:


AUGMENTED EXPERIMENTS


4-LINE TO 16-LINE DECODER/DEMULTIPLEXER

PIN DIAGRAM:
TRUTHTABLE
Inputs Outputs
G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L L L L L L L H H H H H H H H H H H H H H H
L L L L L H H L H H H H H H H H H H H H H H
L L L L H L H H L H H H H H H H H H H H H H
L L L L H H H H H L H H H H H H H H H H H H
L L L H L L H H H H L H H H H H H H H H H H
L L L H L H H H H H H L H H H H H H H H H H
L L L H H L H H H H H H L H H H H H H H H H
L L L H H H H H H H H H H L H H H H H H H H
L L H L L L H H H H H H H H L H H H H H H H
L L H L L H H H H H H H H H H L H H H H H H
L L H L H L H H H H H H H H H H L H H H H H
L L H L H H H H H H H H H H H H H L H H H H
L L H H L L H H H H H H H H H H H H L H H H
L L H H L H H H H H H H H H H H H H H L H H
L L H H H L H H H H H H H H H H H H H H L H
L L H H H H H H H H H H H H H H H H H H H L
L H X X X X H H H H H H H H H H H H H H H H
H L X X X X H H H H H H H H H H H H H H H H
H H X X X X H H H H H H H H H H H H H H H H
H HIGH LevelL Low Level X Don’t Care

Exp No:13 Date:
4-LINE TO 16-LINE DECODER/DEMULTIPLEXER
AIM:
To verify the truth tables of 3 to 8 line decoder/de-multiplexer.
APPARATUS REQUIRED:
2. Multiplexer IC (74154) 1
THEORY:
The 74HC154; 74HCT154 is a 4-to-16 line decoder/demultiplexer. It decodes four binary weighted address inputs
(A0 to A3) to sixteen mutually exclusive outputs (Y0 to Y15). The device features two input enable (E0 and E1)
inputs. What is a 4/16 decoder 4-to-16 decoder consists of 4 inputs and 16 outputs. Similar to all the decoders
discussed above, in this also only one output will be low at a given time and all other outputs are high (using
maxterms). The truth table of this type of decoder

LOGIC DIAGRAM:

PROCEDURE:

RESULT:


DESIGN AND IMPLEMENTATION OF BCD ADDER

PIN DIAGRAM:
Pin no. 1(A4), 3(A3), 8(A2), 10(A1) are subjected to give first 4-bit numbers as input 1.
Pin no. 16(B4), 4(B3), 7(B2), 11(B1) are subjected to give the second 4-bit number as input 2.
Pin no. 15(S4), 2(S3), 6(S2), 9(S1) are the output pins to collect the data after addition.
Pin no. 14(C4) is for input carry.
Pin no. 13(C0) is for output carry.
Pin no. 5 is Vcc for Positive power supply.
Pin no. 12 is GND for negative power supply.
TRUTHTABLE

Exp No:14 Date:
DESIGN AND IMPLEMENTATION OF BCD ADDER
AIM:
To design and implement BCD adder using 4 bit binary adder IC 7483.
APPARATUS REQUIRED:
2. IC 7483(4 BIT BINARY ADDER) 1
3. IC 7408 (AND) 1
4. IC 7432 (OR) 1
THEORY:
BCD ADDITION:
Binary Coded Decimal is a method of using binary digits to represent the decimal digits 0
through 9.The valid BCD numbers are (0000to1001) BCD. Each digit of the decimal
number will be represented by its four bit binary equivalent.
Ex: (127) 10-BCD equivalent (000100100111)2.

In BCD addition the following three cases are observed,
1. The resulting BCD number equal to less than(1001)BCD.
2. The resulting BCD number greater than(1001)BCD.
3. Carry is generated in the BCD addition.
For case 2 and 3, the result is added with correction factor (0110) BCD so that the result is
in valid BCD number.

LOGIC DIAGRAM:
BCDADDER:

BCD Adder:
The two BCD inputs to be added are applied at inputs A and B of the first binary adder
IC7483. The sum output of the first binary adder is given to the B input of the second
binary adder. The A input of the binary adder is given (0110) BCD when a carry is
generated from the first adder or when sum from the first binary adder is greater than
(0110)BCD, else A input is (0000)BCD. The following Boolean expression is used to find
whether (0110)BCD or (0000)BCD needs to be applied to the A input,
C out = Cout1 + S4 (S3*S2)
Where S4, S3, S2, S1 are the sum of the BCD from the first binary adder with S4 as the
MSB and S1 as the LSB. Cout1 is the carry output from the first binary adder.
PROCEDURE:
1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Apply and verify the various combination of input according to the truth table for
BCD adder.
RESULT:


Deld (Ar20) Wov

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Digital Electronics & Logic Design Lab B.

Tech III semester

ADITYA ENGINEERING COLLEGE(A)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DIGITAL ELECTRONICS AND LOGIC DESIGN LABORATORY

B.Tech –III SEMESTER Regulation: AR20

1. Functional verification of logic gates.

2. Develop basic logic gates using universal gates.

4.Design a logic circuit for a given Boolean expression.

5.Design Full adder circuit and verify its truth table.

6. Design a combinational logic circuit for 8 to 1MUX.

8.Verify the truth tables of Basic Flip-flops.

9. Design a synchronous decade counter.

11. Design BCD to Seven Segment Display Decoder.

Dept. of ECE, Aditya Engineering College(A) 1

Dept. of ECE, Aditya Engineering College(A) 2

VERIFICATION OF LOGIC GATES

Dept. of ECE, Aditya Engineering College(A) 3

INPUTS OUTPUT VERIFIED

INPUTS OUTPUT VERIFIED

Dept. of ECE, Aditya Engineering College(A) 4

Dept. of ECE, Aditya Engineering College(A) 5

Exp No:1 Date:

VERIFICATION OF LOGIC GATES

S.NO EQUIPMENT /COMPONENT NAME QUANTITY

1. Component development system (bread board trainer) 1

9. Patch chords & Connecting Wires As per Required

Dept. of ECE, Aditya Engineering College(A) 6

INPUTS OUTPUT VERIFIED

INPUTS OUTPUT VERIFIED

Dept. of ECE, Aditya Engineering College(A) 7

Dept. of ECE, Aditya Engineering College(A) 8

Dept. of ECE, Aditya Engineering College(A) 9

INPUTS OUTPUT VERIFIED

Dept. of ECE, Aditya Engineering College(A) 10

Dept. of ECE, Aditya Engineering College(A) 11

Dept. of ECE, Aditya Engineering College(A) 12

Dept. of ECE, Aditya Engineering College(A) 13

Dept. of ECE, Aditya Engineering College(A) 14

DEVELOP BASIC LOGIC GATES USING UNIVERSAL GATES

Dept. of ECE, Aditya Engineering College(A) 15

INPUTS OUTPUT VERIFIED

2- input OR gate using NAND gate: OR gate Truth Table

INPUTS OUTPUT VERIFIED

Dept. of ECE, Aditya Engineering College(A) 16

Exp No: 2 Date:

DEVELOP BASIC LOGIC GATES USING UNIVERSAL GATES

S.NO EQUIPMENT /COMPONENT NAME QUANTITY

1. Component development system (bread board trainer) 1

4. Patch chords & Connecting Wires As per Required

Dept. of ECE, Aditya Engineering College(A) 17

NOT gate using NAND gate: Truth Table:

INPUTS OUTPUT VERIFIED

NOT gate realization using NAND gate :

Fig: Realization of basic gates using NAND gate

2 input AND gate using NOR gates Truth Table

INPUTS OUTPUT VERIFIED

Dept. of ECE, Aditya Engineering College(A) 18

Commonly available neither Digital Logic NOR Gate IC does include:

Dept. of ECE, Aditya Engineering College(A) 19

2 input OR gate using NOR gates OR gate Truth Table

INPUTS OUTPUT VERIFIED