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Removal of flux residues from highly dense assemblies

Conference Paper  in  Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium · November 2012
DOI: 10.1109/IEMT.2012.6521836

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 REMOVAL OF FLUX RESIDUES FROM HIGHLY DENSE ASSEMBLIES
Mike Bixenman
Chief Technology Officer
mikeb@kyzen.com
Jason Chan
Technical Applications Manager – Asia
jason_chan@kyzen.com
T.C. Loy
Technical Sales Manager
tc_loy@kyzen.com

Abstract Highly Dense Packages (BTCs)

Quality and reliability is a function of the manufacturing
design that achieves repeatability and reproducibility.
Designing advanced packages and assemblies is more difficult
due to lead-free wetting and higher process temperature
requirements. The associated manufacturing changes along
with component miniaturization and board density increases
complexity.
From a cleaning perspective, many designers have poor
insight into factors that assure a cleanable design. Solder paste
selection, reflow conditions, component placement,
component clearance (standoff), cleaning agent and cleaning
equipment are important factors. Collaboration between
process engineers, assembly designers, solder materials,
cleaning agent and cleaning equipment experts can improve
integration of the circuit design and assembly.
Innovation of surface mount technology and advanced
packaging are driven by market pressures. Smart phones,
tablet PCs, digital cameras, notebooks are fast-growing
markets with demand for smaller, thinner and lighter designs.
Thus, electronic products trend toward miniaturization with
more functionality, increased memory, fast cycle times, cost
reduction and improved quality. With all these requirements,
more components need to be placed on finer and compact
platforms as compared to conventional PCB assemblies.
Components designers and OEMs are designing and
packaging electronic devices using smaller form factors,
through-silicon vias (TSV), high density interconnects (HDI)
and embedded technology. These technologies allow for
shrinking die size and create more functionality in a single
component such as BGAs, QFNs, CSPs and Flip Chips.

Package design plays an important role when cleaning is
required. Density of components, component layout, thermal
heat requirements, and standoff height/clearance are key
considerations. From a cleanability perspective, package on
package, flip chip, bottom termination component (BTC)
selection, solder mask definition, placement and layout
influence the clearance gaps. The purpose of this research is to
use a BTC test vehicle for studying factors related to the
cleaning process. The designed experiment will present
findings for removing flux residues under bottom termination
components.
The general definition of HDI is a printed circuit board with
higher wiring density per unit area than conventional printed
circuit board designs. High density interconnects have finer
lines and spaces (≦100μm), smaller vias (<150μm) and
capture pads (<400μm), and higher connection pad density
(>20 pads/cm2) than employed in conventional PCB
technology (Figure1).

©Kyzen Corporation Page 1

 
 During the electronic assembly process, flux residues are left
behind post soldering under/around components on the PCB.
The nature of flux residue affects reliability. The ionic
property of flux residue will lead to electrochemical migration
when the device is exposed to a humid environment (mono-
layers of moisture) and biased (plating of metal deposits due
to the Coulomb effects applied an electric field). Positive
metal ions are formed at anode and migrate toward to cathode.
Overtime, these ions accumulate as metallic dendrites,
reducing the spacing between electrodes, and eventually
creating a metal bridge (Figure 3).

Figure 1: HDI PCB

The significant benefit and advantage of high density

interconnects is the possibility of applying advanced
component packaging (high I/O, fine-pitch features) on highly
dense and thinner (less layers) print circuit board to achieve
cost reduction and miniaturization. These design features
improve electrical performance and signal integrity through
the use of blind and buried microvia designs (Figure 2).
Conductor routing takes place from the internal layers under
vias to create more usable space. Benefits include shorter
circuit paths, lower cross talk and noise. Others advantages are
thermal reliability and ground connections. Figure 3: Electrochemical Migration Failure Mechanism

Larger pitch devices (Figure 4) exhibit a lower failure rate due

to a comparably lower electric field [Electric Field (E) =
voltage (v) / distance (d)]. Smaller pitch devices (Figure 5)
exhibit higher electrical field (less distance between
conductors) resulting in lower voltage tolerances. The electric
field rises inversely with conductor spacing, which increases
electrical, mechanical and thermal modes of failure. Rates of
failure are driven by a combination of temperature, voltage,
current and frequency.

Figure 2: HDI structure

Why Cleaning is Needed

Nowadays, all industries design and apply high technology

electronic devices to achieve the jobs that customers need to
accomplish. For some industries such as military, aerospace,
medical and automotive, the jobs that need to be done require
electronic devices that perform on demand under various
environment conditions. As a result, reliability of electronic
devices has become more important and should be called out
by industry standards or specified by end customers.

©Kyzen Corporation Page 2

 
 Figure 4: Higher Pitch Devices
Figure 5: Smaller Pitch Devices
The electric field is proportional to the force applied on a
metallic ion. Electrical forces applied to a charged particle
affects the time it takes for the metallic ion to move through
an electrolytic solution. Bumiller, Pecht and Hillman’s
research found a strong correlation between dendrite
formation and the electric field.1 Dendritic growth was found
on boards with contamination as low as 0 μg/in2 Cl levels on
boards with less than 2 mil spacing. At contamination levels of
0-2 μg/in2 Cl, dendritic growth was found on 6.25 mil comb
spacing, with infrequent appearances on 12.5 mil spacing, and
no occurrence on 25 mil spacing. At 5-20 μg/in2 Cl, dendritic
growth was found on both 6.25 and 12.5 mil spacing, with
infrequent occurrences on 20 mil spacing. The research found
a strong correlation between contamination levels and the
distance between conductors. Figure 6 illustrates this point
from research conducted by Minizari et al. research conducted
on electrochemical migration within chloride environments.2
©Kyzen Corporation Page 3
Figure 6: Dendritic Growth as a Function of Contamination
Highly dense circuits have a number of reliability risks that
must be considered. Higher current densities, lower voltage
tolerances and higher electric fields are common place with
these circuit designs. On highly dense interconnects,
cleanliness is an important consideration even when the
residues are deemed “no-clean.” The problem is that cleaning
highly dense assemblies is very difficult. Improving on current
test methods that help assemblers validate good design
parameters, and to confirm that levels of cleanliness are
sufficient, is increasingly important.
Soil Considerations
Generally, three flux families are used for electronics
soldering process including no-clean, water soluble (organic
acid or OA) and RMA. No-clean flux residues are of risk due
to weak organic acid that is difficult to fully activate under the
Z-axis and may exceed limitation of contamination level
(>150μg/in2). In addition, no-clean flux residue is typically
difficult to fully remove which may result in partial cleaning.
The residue exposes the theory of encapsulation while leaving
behind ionic contamination. Water soluble flux residues
always leave high levels of ionic material behind and therefore
create high potential of dendrite growth.
Miniaturization and lead-free soldering process have driven
multiple changes to soldering processes and soldering
materials. The elevated soldering temperature and changing
flux compositions result in harder to clean residues.
Overheating during soldering can result in flux burn out,
polymerization and charring. To improve wetting, flux
compositions are formulated with higher molecular oxygen
barriers and enhanced flux capacity. The residues exhibit
improved thermal resistance, wetting and solderability.
One limitation of these higher molecular weight flux residues
is the increased time needed to dissolve the residue during
cleaning (Figure 7).3 Additionally, the spacing from the board
to the bottom of the component is less than 2 mils on many
bottom termination components. To overcome these cleaning
difficulties, solder mask strategies can improve cleaning by
reducing capillary effects and increasing gap heights.
 Figure 7: Soil Properties

Solder Mask Strategies that Improve Cleaning

To clean under component gaps with tight pitches and reduced

standoffs, board design along with chemical and mechanical
effects must be optimized. Past research data findings infer
that longer wash exposure time and deflective energy are
needed to penetrate the gap, break the flux dam, create a flow
channel and ultimately remove all flux residues. The success
of cleaning under bottom termination components requires a
design for cleaning mentality.
Solder mask definition influences where the flux residue flows
away from the component pad during solder reflow and the
potential for under filling the underside of the component.
Using design for cleaning forethought, three strategies can be
applied: (1.) Solder Mask Defined, (2.) Non Solder Mask
Defined and (3.) No Solder Mask.
Plexus and Kyzen Corporation collaborated on the design of a
Test Vehicle to study cleaning effects under Bottom
Termination Components (Figure 8).4 The test vehicle is
designed to study solder mask definition strategies. Solder
mask defined pads (SMD) place a layer to solder mask over
the metal pad. No solder mask defined pads (NSMD) remove
2-8 mils of solder mask adjacent the metal pad. No solder
mask (NoSM) remove all solder mask under and between
terminations.
Figure 8: Plexus – Kyzen Clean Test Vehicle
The first strategy is to define the solder pads with solder mask
(Figure 9).5 Research into this topic finds the flux residues
flowing away from the pad during reflow. Solder mask on the
outer layer of the termination pad reduces gap height on
leadless devices. During soldering, capillary forces under the
component create forces for underfilling chip caps and
leadless bottom termination components with flux residue. An
analogy to this effect occurs when soldering two copper
fittings together. As flux is activated, the clean metal pads
draw the flux under the component. On gaps of less than 3
mils, the capillary effects of the flux residues underfill the
device and block all flow channels. This tendency to bridge
conductors creates a highly difficult cleaning challenge that
requires increased wash time and impingement pressure.

©Kyzen Corporation Page 4

 
 Figure 9: Solder Mask Defined Pads
No solder mask defined (NSMD) pads (Figure 10) creates a
trough around the component pad. During reflow, the trough
breaks the vacuum effect. Flux residues have a tendency to fill
the trough and reside next to the pad. As such, the flux residue
has a lessor tendency to flow away from the component. There
are instances where the flux residue will underfill the
component, but in many cases the flux residue will accumulate
into the troughs, which leaves a non-dammed gap under the
component. This provides less time to clean under the
component.
©Kyzen Corporation Page 5
Figure 10: Non Solder Mask Defined Pads
No solder mask (NoSM) under the component can also
improve cleaning since this design strategy breaks the vacuum
and increases the gap height under the component (Figure 11).
In contrast to solder mask defined pads, the flux residue has a
greater tendency to accumulate next to the pads and not
underfill the bottom side of the component. The benefit of this
design strategy is the increased standoff gap, which allows the
cleaning material to wet and penetrate the gap at reduce time.
The increased gap height improves the potential to penetrate
the component gap and reduces time to clean.
 Figure 12: Chip Cap Cleaning Data

For QFN and other leadless devices, removal of the solder

mask around terminations and under the component improves
cleaning. QFN’s are one of the most difficult to clean
components due to the low Z-axis and ground pad in the
center of the component (Figure 13). On QFNs printed over
solder mask defined pads, the gap height is between 1-2 mils.
To properly clean QFN’s, high pressure sprays and long wash
time is needed. The data finds that No Solder Mask defined
pads improve the cleaning process window by increasing the
Z-Axis (Figure 14).

Figure 13: MLF/QFN Components

Figure 11: No Solder Mask Defined Pads

Data Findings

The data finds that the use of No Solder Mask Defined pads is
the best strategy for cleaning chip capacitors/resistors (Figure
12). Removal of the solder mask reduces capillary forces that
create a vacuum under the component. This vacuum effect
leads to flux residue underfilling the bottom side of the
component. Removal of the solder mask increases the Z-Axis Figure 14: QFN Cleaning Data
standoff by 1-2 mils, which improves cleaning.
A much different cleaning dynamic is seen when cleaning Ball
Grid Array components. On BGA devices, the Z-Axis is in the
range of 5-15 mils. On Solder Mask Defined and Non Solder
©Kyzen Corporation Page 6
 
Mask Defined pads, the flux residue tends to accumulate next components to the end package. Most of these residues are
to the interconnection. Due to the gap height, the residue does soluble in water or water plus an aqueous additive.
not form this vacuum effect. An opposite effect occurs when
using No Solder Mask under the component. The flux residue
tends to run away from the component in a thin layer, which
increases the risk of flux burn out. The data finds that solder
mask defined pads represent best practice on ball grid array
components (Figure 15).

Figure 17: Flip Chip @ 150x with 43μm Gap Height

Best practice cleaning strategies implement water plus

aqueous additives that reduce surface tension, control foaming
effects, and increase cleaning rates. Devices are placed into
fixtures and cleaned with high spray-in-air cleaning tools. The
sprays are targeted at the leading edge of the die (Figure 18).

Figure 15: Ball Grid Array Cleaning Data

Component Cleaning Strategies

Flip chip packages use a no-solder mask design strategy

(Figure 16). Interconnects are soldered during the back end
wafer bumping process. Negative photoresist is commonly
used to define bumping sites. Once the wafer is bumped,
photoresist is removed. The solder spheres are reflowed to
achieve interconnect symmetry. Flux residue is removed and
wafer is diced into chip scale components. Figure 18: Spray Targeted at the Z-Axis

On leadless devices (Figure 19) such as QFNs, removal of the

solder mask under the component allows the cleaning agent to
penetrate and remove the soil at a faster rate (Figure 20). The
cleaning agent must be matched up to the flux residue. Poorly
matched cleaning agents will not be effective even when
delivered with high pressure. Spray-in-air coherent jets
improve cleaning due to the defective energy needed to deliver
the cleaning agent under the component.

Figure 16: Flip Chip No Solder Mask Defined Strategy

The gap height on flip chip, chip scale, wafer level and
package on package devices is a function of the ball pitch.
Tighter ball pitch results in lower gap heights. The image in
Figure 17 is magnified at 150x with a standoff gap of 43μm
(1.5 mils). Due to the large surface area and low gap heights,
many assemblers use easy to clean flux pastes to join these Figure 19: Leadless Devices Example

©Kyzen Corporation Page 7

 

Figure 20: Removal of Solder Mask under QFN
Chip cap resistors continue to miniaturize. The narrow
distances between conductors in combination with the low Z-
axis creates a vacuum effect under the chip cap during reflow.
Flux residues tend to underfill the component while blocking
flow channels. These effects create a difficult cleaning
challenge. Removal of the solder mask from under the
component reduces the vacuum effect and renders less residue
under the chip cap during reflow (Figure 21). The high
standoff gap reduces the time to clean and opens the cleaning
process window.
Figure 21: Chip Cap Resistor Example
Ball Grid arrays are much easier to clean over leadless devices
due to the ball size and standoff gaps. Flux residues tend to
accumulate next to the ball or column. Unlike leadless chip
caps and QFN devices, removal of solder mask tends to create
a more challenging cleaning process. The data finds that
solder mask defined pads provide an easier to clean condition.
As cleaning fluid flow under the device, the residues sitting on
the solder mask remove cleanly next to the interconnection
(Figure 22).
©Kyzen Corporation Page 8
Figure 22: BGA Before and After Cleaning Example
Concluding Remarks
Smart phones, tablet PCs, digital cameras, notebooks are fast-
growing markets with demand for smaller, thinner and lighter
designs. Electronic products trend toward miniaturization with
more functionality, increased memory, fast cycle times, cost
reduction and improved quality. With all these requirements,
more components need to be placed on finer and compact
platforms as compared to conventional PCB assemblies. The
problem is that research data finds that cleanliness becomes
more critical as distance between conductors narrows.
To clean under component gaps with tight pitches and
reduced standoffs, board design along with chemical and
mechanical effects must be optimized. Solder mask
definition influences where the flux residue flows away from
the component pad during solder reflow and the potential for
under filling the underside of the component.
The data finds that the use of No Solder Mask Defined pads is
the best strategy for cleaning chip capacitors/resistors.
Removal of the solder mask reduces capillary forces that
create a vacuum under the component. This vacuum effect
leads to flux residue underfilling the bottom side of the
component. Removal of the solder mask increases the Z-Axis
standoff by 1-2 mils, which improves cleaning.
For QFN and other leadless devices, removal of the solder
mask around terminations and under the component improves
cleaning. QFN’s are one of the most difficult to clean
components due to the low Z-axis and ground pad in the
center of the component. The data finds that No Solder Mask
defined pads improve the cleaning process window by
increasing the Z-Axis.
On BGA devices, the Z-Axis is in the range of 5-15 mils. On
Solder Mask Defined and Non Solder Mask Defined pads, the
flux residue tends to accumulate next to the interconnection.
The data finds that solder mask defined pads represent best
practice on ball grid array components.
References

1. Bumiller, E., Pecht, M., & Hillman, C. (n.d.)

Electrochemical Migration on HASL Plated FR-4
Printed Circuit Boards. Retrieved from
http://www.dfrsolutions.com/uploads/publications/
2004_ECM_Hillman‐Bumiller.pdf
2. Minzari, D., Jellesen, M.S., Moller, P., Wahlberg, P.,
& Ambat, R. (2009, September). Electrochemical
Migration on Electronic Chip Resistors in Chloride
Environments. IEEE Transactions on Device and
Materials Reliability. 9 (3), 392-402.
3. Stach, S. Bixenman, M. (2004) “Optimizing Cleaning
Energy in Batch and Inline Spray Systems” SMTAI,
Rosemont, IL
4. Lee, D. et al. (2011). Cleaning Test Card Designs.
Meptec/SMTA Medical Conference. Tempe, AZ.
5. Stach, S. & Bixenman, M. (2012). High Speed
Cleaning in a Reduced Manufacturing Footprint.
SMTAI, Orlando, FL

©Kyzen Corporation Page 9

 

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