Batch1

SRM Institute of Science and Technology Mode of Exam

College of Engineering and Technology ONLINE
School of Computing
Common to Computing Technologies/Networking and Communication/Computational
Intelligence/Data science and Business systems
SRM Nagar, Kattankulathur – 603203, Chengalpattu District, Tamilnadu
Academic Year: 2021-22 (ODD)

Test: CLAT-3 Date: 31/01/2022

Course Code & Title: 18CSS201J – Analog and Digital Electronics Duration: 100 Mins
Year & Sem: II & III Max. Marks: 50

Course Articulation Matrix:

Course
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
Outcomes
CO1 H H
CO2 H H
CO3 H H H
CO4 H H H H H H
CO5 H H H H
CO6 H H H H

Part - A
(30 x 1 Marks = 30 Marks)
Instructions: Answer all the questions
Q. Question Mar PI
BL CO PO
No ks Code
1 In a JK Flip-Flop, toggle means
(A) Set Q = 1 and Q’ = 0.
(B) Set Q = 0 and Q’ = 1.
1 1 4 1 1.6.1
(C) Change the output to the opposite state.
(D) No change in output.
ANS: C
2 The output of SR flip flop when S=1, R=0 is
(A) 1 (B) 0
1 1 4 1 1.6.1
(C) No change (D) High impedance
ANS: A
3 For JK flipflop J = 0, K=1, the output after clock pulse will be
(A) 1. (B) no change.
1 2 4 2 1.6.1
(C) 0. (D) high impedance.
ANS: C
4 The basic storage element in a digital system is
(A) flipflop
(B) counter
1 2 4 1 1.6.1
(C) multiplexer
(D) encoder
ANS: A
5 The truth table for an S-R flip-flop has how many VALID
entries? 1 1 4 1 1.6.1
(A) 1
 (B) 2
(C) 3
(D) 4
ANS: C
6 A basic S-R flip-flop can be constructed by cross-coupling of
which basic logic gates?
(A) AND or OR gates
(B) XOR or XNOR gates 1 1 4 1 1.6.1
(C) NOR or NAND gates
(D) AND or NOR gates
ANS: C
7 The logic circuits whose outputs at any instant of time depends
only on the present input but also on the past outputs are called
(A) Combinational circuits
(B) Sequential circuits 1 1 4 1 1.6.1
(C) Latches
(D) Flip-flops
ANS: B
8 S-R type flip-flop can be converted into D type flip-flop if S is
connected to R through
(A) OR Gate
(B) AND Gate 1 2 4 1 1.6.1
(C) Inverter
(D) Full Adder
ANS: C
9 What is one disadvantage of an S-R flip-flop?
(A) It has no Enable input
(B) It has a RACE condition
1 1 4 1 1.6.1
(C) It has no clock input
(D) Invalid State
ANS: D
10 A J-K flip-flop can be obtained from the clocked S-R flip-flop by
augmenting
(A) Two AND gates
(B) Two NAND gates 1 1 4 1 1.6.1
(C) Two NOT gates
(D) Two OR gates
ANS: A
11 In J-K flip-flop, “no change” condition appears when
(A) J = 1, K = 1
(B) J = 1, K = 0
1 1 4 2 1.6.1
(C) J = 0, K = 1
(D) J = 0, K = 0
ANS: D
12 In D flip-flop, if clock input is LOW, the D input
(A) Has no effect
(B) Goes high
1 1 4 2 1.6.1
(C) Goes low
(D) Has effect
ANS: A
13 The characteristic equation of J-K flip-flop is
(A) Q(n+1)=JQ(n)+K’Q(n)
(B) Q(n+1)=J’Q(n)+KQ'(n)
1 1 4 1 1.6.1
(C) Q(n+1)=JQ'(n)+KQ(n)
(D) Q(n+1)=JQ'(n)+K’Q(n)
ANS: D
14 In a J-K flip-flop, if J=K the resulting flip-flop is referred to as
(A) D flip-flop
(B) S-R flip-flop
1 2 4 1 1.6.1
(C) T flip-flop
(D) S-K flip-flop
ANS: C
15 The only difference between a combinational circuit and a flip-
flop is that
(A) The flip-flop requires previous state
(B) The flip-flop requires next state 1 2 4 1 1.6.1
(C) The flip-flop requires a clock pulse
(D) The flip-flop depends on the past as well as present states
ANS: C
16 How many flip-flops are required to construct mod 30 counter?
(A) 5 (B) 6 1.6.1
1 3 5 2
(C) 4 (D) 8 2.5.1
ANS: A
17 A device which converts BCD to Seven Segment is called
(A) Encoder
(B) Decoder
1 2 5 1 1.6.1
(C) Multiplexer
(D) Demultiplexer
ANS: B
18 A 4-bit synchronous counter uses flip-flops with propagation
delay times of 45 ns each. The maximum possible time required
for change of state will be 1.6.1
1 3 5 3
(A) 15 ns. (B) 30 ns. 2.5.1
(C) 45 ns. (D) 60 ns.
ANS: C
19 In a positive logic system, logic state 1 corresponds to
(A) positive voltage (B) higher voltage level
1 2 5 2 1.6.1
(C) zero voltage level (D) lower voltage level
ANS: B
20 A weighted resistor digital to analog converter using N bits
requires a total of
(A) N precision resistors. (B) 2N precision resistors. 1 2 5 3 1.6.1
(C) N + 1 precision resistors. (D) N – 1 precision resistors.
ANS: A
21 Two J-K flip-flops with their J-K inputs tied HIGH are cascaded
to be used as counters. After four input clock pulses, the binary
count is
(A) 00 1.6.1
1 3 5 2
(B) 11 2.5.1
(C) 01
(D) 10
ANS: A
22 The preferred type of flip flop for designing a binary counter is
-----
(A) D type
(B) S-R type 1 2 5 3 1.6.1
(C) Latch
(D) J-K type
ANS: D
23 The term synchronous means ____________
(A) The output changes state only when any of the input is
triggered
(B) The output changes state only when all the clock input is
1 2 5 2 1.6.1
triggered at the same instant
(C) The output changes state only when the input is reversed
(D) The output changes state only when the input follows it
ANS: B
24 For a 4-bit universal shift register, the selection lines S0S1 = 10
represents _____ operation
(A) Locked state (No change)
(B) Shift-Left 1 2 5 1 1.6.1
(C) Shift-Right
(D) Parallel Loading
ANS: C
25 The propagation delay in synchronous counter is much lesser
than that of asynchronous counter due to ……………….
(A) clocking of all flip flops at the same instant
(B) increase in number of states
1 2 5 2 1.6.1
(C) absence of connection between output of preceding flip flop
and clock of next one
(D) absence of mode control operation
ANS: A
26 The terminal count of a typical modulus-10 binary counter is
(A) 0000
(B) 1010
1 3 5 2 1.6.1
(C) 1001
(D) 1111
ANS: C
27 A Seven-segment, common-anode LED display is designed for
(A) All cathodes to be wired together
(B) One common LED
1 2 5 2 1.6.1
(C) A high signal to turn off each segment
(D) Disorientation of segment module
ANS: C
28 The flash type ADC each comparator output is connected to an
input of
(A) priority encoder
(B) multiplexer 1 1 5 1 1.6.1
(C) demultiplexer
(D) decoder
ANS: A
29 Analog to digital conversion includes
(A) quantization
(B) simulation
1 2 5 1 1.6.1
(C) Data accumulation
(D) summation
ANS: A
30 A 4-bit counter has a maximum modulus of ____________
(A) 3
(B) 6 1.6.1
1 3 5 2
(C) 8 2.5.1
(D) 16
ANS: D
Part – B
(10 x 2 Marks = 20 Marks)
Instructions: Answer all the questions
31 For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 &
present state is 0 then the excitation input will be
(A) J=1, K=1
(B) J=X, K=1 2 1 4 2 1.6.1
(C) J=1, K=X
(D) J=0, K=0
ANS: C
32 The sequence detected by the state diagram shown below is

1.6.1
2 2 4 3
2.5.1

(A) 1110 sequence detector without overlap

(B) 1100 sequence detector with overlap
(C) 1101 sequence detector without overlap
(D) 1101 sequence detector with overlap
ANS: C
33 Which statement describes the BEST operation of a negative-
edge-triggered D flipflop?
(A) The logic level at the D input is transferred to Q on NGT of
CLK
(B) The Q output is ALWAYS identical to the CLK input if the
2 2 4 2 1.6.1
D input is HIGH
(C) The Q output is ALWAYS identical to the D input when
CLK = PGT
(D) The Q output is ALWAYS identical to the D input
ANS: A
34 The state table of a synchronous circuit is given. As a part
of the logic circuit design with D flip flops, the input to flip
flop B is given as
Present state Next state
A B C A+ B+ C+
0 0 0 1 1 1
1 1 0 1 0 0
0 1 1 1 1 0 1.6.1
2 3 4 3
1 0 0 0 1 1 2.5.1
1 1 1 0 0 0

(A) DB = A+C’
(B) DB = C’
(C) DB = A’+B’
(D) DB = C+B’
ANS: C
35 In JK flip flop same input, i.e. at a particular time or during a
clock pulse, the output will oscillate back and forth between 0
and 1. At the end of the clock pulse the value of output Q is
2 2 4 2 1.6.1
uncertain. The situation is referred to as?
(A) Conversion condition
(B) Race around condition
 (C) Lock out state
(D) Forbidden State
ANS: B
36 The resolution of an n bit DAC with a maximum input of 5 V
is 5 mV. The value of n is …….
1.6.1
(A) 8 (B) 9 2 3 5 3
2.5.1
(C) 10 (D) 11
ANS: C
37 A decade counter skips ………..
(A) binary states 1000 to 1111
(B) binary states 0000 to 0011
2 2 5 2 1.6.1
(C) binary states 1010 to 1111
(D) binary states 1111 to higher
ANS: C
38 What output voltage would be produced by a D/A converter
whose output range is 0 to 10 V and whose binary number is
0101 (for a 4-bit DAC)
(A) 3.75 V 1.6.1
2 3 5 3
(B) 3.125 V 2.5.1
(C) 8.125 V
(D) 6.25 V
ANS: B
39 The desirable count for a presettable counter is loaded when
(A) preset = 1 and clear =1
(B) preset = 1 and clear =0
2 2 5 2 1.6.1
(C) preset = 0 and clear =1
(D) preset = 0 and clear =0
ANS: B & C
40 BCD input 1000 is fed to a 7-segment display through a BCD to
7 segment decoder/driver. The segments which will lit up are
(A) a,b,d
(B) a,,b,c 2 3 5 2 1.6.1
(C) a,b,g,c,d
(D) a,,b,c,d,e,f,g
ANS: D

Course Outcome (CO) and Bloom’s level (BL) Coverage in Questions

Approved by the Audit Professor/Course Coordinator