BCS-29

Advanced Computer Architecture

Input Output Techniques
Input/Output Problems
• Wide variety of peripherals
• Delivering different amounts of data
• At different speeds
• In different formats
• All slower than CPU and RAM
• Need I/O modules w/ some “intelligence”
Accessing I/O Devices

• Computer system components communicate through

an interconnection network
• How to address the I/O devices? Memory-mapped I/O
allows I/O registers to be accessed as memory
locations. As a result, these registers can be accessed
using only Load and Store instructions
I/O Device Interface
• An I/O device interface is a circuit between
a device and the interconnection network
• Provides the means for data transfer and
exchange of status and control information
• Includes data, status, and control registers
accessible with Load and Store instructions
• Memory-mapped I/O enables software to view these
registers as locations in memory
Generic Model of I/O Module
Input/Output Module
• Interface to CPU and Memory
• Interface to one or more peripherals
External Devices
• Human readable (human interface)
• Monitor, printer, keyboard, mouse
• Machine readable
• Disk, tape, sensors
• Communication
• Modem
• Network Interface Card (NIC)
External Device Block Diagram
I/O Module Function
• Control & Timing
• CPU (Processor) Communication
• Device Communication
• Data Buffering
• Error Detection (e.g., extra parity bit)
I/O Steps
• CPU checks (interrogates) I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer by sending a
command to the I/O module
• I/O module gets a unit of data (byte, word, etc.) from
device
• I/O module transfers data to CPU
• Variations of these steps for output, DMA, etc.
Processor/device Communications
• Command decoding
• Data
• Status reporting
• Address recognition
 I/O Module Diagram

Systems Bus Interface External Device Interface

External Data
Data Data Register Device
Lines Status
Interface
Status/Control Register
Logic Control

Address
Lines Input External Data
Output Device
Data Logic Status
Interface
Lines
Logic Control
14
I/O Module Decisions
• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for CPU
• Also O/S decisions
• e.g. Unix treats everything it can as a file
Input Output Techniques
• Programmed
• Interrupt driven
• Direct Memory Access (DMA)
Programmed I/O
• CPU has direct control over I/O
• Sensing status
• Read/write commands
• Transferring data
• CPU waits for I/O module to complete operation
• Wastes CPU time
Programmed I/O - detail
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
Program-Controlled I/O
• Discuss I/O issues using keyboard & display
• Read keyboard characters, store in memory, and
display on screen
• Implement this task with a program that performs all
of the relevant functions
• This approach called program-controlled I/O
• How can we ensure correct timing of actions
and synchronized transfers between devices?
Signaling Protocol for I/O Devices
• Assume that the I/O devices have a way to send a
‘READY’ signal to the processor
• For keyboard, it indicates that the character is ready
to be read.
• For display, it indicates the display is ready to receive
the character.
• The ‘READY’ signal in each case is a status flag
in status register that is polled by processor
I/O Commands
• CPU issues address
• Identifies module (& device if >1 per module)
• CPU issues command
• Control - telling module what to do
• e.g. spin up disk
• Test - check status
• e.g. power? Error?
• Read/Write
• Module transfers data via buffer from/to device
Addressing I/O Devices

• Under programmed I/O data transfer is very like memory

access (CPU viewpoint)
• Each device given unique identifier
• CPU commands contain identifier (address)
I/O Mapping
• Memory mapped I/O
• Devices and memory share an address space
• I/O looks just like memory read/write
• No special commands for I/O
• Large selection of memory access commands available
• Isolated I/O
• Separate address spaces
• Need I/O or memory select lines
• Special commands for I/O
• Limited set
Interrupt Driven I/O
• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready
Interrupts

• Drawback of a programmed I/O: BUSY-WAIT LOOP

• Due to the time needed to poll if I/O device is ready, the
processor cannot often perform useful computation
• Instead of using a BUSY-WAIT LOOP, let I/O device alert
the processor when it is ready
• Hardware sends an interrupt-request signal
to the processor at the appropriate time, much like a
phone call.
• Meanwhile, processor performs useful tasks
Example of Using Interrupts
• Consider a task with extensive computation and
periodic display of current results
• Timer circuit can be used for desired interval, with
interrupt-request signal to processor
• Two software routines: COMPUTE & DISPLAY
• Processor suspends COMPUTE execution to execute
DISPLAY on interrupt, then returns
• DISPLAY is short; time is mostly in COMPUTE
Interrupt Driven I/O
Basic Operation
• CPU issues read command
• I/O module gets data from peripheral whilst CPU
does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
CPU Viewpoint
• Issue read command
• Do other work
• Check for interrupt at end of each instruction cycle
• If interrupted:-
• Save context (registers)
• Process interrupt
• Fetch data & store
• See Operating Systems notes
Design Issues
• How do you identify the module issuing the
interrupt?
• How do you deal with multiple interrupts?
• i.e. an interrupt handler being interrupted
Identifying Interrupting Module (1)
• Different line for each module
• PC
• Limits number of devices
• Software poll
• CPU asks each module in turn
• Slow
Identifying Interrupting Module (2)
• Daisy Chain or Hardware poll
• Interrupt Acknowledge sent down a chain
• Module responsible places vector on bus
• CPU uses vector to identify handler routine
• Bus Master
• Module must claim the bus before it can raise interrupt
• e.g. PCI & SCSI
Multiple Interrupts
• Each interrupt line has a priority
• Higher priority lines can interrupt lower priority lines
• If bus mastering only current master can interrupt
Example - PC Bus
• 80x86 has one interrupt line
• 8086 based systems use one 8259A interrupt
controller
• 8259A has 8 interrupt lines
Sequence of Events
• 8259A accepts interrupts
• 8259A determines priority
• 8259A signals 8086 (raises INTR line)
• CPU Acknowledges
• 8259A puts correct vector on data bus
• CPU processes interrupt
ISA Bus Interrupt System
• ISA bus chains two 8259As together
• Link is via interrupt 2
• Gives 15 lines
• 16 lines less one for link
• IRQ 9 is used to re-route anything trying to use IRQ 2
• Backwards compatibility
• Incorporated in chip set
82C59A Interrupt
Controller
Intel 82C55A
Programmable Peripheral Interface
Using 82C55A To Control
Keyboard/Display
8086 External Interrupt Connections
NMI - Non-Maskable Interrupt INTR - Interrupt Request

Programmable
NMI Requesting Interrupt Controller
Device (part of chipset)

NMI
8086 CPU
Intel
INTR
Interrupt Logic 8259A
PIC
Divide Single
int into
Error Step

Software Traps
Interrupt Vector Table – IVT (in memory)

• x86 has 256 interrupts, specified by Type Number or Vector

• 1 byte of data must accompany each interrupt; specifies Type

• Vector is a pointer (address) into Interrupt Vector Table, IVT

• IVT is stored in memory from 0000:0000 to 0000:03ffh

• IVT contains 256 far pointer values (addresses)

• Far pointer is CS:IP values

• Each far pointer is address of Interrupt Service Routine, ISR

• Also referred to as Interrupt Handler
When interrupt is requested, which IVT entry? Type!
IVT Format
0000:0000
0000:0001
Offset
0000:0002
Interrupt 0 IP LSB

0000:0003
Segment IP MSB

0000:0004 CS LSB

0000:0005
Offset CS MSB
Interrupt 1
0000:0006
0000:0007
Segment

Given a Vector, where is the

ISR address stored in memory ?

Offset = Type  4
0000:03fc
0000:03fd
Offset Example: int 36h
0000:03fe
Interrupt 255
0000:03ff
Segment Offset = (544) = 216
= 00d8h
Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-41
What Happens During an
Interrupt ?
Complete push
Current Flags
Instruction

Internal
YES Set
TEMP=TF
TF=TEMP
Interrupt

NO

YES IF=0 pop

NMI TF=0 IP and CS
NO

YES 1
push
INTR IF popf
CS and IP
0
NO

1 acknowledge call Resume

TF Interrupted
interrupt ISR Procedure
0

Fetch Read Type

YES
Next Code # NMI
Instruction
Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-42
NO
Similarity to Subroutine
Procedure
• call  int

• ret  iret
• call pushes CS, IP and loads CS:IP with address of subroutine

• int does what call does and more

• ret pops IP, CS

• iret pops FLAGS, IP, and CS

• This is why ALL programs MUST have a stack segment, so that interrupts
can be handled

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-43

Interrupt Vector Assignments
Type Function Comment
0 Divide Error Processor - zero or overflow
1 Single Step (DEBUG) Processor - TF=1
2 Nonmaskable Interrupt Pin Processor - NMI Signal
3 Breakpoint Processor - Similar to Sing Step
4 Arithmetic Overflow Processor - into
5 Print Screen Key BIOS - Key Depressed
6 Invalid Opcode Processor - Invalid Opcode
7 Coprocessor Not Present Processor - no FPU
8 Time Signal BIOS - From RT Chip (AT - IRQ0)
9 Keyboard Service BIOS - Gen Service (AT - IRQ1)
A-F Originally Bus Ops (IBM PC) BIOS - (AT - IRQ2-7)
10 Video Service Request BIOS - Accesses Video Driver
11 Equipment Check BIOS - Diagnostic
12 Memory Size BIOS - DOS Memory
13 Disk Service Request BIOS - Accesses Disk Driver
14 Serial Port Service Request BIOS - Accesses Serial Port Drvr
15 Miscellaneous BIOS - Cassette, etc.
16 Keyboard Service Request BIOS - Accesses KB Driver

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-44

Interrupt Vector Assignments
Type Function Comment
17 Parallel Port LPT Service BIOS - Printer Driver
18 ROM BASIC BIOS - BASIC Interpreter in ROM
19 Reboot BIOS - Bootstrap
1A Clock Service BIOS - Time of Day from BIOS
1B Control-Break Handler BIOS - Keyboard Break
1C User Timer Service BIOS - Timer Tick
1D Pointer to Video Parm Table BIOS - Video Initialization
1E Pointer to Disk Parm Table BIOS - Disk Subsystem Init.
1F Pointer to Graphics Fonts BIOS - CGA Graphics Fonts
20 Program Terminate DOS - Clear Memory, etc.
21 Function Call DOS - Transfer Control
22 Terminate Address DOS - program Terminate handler
23 Control-C Handler DOS - For OS Use
24 Fatal Error Handler DOS - Critical Error
25 Absolute Disk Read DOS - Disk Read
26 Absolute Disk Write DOS - Disk Write
27 Terminate DOS - TSR Usage
28 Idle Signal DOS - Idle
2F Print Spool DOS - Cassette, etc.
70-77 Hardware Interrupts in AT Bios DOS - (AT - IRQs 8-15)

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-45

AT – IRQ Definitions
IBM-AT (Advanced Technology) - Intel 80286

Name Interrupt Vector Priority Description

NMI 02 1 Memory Parity Error
IRQ0 08 2 Timer (Intel 8253 Chip 55 ms intervals)
IRQ1 09 3 Keyboard
IRQ2 0A 4 8259 PIC Slave or EGA/VGA Vert. Retrace
IRQ3 0B 13 Serial Port (COM2 or COM4)
IRQ4 0C 14 Serial Port (COM1 or COM3)
IRQ5 0D 15 Fixed Disk or LPT2 Request
IRQ6 0E 16 Floppy Disk Driver
IRQ7 0F 17 LPT1 Request
IRQ8 70 5 CMOS Real-Time Clock (RT Chip)
IRQ9 71 6 Re-directed to IRQ2
IRQ10 72 7 RESERVED
IRQ11 73 8 RESERVED
IRQ12 74 9 Mouse or other
IRQ13 75 10 Math Coprocessor (NPX)
IRQ14 76 11 Hard Disk
IRQ15 77 12 RESERVED

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-46

Interrupt Service Routines
• ALL Interrupts
• Interrupts for Input
• Interrupts for Output
Interrupts for Input
• INT 16h / AH = 00h - get keystroke from keyboard
(no echo)
• INT 16h / AH = 01h - check for keystroke in the
keyboard buffer
• INT 21h / AH=1 - read character from standard input,
with echo
• INT 21h / AH=6 - direct console input or output
• INT 21h / AH=7 - character input without echo to AL
• INT 21h / AH=0Ah - input of a string
• INT 21h / AH=0Bh - get input status
Interrupts for Output
• INT 21h / AH=2 - write character to standard output
• INT 21h / AH=9 - output of a string
Direct Memory Access
• Interrupt driven and programmed I/O require active
CPU intervention
• Transfer rate is limited
• CPU is tied up
• DMA is the answer
DMA Application
• DMA is for high-speed data transfer from/to mass storage peripherals,
e.g. harddisk drive, magnetic tape, CD-ROM, and sometimes video
controllers.
• For example, a hard disk may boasts a transfer rate of 5 M bytes per
second, i.e. 1 byte transmission every 200 ns. To make such data transfer
via the CPU is both undesirable and unnecessary.
• The basic idea of DMA is to transfer blocks of data directly between
memory and peripherals. The data don’t go through the microprocessor
but the data bus is occupied.
• “Normal” transfer of one data byte takes up to 29 clock cycles. The DMA
transfer requires only 5 clock cycles.
• Nowadays, DMA can transfer data as fast as 60 M byte per second. The
transfer rate is limited by the speed of memory and peripheral devices.

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-51

Basic DMA concept
• Direct memory access (DMA) is a feature of modern
computer systems that allows certain hardware subsystems to
read/write data to/from memory without microprocessor
intervention, allowing the processor to do other work.
• Used in disk controllers, video/sound cards etc, or between
memory locations.
• Typically, the CPU initiates DMA transfer, does other
operations while the transfer is in progress, and receives an
interrupt from the DMA controller once the operation is
complete.
• Can create cache coherency problems (the data in the cache
may be different from the data in the external memory after
DMA)
Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-52
The 8237 DMA controller
• Supplies memory and I/O with control signals and addresses during DMA
transfer
• 4-channels (expandable)
• 0: DRAM refresh
• 1: Free
• 2: Floppy disk controller
• 3: Free
• 1.6MByte/sec transfer rate
• 64 KByte section of memory address capability with single programming
• “fly-by” controller (data does not pass through the DMA-only memory to I/O
transfer capability)
• Initialization involves writing into each channel:
• i) The address of the first byte of the block of data that must be transferred (called the base
address).
• ii) The number of bytes to be transferred (called the word count).

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-53

DMA Operation
• CPU tells DMA controller:-
• Read/Write
• Device address
• Starting address of memory block for data
• Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished
DMA Transfer & Cycle Stealing
• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
• CPU does not switch context
• CPU suspended just before it accesses bus
• i.e. before an operand or data fetch or a data write
• Slows down CPU but not as much as CPU doing
transfer
Basic process of DMA
In maximum mode:
1. Handshaking Pins: RQ/GT1 and RQ/GT0 → DMA request and acknowledge
Sequences:
2. Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has
higher priority)
3. CPU completes its current bus cycle and enters into a HOLD state
4. CPU grants the right of bus control by asserting a grant signal via the same pin as
the request signal.
5. DMA operation starts
6. Upon completion of the DMA operation, the peripheral asserts the request/grant
pin again to relinquish bus control.

In minimum mode:
The HOLD and HLDA pins are used for handshaking
DMA Controller
• A DMA controller interfaces with several peripherals that may request
DMA.
• The controller decides the priority of simultaneous DMA requests and
communicates with the peripheral and the CPU, and provides memory
addresses for data transfer.
• DMA controller commonly used with 8088 is the 8237 programmable
device.
• The 8237 is in fact a special-purpose processor.
• Normally it appears as part of the system controller chip-sets.
• The 8237 is a 4-channel device. Each channel is dedicated to a specific
peripheral device and capable of addressing 64 K bytes section of memory.
DMA on the 8088 CPU
• The I/O device asserts the appropriate DRQ signal for the channel.
• The DMA controller will enable appropriate channel, and ask the CPU to
release the bus so that the DMA may use the bus. The DMA requests the
bus by asserting the HOLD signal which goes to the CPU.
• The CPU detects the HOLD signal, and will complete executing the current
instruction. Now all of the signals normally generated by the CPU are
placed in a tri-stated condition (neither high or low) and then the CPU
asserts the HLDA signal which tells the DMA controller that it is now in
charge of the bus.
• The CPU may have to wait (hold cycles).
• DMA activates its -MEMR, -MEMW, -IOR, -IOW output signals, and the
address outputs from the DMA are set to the target address, which will be
used to direct the byte that is about to transferred to a specific memory
location.
• The DMA will then let the device that requested the DMA transfer know
that the transfer is commencing by asserting the -DACK signal.
Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-59
DMA on the 8088 CPU
• The peripheral places the byte to be transferred on the bus Data lines.
• Once the data has been transferred, The DMA will de-assert the -DACK2
signal, so that the FDC knows it must stop placing data on the bus.
• The DMA will now check to see if any of the other DMA channels have any
work to do. If none of the channels have their DRQ lines asserted, the
DMA controller has completed its work and will now tri-state the -MEMR,
-MEMW, -IOR, -IOW and address signals.
• Finally, the DMA will de-assert the HOLD signal. The CPU sees this, and de-
asserts the HOLDA signal. Now the CPU resumes control of the buses and
address lines, and it resumes executing instructions and accessing main
memory and the peripherals.

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-60

A 8237 DMA application

Dr P K Singh BCS-29 Advanced Computer Architecture BCS-29(!)-61

DMA Module Diagram
DMA Configurations (1)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
• I/O to DMA then DMA to memory
• CPU is suspended twice
DMA Configurations (2)

• Single Bus, Integrated DMA controller

• Controller may support >1 device
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once
DMA Configurations (3)

• Separate I/O Bus

• Bus supports all DMA enabled devices
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once