EXPERIMENT 3: DESIGN A 3-BIT SYNCHRONOUS COUNTER

1.0 OBJECTIVES

After completing this task, the student should be able to:

● Implement flip-flop in designing counter.

● Design and verify the truth table for a 3-bit synchronous up/down counter.

2.0 THEORY

In a synchronous counter, all the flip-flops are synchronized to the same clock input.
This means that for every clock pulse, all the flip-flops will generate an output. Since
the clocking is done in a parallel manner, synchronous counters are also known as
parallel or simultaneous counters. In this experiment, we will be implementing a JK
flip-flop to make an 8-mod synchronous counter.The only way we can build such a
counter circuit from J-K flip-flops is to connect all the clock inputs together, so that
each and every flip-flop receives the exact same clock pulse at the exact same time.

3.0 METHODOLOGY

A synchronous counter is one whose bits change state at the same time, with

no ripple. In these sorts of counters, the flip flops are clocked at the same time by a
common clock pulse. Hence, all the flip flops change state at the same time (in
parallel). It progress upward in arrangement (0, 1, 2, 3, 4, 5, 6, 7).

EQUIPMENT/MATERIAL REQUIRED

NO. Description Quantity

1 Digital Trainer Kit 1
2 *7408 (AND Gate) 1
3 *7476-JK Flip-Flop 2
4 Wire Cable As per need
 Figure 3.1: 3-bit counter JK Flip Flop

a) b)

Figure 3.2: Pic configuration of 7476(a) and 7408(b)

 Table 3.1: Excitation Table of J-K flip-flop

PROCEDURES

1. Verified all pin configurations whether they are in good condition or not.

2. Construct the circuit as shown in Figure 3.1 on the Digital Trainer Kit.

3. Insert the input data to the circuit via the switches. Check the continuity of each
connection.Switch ON the digital trainer’s power supply.
(Demonstrate the results to the instructor).

4. Determined the number of flip flop, the state diagram of J-K Flip-flop and construct
the excitation table as in Table 3.2.
 Table 3.2: J-K Flip Flop Excitation Table

4. Based on the excitation table, obtained simplified equations using the K-Map.

5. Draw the flip flop logic diagram accordingly.

6. Compared the results with the original theoretical solution as Table

3.3(Demonstrate the results to the instructor). The work from our Digital Trainer Kit
as been included in the report.

Table 3.3: Comparison between theoretical and experimental counting sequences.

8. Switch OFF the Digital Trainer Kit.

4.0 RESULT
5.0 CONCLUSION

In this experiment,we able to conclude that we can design a counter by using flip-
flop.We follow the procedure one by one to construct a circuit by using 7474 IC
which is D flip-flop and 7476 IC for J-K flip-flop.By knowing the functions of the pin
we able to assembly the circuit on breadboard.While designing the circuit we learn
more about the flip-flop and the operations of the IC by looking to the
schematic.Once we done designing the circuit we make sure that there is no short
circuit between the components so we use multimeter for a continuity check.Lastly,
we record the details in our report and we learn that comparison between theorotical
and experimental counting sequences.