EEEB2014 Sem.

1 22/23 Differential Amplifier with Active Load

Chapter 11: (Part 3) Differential Amplifier with Active load

• Active load: transistor current-source in place of resistive load.

o Transistors biased at Q-point in the forward active mode
o For BJT device:
• Δ IC due to diff-pair → Δ VCE → proportional to RO
• Similar for MOSFET for Δ ID and Δ VDS
o Ro > discrete resistive load (e.g RC or RD):
• ↑ Small-signal voltage gain

A) BJT diff-amp with active load

Figure: differential amplifier with

active load:
• Q1 & Q2: differential pair
biased with constant current
source IQ
• Q3 & Q4: load circuit
• One sided output from
collector of Q2 & Q4

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EEEB2014 Sem.1 22/23 Differential Amplifier with Active Load
i) Active load: balanced condition
• Figure: BJT diff-amp with:
o three-transistor active-load
o second gain-stage
• If gain-stage not connected:
o Assume: matched transistors & pure
common-mode signals
→ vB1 = vB2 = vcm (current IQ splits
evenly)
o Neglect base currents, I4= I3 through
the current source circuit
o With no load at output,
I1=I2=I3=I4=IQ/2

• Actual case:
o Base currents not zero & second amplifier stage connected at diff-
amp output
▪ IO is the dc bias current from the gain stage
o Assume: all transistor matched, β are equal & vB1 = vB2 = vcm,
current IQ splits evenly and I1=I2.
o To ensure Q2 & Q4 biased in the forward-active mode, the dc
currents must be balanced, or I3=I4.
I3 I4
I E 5 = I B3 + I B 4 = +
 
I I +I
Then I B 5 = 1 +  =  (1 +  )
E5 3 4

If base currents and IO are small, then I 3 + I 4  I Q

IQ
Therefore I B5 
 (1 +  )

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o For the circuit to be balanced, i.e. for I1=I2 and I3=I4
IQ
I O = I B5 =
 (1 +  )

→ Design & biasing of second gain stage is important.

▪ Example: Darlington pair
ii) Small-signal analysis of BJT active load

• Figure: Differential amplifier:

o Three-transistor active load
o RL : small-signal input
resistance of second gain
stage
• Pure differential input signal:
o produces a signal collector
current i1 = ( g m vd ) / 2 ,
o Neglect base currents, signal
current i3=i1 induced in Q3
o current mirror produces
signal current i4=i3.

→ In Q2 , input signal produces signal current i2 = ( g m vd ) / 2 with the

direction shown.
• The two signal currents, i2 and i4, add to produce a signal current in
the load resistance RL.

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iii) Output voltage & Differential gain

To determine the output voltage, need to consider the equivalent small-

signal collector-emitter output circuit of Figure (a).

Rout=ro2||ro4
Rout

From Figure (b), output voltage is

g v 
vo = 2 m d (ro 2 ro 4 RL )
 2 
The small-signal differential-mode gain is
v
Ad = o = g m (ro 2 ro 4 RL ) = g m ( Rout RL )
vd

iv) Output resistance

• Output resistance looking back into the common collector node is
Rout = ro 2 ro 4 .
• To minimize loading effect, RL> Rout.

# Example 11.10
# Ex 11.10
# TYU 11.11 to 11.14
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B) MOSFET diff-amp with active load

Figure: differential amplifier with

active load:
• M1 & M2: nmos differential pair
biased with constant current
source IQ
• M3 & M4: load circuit
• One sided output from drain of
M2 & M4

Pure common-mode signal, v1=v2=vcm:

o IQ splits evenly between M1
& M2.
→ no gate currents, iD1=iD2 and
iD3=iD4

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i) Small-signal analysis of MOSFET active load
• Small differential-mode input voltage vd = v1-v2 applied:
IQ IQ g mvd
id 1 = + id and id 2 = − id , where id =
2 2 2

IQ
• M1 and M3 in series, iD 3 = iD1 = + id
2
IQ
i =
• Current mirror of M3 and M4 produces D 4 D 3 2 + id
i =

Rout
Rout

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EEEB2014 Sem.1 22/23 Differential Amplifier with Active Load

Rout
Rout=ro2||ro4

• Figure (a): ac equivalent circuit of the drain node of M 2 and M4

o output terminal is open circuit, from Figure (b):

g v 
vo = 2 m d (ro 2 ro 4 )
 2 

o The small-signal differential-mode gain is

vo
Ad = = g m ( ro 2 ro 4 ) = g m Rout
vd

→ recall that g m = 2 K n I DQ = 2 K n I Q where IDQ= ID1= ID2=IQ/2

# Design example 11.11

# Ex 11.11
# TYU 11.15
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ii) MOSFET Diff-Amp with Cascode Active Load

• Differential gain can be increased if the small-signal output

resistance Rout looking into the active load transistor is increased.
o Cascode active load,
Rcascode  g m 4 ro 4 ro 6
o Rout=Rcascode||ro2

vo
Ad = = g m1Rout = g m1 (ro 2 Rcascode )
vd
Rcascode

# Example 11.12, Ex 11.12

iii) MOSFET Cascode Diff-Amp with Cascode Active Load

• Cascode diff-amp & active load to

further increase gain.

vo
Ad = = g m1 ( Ro 4 Ro 6 )
vd

RO 4  g m ro 2 ro 4 and RO 6  g m ro 6 ro8

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